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58 #ifndef __ARCH_X86_TYPES_HH__
59 #define __ARCH_X86_TYPES_HH__
64 #include "base/bitunion.hh"
65 #include "base/cprintf.hh"
69 //This really determines how many bytes are passed to the predecoder.
70 typedef uint64_t MachInst;
88 BitUnion8(LegacyPrefixVector)
89 Bitfield<7, 4> decodeVal;
95 //There can be only one segment override, so they share the
96 //first 3 bits in the legacyPrefixes bitfield.
98 EndBitUnion(LegacyPrefixVector)
121 Bitfield<2,0> bottom3;
124 BitUnion8(OperatingMode)
126 Bitfield<2,0> submode;
127 EndBitUnion(OperatingMode)
142 //The intermediate structure the x86 predecoder returns.
146 LegacyPrefixVector legacy;
148 //This holds all of the bytes of the opcode
151 //The number of bytes in this opcode. Right now, we ignore that
152 //this can be 3 in some cases
154 //The first byte detected in a 2+ byte opcode. Should be 0xF0.
156 //The second byte detected in a 3+ byte opcode. Could be 0xF0 for
157 //3dnow instructions, or 0x38-0x3F for some SSE instructions.
159 //The main opcode byte. The highest addressed byte in the opcode.
167 uint64_t displacement;
169 //The effective operand size.
171 //The effective address size.
173 //The effective stack size.
180 inline static std::ostream &
181 operator << (std::ostream & os, const ExtMachInst & emi)
183 ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
184 "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
185 "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
186 "modRM = %#x,\n\tsib = %#x,\n\t"
187 "immediate = %#x,\n\tdisplacement = %#x\n}\n",
188 (uint8_t)emi.legacy, (uint8_t)emi.rex,
189 emi.opcode.num, (uint8_t)emi.opcode.op,
190 emi.opcode.prefixA, emi.opcode.prefixB,
191 (uint8_t)emi.modRM, (uint8_t)emi.sib,
192 emi.immediate, emi.displacement);
197 operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
199 if(emi1.legacy != emi2.legacy)
201 if(emi1.rex != emi2.rex)
203 if(emi1.opcode.num != emi2.opcode.num)
205 if(emi1.opcode.op != emi2.opcode.op)
207 if(emi1.opcode.prefixA != emi2.opcode.prefixA)
209 if(emi1.opcode.prefixB != emi2.opcode.prefixB)
211 if(emi1.modRM != emi2.modRM)
213 if(emi1.sib != emi2.sib)
215 if(emi1.immediate != emi2.immediate)
217 if(emi1.displacement != emi2.displacement)
219 if(emi1.mode != emi2.mode)
221 if(emi1.opSize != emi2.opSize)
223 if(emi1.addrSize != emi2.addrSize)
225 if(emi1.stackSize != emi2.stackSize)
230 typedef uint64_t IntReg;
231 //XXX Should this be a 128 bit structure for XMM memory ops?
232 typedef uint64_t LargestRead;
233 typedef uint64_t MiscReg;
235 //These floating point types are correct for mmx, but not
236 //technically for x87 (80 bits) or at all for xmm (128 bits)
237 typedef double FloatReg;
238 typedef uint64_t FloatRegBits;
246 //XXX This is very hypothetical. X87 instructions would need to
247 //change their "context" constantly. It's also not clear how
248 //this would be handled as far as out of order execution.
249 //Maybe x87 instructions are in order?
255 typedef int RegContextVal;
257 typedef uint8_t RegIndex;
260 #endif // __ARCH_X86_TYPES_HH__