src/arch/x86/types.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
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  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_TYPES_HH__
  59 #define __ARCH_X86_TYPES_HH__
  60
  61 #include <inttypes.h>
  62 #include <iostream>
  63
  64 namespace X86ISA
  65 {
  66     //This really determines how many bytes are passed to the predecoder.
  67     typedef uint64_t MachInst;
  68
  69     enum Prefixes {
  70         NoOverride = 0,
  71         CSOverride = 1,
  72         DSOverride = 2,
  73         ESOverride = 3,
  74         FSOverride = 4,
  75         GSOverride = 5,
  76         SSOverride = 6,
  77         //The Rex prefix obviously doesn't fit in with the above, but putting
  78         //it here lets us save double the space the enums take up.
  79         Rex = 7,
  80         //There can be only one segment override, so they share the
  81         //first 3 bits in the legacyPrefixes bitfield.
  82         SegmentOverride = 0x7,
  83         OperandSizeOverride = 8,
  84         AddressSizeOverride = 16,
  85         Lock = 32,
  86         Rep = 64,
  87         Repne = 128
  88     };
  89
  90     //The intermediate structure the x86 predecoder returns.
  91     struct ExtMachInst
  92     {
  93       public: //XXX These should be hidden in the future
  94
  95         uint8_t legacyPrefixes;
  96         uint8_t rexPrefix;
  97         //Right now, we ignore that this can be 3 in
  98         //some cases
  99         uint8_t numOpcodes;
 100         //This will need to be decoded specially later
 101         bool is3dnow;
 102         uint8_t opcode;
 103         uint64_t immediate;
 104         uint64_t displacement;
 105
 106       public:
 107
 108         //These are to pacify the decoder for now. This will go away once
 109         //it can handle non integer inputs, and in the mean time allow me to
 110         //excercise the predecoder a little.
 111         operator unsigned int()
 112         {
 113             return 0;
 114         }
 115
 116         ExtMachInst(unsigned int)
 117         {;}
 118
 119         ExtMachInst()
 120         {;}
 121     };
 122
 123     inline static std::ostream &
 124         operator << (std::ostream & os, const ExtMachInst & emi)
 125     {
 126         os << "{X86 ExtMachInst}";
 127         return os;
 128     }
 129
 130     inline static bool
 131         operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
 132     {
 133         //Since this is empty, it's always equal
 134         return true;
 135     }
 136
 137     typedef uint64_t IntReg;
 138     //XXX Should this be a 128 bit structure for XMM memory ops?
 139     typedef uint64_t LargestRead;
 140     typedef uint64_t MiscReg;
 141
 142     //These floating point types are correct for mmx, but not
 143     //technically for x87 (80 bits) or at all for xmm (128 bits)
 144     typedef double FloatReg;
 145     typedef uint64_t FloatRegBits;
 146     typedef union
 147     {
 148         IntReg intReg;
 149         FloatReg fpReg;
 150         MiscReg ctrlReg;
 151     } AnyReg;
 152
 153     //XXX This is very hypothetical. X87 instructions would need to
 154     //change their "context" constantly. It's also not clear how
 155     //this would be handled as far as out of order execution.
 156     //Maybe x87 instructions are in order?
 157     enum RegContextParam
 158     {
 159         CONTEXT_X87_TOP
 160     };
 161
 162     typedef int RegContextVal;
 163
 164     typedef uint8_t RegIndex;
 165 };
 166
 167 #endif // __ARCH_X86_TYPES_HH__