src/arch/x86/types.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
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  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_TYPES_HH__
  59 #define __ARCH_X86_TYPES_HH__
  60
  61 #include <inttypes.h>
  62 #include <iostream>
  63
  64 #include "base/bitunion.hh"
  65 #include "base/cprintf.hh"
  66
  67 namespace X86ISA
  68 {
  69     //This really determines how many bytes are passed to the predecoder.
  70     typedef uint64_t MachInst;
  71
  72     enum Prefixes {
  73         NoOverride,
  74         CSOverride,
  75         DSOverride,
  76         ESOverride,
  77         FSOverride,
  78         GSOverride,
  79         SSOverride,
  80         RexPrefix,
  81         OperandSizeOverride,
  82         AddressSizeOverride,
  83         Lock,
  84         Rep,
  85         Repne
  86     };
  87
  88     BitUnion8(LegacyPrefixVector)
  89         Bitfield<7, 4> decodeVal;
  90         Bitfield<7> repne;
  91         Bitfield<6> rep;
  92         Bitfield<5> lock;
  93         Bitfield<4> op;
  94         Bitfield<3> addr;
  95         //There can be only one segment override, so they share the
  96         //first 3 bits in the legacyPrefixes bitfield.
  97         Bitfield<2,0> seg;
  98     EndBitUnion(LegacyPrefixVector)
  99
 100     BitUnion8(ModRM)
 101         Bitfield<7,6> mod;
 102         Bitfield<5,3> reg;
 103         Bitfield<2,0> rm;
 104     EndBitUnion(ModRM)
 105
 106     BitUnion8(Sib)
 107         Bitfield<7,6> scale;
 108         Bitfield<5,3> index;
 109         Bitfield<2,0> base;
 110     EndBitUnion(Sib)
 111
 112     BitUnion8(Rex)
 113         Bitfield<3> w;
 114         Bitfield<2> r;
 115         Bitfield<1> x;
 116         Bitfield<0> b;
 117     EndBitUnion(Rex)
 118
 119     BitUnion8(Opcode)
 120         Bitfield<7,3> top5;
 121         Bitfield<2,0> bottom3;
 122     EndBitUnion(Opcode)
 123
 124     BitUnion8(OperatingMode)
 125         Bitfield<3> mode;
 126         Bitfield<2,0> submode;
 127     EndBitUnion(OperatingMode)
 128
 129     enum X86Mode {
 130         LongMode,
 131         LegacyMode
 132     };
 133
 134     enum X86SubMode {
 135         SixtyFourBitMode,
 136         CompatabilityMode,
 137         ProtectedMode,
 138         Virtual8086Mode,
 139         RealMode
 140     };
 141
 142     //The intermediate structure the x86 predecoder returns.
 143     struct ExtMachInst
 144     {
 145         //Prefixes
 146         LegacyPrefixVector legacy;
 147         Rex rex;
 148         //This holds all of the bytes of the opcode
 149         struct
 150         {
 151             //The number of bytes in this opcode. Right now, we ignore that
 152             //this can be 3 in some cases
 153             uint8_t num;
 154             //The first byte detected in a 2+ byte opcode. Should be 0xF0.
 155             uint8_t prefixA;
 156             //The second byte detected in a 3+ byte opcode. Could be 0xF0 for
 157             //3dnow instructions, or 0x38-0x3F for some SSE instructions.
 158             uint8_t prefixB;
 159             //The main opcode byte. The highest addressed byte in the opcode.
 160             Opcode op;
 161         } opcode;
 162         //Modifier bytes
 163         ModRM modRM;
 164         Sib sib;
 165         //Immediate fields
 166         uint64_t immediate;
 167         uint64_t displacement;
 168
 169         //The effective operand size.
 170         uint8_t opSize;
 171         //The effective address size.
 172         uint8_t addrSize;
 173         //The effective stack size.
 174         uint8_t stackSize;
 175
 176         //Mode information
 177         OperatingMode mode;
 178     };
 179
 180     inline static std::ostream &
 181         operator << (std::ostream & os, const ExtMachInst & emi)
 182     {
 183         ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
 184                      "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
 185                            "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
 186                      "modRM = %#x,\n\tsib = %#x,\n\t"
 187                      "immediate = %#x,\n\tdisplacement = %#x\n}\n",
 188                      (uint8_t)emi.legacy, (uint8_t)emi.rex,
 189                      emi.opcode.num, (uint8_t)emi.opcode.op,
 190                      emi.opcode.prefixA, emi.opcode.prefixB,
 191                      (uint8_t)emi.modRM, (uint8_t)emi.sib,
 192                      emi.immediate, emi.displacement);
 193         return os;
 194     }
 195
 196     inline static bool
 197         operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
 198     {
 199         if(emi1.legacy != emi2.legacy)
 200             return false;
 201         if(emi1.rex != emi2.rex)
 202             return false;
 203         if(emi1.opcode.num != emi2.opcode.num)
 204             return false;
 205         if(emi1.opcode.op != emi2.opcode.op)
 206             return false;
 207         if(emi1.opcode.prefixA != emi2.opcode.prefixA)
 208             return false;
 209         if(emi1.opcode.prefixB != emi2.opcode.prefixB)
 210             return false;
 211         if(emi1.modRM != emi2.modRM)
 212             return false;
 213         if(emi1.sib != emi2.sib)
 214             return false;
 215         if(emi1.immediate != emi2.immediate)
 216             return false;
 217         if(emi1.displacement != emi2.displacement)
 218             return false;
 219         if(emi1.mode != emi2.mode)
 220             return false;
 221         if(emi1.opSize != emi2.opSize)
 222             return false;
 223         if(emi1.addrSize != emi2.addrSize)
 224             return false;
 225         if(emi1.stackSize != emi2.stackSize)
 226             return false;
 227         return true;
 228     }
 229
 230     typedef uint64_t IntReg;
 231     //XXX Should this be a 128 bit structure for XMM memory ops?
 232     typedef uint64_t LargestRead;
 233     typedef uint64_t MiscReg;
 234
 235     //These floating point types are correct for mmx, but not
 236     //technically for x87 (80 bits) or at all for xmm (128 bits)
 237     typedef double FloatReg;
 238     typedef uint64_t FloatRegBits;
 239     typedef union
 240     {
 241         IntReg intReg;
 242         FloatReg fpReg;
 243         MiscReg ctrlReg;
 244     } AnyReg;
 245
 246     //XXX This is very hypothetical. X87 instructions would need to
 247     //change their "context" constantly. It's also not clear how
 248     //this would be handled as far as out of order execution.
 249     //Maybe x87 instructions are in order?
 250     enum RegContextParam
 251     {
 252         CONTEXT_X87_TOP
 253     };
 254
 255     typedef int RegContextVal;
 256
 257     typedef uint8_t RegIndex;
 258 };
 259
 260 #endif // __ARCH_X86_TYPES_HH__