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58 #include "arch/x86/intregs.hh"
59 #include "arch/x86/miscregs.hh"
60 #include "arch/x86/segmentregs.hh"
61 #include "arch/x86/utility.hh"
62 #include "arch/x86/x86_traits.hh"
66 uint64_t getArgument(ThreadContext
*tc
, int number
, bool fp
) {
68 panic("getArgument() not implemented for x86!\n");
70 panic("getArgument() only implemented for FULL_SYSTEM\n");
76 void initCPU(ThreadContext
*tc
, int cpuId
)
78 // The otherwise unmodified integer registers should be set to 0.
79 for (int index
= 0; index
< NUM_INTREGS
; index
++) {
80 tc
->setIntReg(index
, 0);
83 // These next two loops zero internal microcode and implicit registers.
84 // They aren't specified by the ISA but are used internally by M5's
86 for (int index
= 0; index
< NumMicroIntRegs
; index
++) {
87 tc
->setIntReg(INTREG_MICRO(index
), 0);
90 for (int index
= 0; index
< NumImplicitIntRegs
; index
++) {
91 tc
->setIntReg(INTREG_IMPLICIT(index
), 0);
94 // Set integer register EAX to 0 to indicate that the optional BIST
95 // passed. No BIST actually runs, but software may still check this
96 // register for errors.
97 tc
->setIntReg(INTREG_RAX
, 0);
99 //The following values are dictated by the architecture for after a RESET#
100 tc
->setMiscReg(MISCREG_CR0
, 0x0000000060000010);
101 tc
->setMiscReg(MISCREG_CR2
, 0);
102 tc
->setMiscReg(MISCREG_CR3
, 0);
103 tc
->setMiscReg(MISCREG_CR4
, 0);
104 tc
->setMiscReg(MISCREG_CR8
, 0);
106 tc
->setMiscReg(MISCREG_RFLAGS
, 0x0000000000000002);
108 tc
->setMiscReg(MISCREG_EFER
, 0);
110 SegAttr dataAttr
= 0;
111 dataAttr
.writable
= 1;
112 dataAttr
.readable
= 1;
113 dataAttr
.expandDown
= 0;
115 dataAttr
.defaultSize
= 0;
117 for (int seg
= 0; seg
!= NUM_SEGMENTREGS
; seg
++) {
118 tc
->setMiscReg(MISCREG_SEG_SEL(seg
), 0);
119 tc
->setMiscReg(MISCREG_SEG_BASE(seg
), 0);
120 tc
->setMiscReg(MISCREG_SEG_LIMIT(seg
), 0xffff);
121 tc
->setMiscReg(MISCREG_SEG_ATTR(seg
), dataAttr
);
124 SegAttr codeAttr
= 0;
125 codeAttr
.writable
= 0;
126 codeAttr
.readable
= 1;
127 codeAttr
.expandDown
= 0;
129 codeAttr
.defaultSize
= 0;
131 tc
->setMiscReg(MISCREG_CS
, 0xf000);
132 tc
->setMiscReg(MISCREG_CS_BASE
, 0x00000000ffff0000);
133 // This has the base value pre-added.
134 tc
->setMiscReg(MISCREG_CS_LIMIT
, 0xffffffff);
135 tc
->setMiscReg(MISCREG_CS_ATTR
, codeAttr
);
137 tc
->setPC(0x000000000000fff0 +
138 tc
->readMiscReg(MISCREG_CS_BASE
));
139 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
141 tc
->setMiscReg(MISCREG_GDTR_BASE
, 0);
142 tc
->setMiscReg(MISCREG_GDTR_LIMIT
, 0xffff);
144 tc
->setMiscReg(MISCREG_IDTR_BASE
, 0);
145 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
147 tc
->setMiscReg(MISCREG_LDTR
, 0);
148 tc
->setMiscReg(MISCREG_LDTR_BASE
, 0);
149 tc
->setMiscReg(MISCREG_LDTR_LIMIT
, 0xffff);
150 tc
->setMiscReg(MISCREG_LDTR_ATTR
, 0);
152 tc
->setMiscReg(MISCREG_TR
, 0);
153 tc
->setMiscReg(MISCREG_TR_BASE
, 0);
154 tc
->setMiscReg(MISCREG_TR_LIMIT
, 0xffff);
155 tc
->setMiscReg(MISCREG_TR_ATTR
, 0);
157 // This value should be the family/model/stepping of the processor.
158 // (page 418). It should be consistent with the value from CPUID, but the
159 // actual value probably doesn't matter much.
160 tc
->setIntReg(INTREG_RDX
, 0);
162 // TODO initialize x87, 64 bit, and 128 bit media state
164 tc
->setMiscReg(MISCREG_MTRRCAP
, 0x0508);
165 for (int i
= 0; i
< 8; i
++) {
166 tc
->setMiscReg(MISCREG_MTRR_PHYS_BASE(i
), 0);
167 tc
->setMiscReg(MISCREG_MTRR_PHYS_MASK(i
), 0);
169 tc
->setMiscReg(MISCREG_MTRR_FIX_64K_00000
, 0);
170 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_80000
, 0);
171 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_A0000
, 0);
172 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C0000
, 0);
173 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C8000
, 0);
174 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D0000
, 0);
175 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D8000
, 0);
176 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E0000
, 0);
177 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E8000
, 0);
178 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F0000
, 0);
179 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F8000
, 0);
181 tc
->setMiscReg(MISCREG_DEF_TYPE
, 0);
183 tc
->setMiscReg(MISCREG_MCG_CAP
, 0x104);
184 tc
->setMiscReg(MISCREG_MCG_STATUS
, 0);
185 tc
->setMiscReg(MISCREG_MCG_CTL
, 0);
187 for (int i
= 0; i
< 5; i
++) {
188 tc
->setMiscReg(MISCREG_MC_CTL(i
), 0);
189 tc
->setMiscReg(MISCREG_MC_STATUS(i
), 0);
190 tc
->setMiscReg(MISCREG_MC_ADDR(i
), 0);
191 tc
->setMiscReg(MISCREG_MC_MISC(i
), 0);
194 tc
->setMiscReg(MISCREG_DR0
, 0);
195 tc
->setMiscReg(MISCREG_DR1
, 0);
196 tc
->setMiscReg(MISCREG_DR2
, 0);
197 tc
->setMiscReg(MISCREG_DR3
, 0);
199 tc
->setMiscReg(MISCREG_DR6
, 0x00000000ffff0ff0);
200 tc
->setMiscReg(MISCREG_DR7
, 0x0000000000000400);
202 tc
->setMiscReg(MISCREG_TSC
, 0);
203 tc
->setMiscReg(MISCREG_TSC_AUX
, 0);
205 for (int i
= 0; i
< 4; i
++) {
206 tc
->setMiscReg(MISCREG_PERF_EVT_SEL(i
), 0);
207 tc
->setMiscReg(MISCREG_PERF_EVT_CTR(i
), 0);
210 tc
->setMiscReg(MISCREG_STAR
, 0);
211 tc
->setMiscReg(MISCREG_LSTAR
, 0);
212 tc
->setMiscReg(MISCREG_CSTAR
, 0);
214 tc
->setMiscReg(MISCREG_SF_MASK
, 0);
216 tc
->setMiscReg(MISCREG_KERNEL_GS_BASE
, 0);
218 tc
->setMiscReg(MISCREG_SYSENTER_CS
, 0);
219 tc
->setMiscReg(MISCREG_SYSENTER_ESP
, 0);
220 tc
->setMiscReg(MISCREG_SYSENTER_EIP
, 0);
222 tc
->setMiscReg(MISCREG_PAT
, 0x0007040600070406);
224 tc
->setMiscReg(MISCREG_SYSCFG
, 0x20601);
226 tc
->setMiscReg(MISCREG_IORR_BASE0
, 0);
227 tc
->setMiscReg(MISCREG_IORR_BASE1
, 0);
229 tc
->setMiscReg(MISCREG_IORR_MASK0
, 0);
230 tc
->setMiscReg(MISCREG_IORR_MASK1
, 0);
232 tc
->setMiscReg(MISCREG_TOP_MEM
, 0x4000000);
233 tc
->setMiscReg(MISCREG_TOP_MEM2
, 0x0);
235 tc
->setMiscReg(MISCREG_DEBUG_CTL_MSR
, 0);
236 tc
->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP
, 0);
237 tc
->setMiscReg(MISCREG_LAST_BRANCH_TO_IP
, 0);
238 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP
, 0);
239 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP
, 0);
241 // Invalidate the caches (this should already be done for us)
243 // TODO Turn on the APIC. This should be handled elsewhere but it isn't
244 // currently being handled at all.
246 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
248 tc
->setMiscReg(MISCREG_VM_CR
, 0);
249 tc
->setMiscReg(MISCREG_IGNNE
, 0);
250 tc
->setMiscReg(MISCREG_SMM_CTL
, 0);
251 tc
->setMiscReg(MISCREG_VM_HSAVE_PA
, 0);
256 void startupCPU(ThreadContext
*tc
, int cpuId
)
259 // This is the boot strap processor (BSP). Initialize it to look like
260 // the boot loader has just turned control over to the 64 bit OS.
262 // Enable paging, turn on long mode, etc.
266 // This is an application processor (AP). It should be initialized to
267 // look like only the BIOS POST has run on it and put then put it into
272 } //namespace X86_ISA