2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2011 Advanced Micro Devices, Inc.
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
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13 * modified or unmodified, in source code or in binary form.
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19 * redistributions in binary form must reproduce the above copyright
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24 * this software without specific prior written permission.
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41 #include "arch/x86/interrupts.hh"
42 #include "arch/x86/registers.hh"
43 #include "arch/x86/tlb.hh"
44 #include "arch/x86/utility.hh"
45 #include "arch/x86/x86_traits.hh"
46 #include "cpu/base.hh"
47 #include "sim/system.hh"
52 getArgument(ThreadContext
*tc
, int &number
, uint16_t size
, bool fp
)
54 panic("getArgument() not implemented for x86!\n");
58 void initCPU(ThreadContext
*tc
, int cpuId
)
60 // This function is essentially performing a reset. The actual INIT
61 // interrupt does a subset of this, so we'll piggyback on some of its
63 InitInterrupt
init(0);
66 PCState pc
= tc
->pcState();
71 // These next two loops zero internal microcode and implicit registers.
72 // They aren't specified by the ISA but are used internally by M5's
74 for (int index
= 0; index
< NumMicroIntRegs
; index
++) {
75 tc
->setIntReg(INTREG_MICRO(index
), 0);
78 for (int index
= 0; index
< NumImplicitIntRegs
; index
++) {
79 tc
->setIntReg(INTREG_IMPLICIT(index
), 0);
82 // Set integer register EAX to 0 to indicate that the optional BIST
83 // passed. No BIST actually runs, but software may still check this
84 // register for errors.
85 tc
->setIntReg(INTREG_RAX
, 0);
87 tc
->setMiscReg(MISCREG_CR0
, 0x0000000060000010ULL
);
88 tc
->setMiscReg(MISCREG_CR8
, 0);
90 // TODO initialize x87, 64 bit, and 128 bit media state
92 tc
->setMiscReg(MISCREG_MTRRCAP
, 0x0508);
93 for (int i
= 0; i
< 8; i
++) {
94 tc
->setMiscReg(MISCREG_MTRR_PHYS_BASE(i
), 0);
95 tc
->setMiscReg(MISCREG_MTRR_PHYS_MASK(i
), 0);
97 tc
->setMiscReg(MISCREG_MTRR_FIX_64K_00000
, 0);
98 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_80000
, 0);
99 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_A0000
, 0);
100 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C0000
, 0);
101 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C8000
, 0);
102 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D0000
, 0);
103 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D8000
, 0);
104 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E0000
, 0);
105 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E8000
, 0);
106 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F0000
, 0);
107 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F8000
, 0);
109 tc
->setMiscReg(MISCREG_DEF_TYPE
, 0);
111 tc
->setMiscReg(MISCREG_MCG_CAP
, 0x104);
112 tc
->setMiscReg(MISCREG_MCG_STATUS
, 0);
113 tc
->setMiscReg(MISCREG_MCG_CTL
, 0);
115 for (int i
= 0; i
< 5; i
++) {
116 tc
->setMiscReg(MISCREG_MC_CTL(i
), 0);
117 tc
->setMiscReg(MISCREG_MC_STATUS(i
), 0);
118 tc
->setMiscReg(MISCREG_MC_ADDR(i
), 0);
119 tc
->setMiscReg(MISCREG_MC_MISC(i
), 0);
122 tc
->setMiscReg(MISCREG_TSC
, 0);
123 tc
->setMiscReg(MISCREG_TSC_AUX
, 0);
125 for (int i
= 0; i
< 4; i
++) {
126 tc
->setMiscReg(MISCREG_PERF_EVT_SEL(i
), 0);
127 tc
->setMiscReg(MISCREG_PERF_EVT_CTR(i
), 0);
130 tc
->setMiscReg(MISCREG_STAR
, 0);
131 tc
->setMiscReg(MISCREG_LSTAR
, 0);
132 tc
->setMiscReg(MISCREG_CSTAR
, 0);
134 tc
->setMiscReg(MISCREG_SF_MASK
, 0);
136 tc
->setMiscReg(MISCREG_KERNEL_GS_BASE
, 0);
138 tc
->setMiscReg(MISCREG_SYSENTER_CS
, 0);
139 tc
->setMiscReg(MISCREG_SYSENTER_ESP
, 0);
140 tc
->setMiscReg(MISCREG_SYSENTER_EIP
, 0);
142 tc
->setMiscReg(MISCREG_PAT
, 0x0007040600070406ULL
);
144 tc
->setMiscReg(MISCREG_SYSCFG
, 0x20601);
146 tc
->setMiscReg(MISCREG_IORR_BASE0
, 0);
147 tc
->setMiscReg(MISCREG_IORR_BASE1
, 0);
149 tc
->setMiscReg(MISCREG_IORR_MASK0
, 0);
150 tc
->setMiscReg(MISCREG_IORR_MASK1
, 0);
152 tc
->setMiscReg(MISCREG_TOP_MEM
, 0x4000000);
153 tc
->setMiscReg(MISCREG_TOP_MEM2
, 0x0);
155 tc
->setMiscReg(MISCREG_DEBUG_CTL_MSR
, 0);
156 tc
->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP
, 0);
157 tc
->setMiscReg(MISCREG_LAST_BRANCH_TO_IP
, 0);
158 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP
, 0);
159 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP
, 0);
161 // Invalidate the caches (this should already be done for us)
163 LocalApicBase lApicBase
= 0;
164 lApicBase
.base
= 0xFEE00000 >> 12;
165 lApicBase
.enable
= 1;
166 lApicBase
.bsp
= (cpuId
== 0);
167 tc
->setMiscReg(MISCREG_APIC_BASE
, lApicBase
);
169 Interrupts
* interrupts
= dynamic_cast<Interrupts
*>(
170 tc
->getCpuPtr()->getInterruptController());
173 interrupts
->setRegNoEffect(APIC_ID
, cpuId
<< 24);
175 interrupts
->setRegNoEffect(APIC_VERSION
, (5 << 16) | 0x14);
177 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
179 tc
->setMiscReg(MISCREG_VM_CR
, 0);
180 tc
->setMiscReg(MISCREG_IGNNE
, 0);
181 tc
->setMiscReg(MISCREG_SMM_CTL
, 0);
182 tc
->setMiscReg(MISCREG_VM_HSAVE_PA
, 0);
185 void startupCPU(ThreadContext
*tc
, int cpuId
)
187 if (cpuId
== 0 || !FullSystem
) {
188 tc
->activate(Cycles(0));
190 // This is an application processor (AP). It should be initialized to
191 // look like only the BIOS POST has run on it and put then put it into
193 tc
->suspend(Cycles(0));
198 copyMiscRegs(ThreadContext
*src
, ThreadContext
*dest
)
200 // This function assumes no side effects other than TLB invalidation
201 // need to be considered while copying state. That will likely not be
202 // true in the future.
203 for (int i
= 0; i
< NUM_MISCREGS
; ++i
) {
204 if ( ( i
!= MISCREG_CR1
&&
205 !(i
> MISCREG_CR4
&& i
< MISCREG_CR8
) &&
206 !(i
> MISCREG_CR8
&& i
<= MISCREG_CR15
) ) == false) {
209 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
212 // The TSC has to be updated with side-effects if the CPUs in a
213 // CPU switch have different frequencies.
214 dest
->setMiscReg(MISCREG_TSC
, src
->readMiscReg(MISCREG_TSC
));
216 dest
->getITBPtr()->flushAll();
217 dest
->getDTBPtr()->flushAll();
221 copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
224 for (int i
= 0; i
< NumIntRegs
; ++i
)
225 dest
->setIntReg(i
, src
->readIntReg(i
));
227 for (int i
= 0; i
< NumFloatRegs
; ++i
)
228 dest
->setFloatRegBits(i
, src
->readFloatRegBits(i
));
229 copyMiscRegs(src
, dest
);
230 dest
->pcState(src
->pcState());
234 skipFunction(ThreadContext
*tc
)
236 panic("Not implemented for x86\n");
240 getRFlags(ThreadContext
*tc
)
242 const uint64_t ncc_flags(tc
->readMiscRegNoEffect(MISCREG_RFLAGS
));
243 const uint64_t cc_flags(tc
->readIntReg(X86ISA::INTREG_PSEUDO(0)));
244 const uint64_t cfof_bits(tc
->readIntReg(X86ISA::INTREG_PSEUDO(1)));
245 const uint64_t df_bit(tc
->readIntReg(X86ISA::INTREG_PSEUDO(2)));
246 // ecf (PSEUDO(3)) & ezf (PSEUDO(4)) are only visible to
247 // microcode, so we can safely ignore them.
249 // Reconstruct the real rflags state, mask out internal flags, and
250 // make sure reserved bits have the expected values.
251 return ((ncc_flags
| cc_flags
| cfof_bits
| df_bit
) & 0x3F7FD5)
256 setRFlags(ThreadContext
*tc
, uint64_t val
)
258 tc
->setIntReg(X86ISA::INTREG_PSEUDO(0), val
& ccFlagMask
);
259 tc
->setIntReg(X86ISA::INTREG_PSEUDO(1), val
& cfofMask
);
260 tc
->setIntReg(X86ISA::INTREG_PSEUDO(2), val
& DFBit
);
262 // Internal microcode registers (ECF & EZF)
263 tc
->setIntReg(X86ISA::INTREG_PSEUDO(3), 0);
264 tc
->setIntReg(X86ISA::INTREG_PSEUDO(4), 0);
266 // Update the RFLAGS misc reg with whatever didn't go into the
268 tc
->setMiscReg(MISCREG_RFLAGS
, val
& ~(ccFlagMask
| cfofMask
| DFBit
));
272 genX87Tags(uint16_t ftw
, uint8_t top
, int8_t spm
)
274 const uint8_t new_top((top
+ spm
+ 8) % 8);
277 // Removing elements from the stack. Flag the elements as empty.
278 for (int i
= top
; i
!= new_top
; i
= (i
+ 1 + 8) % 8)
279 ftw
|= 0x3 << (2 * i
);
280 } else if (spm
< 0) {
281 // Adding elements to the stack. Flag the new elements as
282 // valid. We should ideally decode them and "do the right
284 for (int i
= new_top
; i
!= top
; i
= (i
+ 1 + 8) % 8)
285 ftw
&= ~(0x3 << (2 * i
));
291 } // namespace X86_ISA