2 * Copyright (c) 2007 The Hewlett-Packard Development Company
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40 #include "config/full_system.hh"
43 #include "arch/x86/interrupts.hh"
45 #include "arch/x86/intregs.hh"
46 #include "arch/x86/miscregs.hh"
47 #include "arch/x86/segmentregs.hh"
48 #include "arch/x86/utility.hh"
49 #include "arch/x86/x86_traits.hh"
50 #include "cpu/base.hh"
51 #include "sim/system.hh"
55 uint64_t getArgument(ThreadContext
*tc
, int number
, bool fp
) {
57 panic("getArgument() not implemented for x86!\n");
59 panic("getArgument() only implemented for FULL_SYSTEM\n");
65 void initCPU(ThreadContext
*tc
, int cpuId
)
67 // This function is essentially performing a reset. The actual INIT
68 // interrupt does a subset of this, so we'll piggyback on some of its
70 InitInterrupt
init(0);
74 tc
->setNextMicroPC(1);
76 // These next two loops zero internal microcode and implicit registers.
77 // They aren't specified by the ISA but are used internally by M5's
79 for (int index
= 0; index
< NumMicroIntRegs
; index
++) {
80 tc
->setIntReg(INTREG_MICRO(index
), 0);
83 for (int index
= 0; index
< NumImplicitIntRegs
; index
++) {
84 tc
->setIntReg(INTREG_IMPLICIT(index
), 0);
87 // Set integer register EAX to 0 to indicate that the optional BIST
88 // passed. No BIST actually runs, but software may still check this
89 // register for errors.
90 tc
->setIntReg(INTREG_RAX
, 0);
92 tc
->setMiscReg(MISCREG_CR0
, 0x0000000060000010ULL
);
93 tc
->setMiscReg(MISCREG_CR8
, 0);
95 // TODO initialize x87, 64 bit, and 128 bit media state
97 tc
->setMiscReg(MISCREG_MTRRCAP
, 0x0508);
98 for (int i
= 0; i
< 8; i
++) {
99 tc
->setMiscReg(MISCREG_MTRR_PHYS_BASE(i
), 0);
100 tc
->setMiscReg(MISCREG_MTRR_PHYS_MASK(i
), 0);
102 tc
->setMiscReg(MISCREG_MTRR_FIX_64K_00000
, 0);
103 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_80000
, 0);
104 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_A0000
, 0);
105 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C0000
, 0);
106 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C8000
, 0);
107 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D0000
, 0);
108 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D8000
, 0);
109 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E0000
, 0);
110 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E8000
, 0);
111 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F0000
, 0);
112 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F8000
, 0);
114 tc
->setMiscReg(MISCREG_DEF_TYPE
, 0);
116 tc
->setMiscReg(MISCREG_MCG_CAP
, 0x104);
117 tc
->setMiscReg(MISCREG_MCG_STATUS
, 0);
118 tc
->setMiscReg(MISCREG_MCG_CTL
, 0);
120 for (int i
= 0; i
< 5; i
++) {
121 tc
->setMiscReg(MISCREG_MC_CTL(i
), 0);
122 tc
->setMiscReg(MISCREG_MC_STATUS(i
), 0);
123 tc
->setMiscReg(MISCREG_MC_ADDR(i
), 0);
124 tc
->setMiscReg(MISCREG_MC_MISC(i
), 0);
127 tc
->setMiscReg(MISCREG_TSC
, 0);
128 tc
->setMiscReg(MISCREG_TSC_AUX
, 0);
130 for (int i
= 0; i
< 4; i
++) {
131 tc
->setMiscReg(MISCREG_PERF_EVT_SEL(i
), 0);
132 tc
->setMiscReg(MISCREG_PERF_EVT_CTR(i
), 0);
135 tc
->setMiscReg(MISCREG_STAR
, 0);
136 tc
->setMiscReg(MISCREG_LSTAR
, 0);
137 tc
->setMiscReg(MISCREG_CSTAR
, 0);
139 tc
->setMiscReg(MISCREG_SF_MASK
, 0);
141 tc
->setMiscReg(MISCREG_KERNEL_GS_BASE
, 0);
143 tc
->setMiscReg(MISCREG_SYSENTER_CS
, 0);
144 tc
->setMiscReg(MISCREG_SYSENTER_ESP
, 0);
145 tc
->setMiscReg(MISCREG_SYSENTER_EIP
, 0);
147 tc
->setMiscReg(MISCREG_PAT
, 0x0007040600070406ULL
);
149 tc
->setMiscReg(MISCREG_SYSCFG
, 0x20601);
151 tc
->setMiscReg(MISCREG_IORR_BASE0
, 0);
152 tc
->setMiscReg(MISCREG_IORR_BASE1
, 0);
154 tc
->setMiscReg(MISCREG_IORR_MASK0
, 0);
155 tc
->setMiscReg(MISCREG_IORR_MASK1
, 0);
157 tc
->setMiscReg(MISCREG_TOP_MEM
, 0x4000000);
158 tc
->setMiscReg(MISCREG_TOP_MEM2
, 0x0);
160 tc
->setMiscReg(MISCREG_DEBUG_CTL_MSR
, 0);
161 tc
->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP
, 0);
162 tc
->setMiscReg(MISCREG_LAST_BRANCH_TO_IP
, 0);
163 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP
, 0);
164 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP
, 0);
166 // Invalidate the caches (this should already be done for us)
168 LocalApicBase lApicBase
= 0;
169 lApicBase
.base
= 0xFEE00000 >> 12;
170 lApicBase
.enable
= 1;
171 lApicBase
.bsp
= (cpuId
== 0);
172 tc
->setMiscReg(MISCREG_APIC_BASE
, lApicBase
);
174 Interrupts
* interrupts
= dynamic_cast<Interrupts
*>(
175 tc
->getCpuPtr()->getInterruptController());
178 interrupts
->setRegNoEffect(APIC_ID
, cpuId
<< 24);
180 interrupts
->setRegNoEffect(APIC_VERSION
, (5 << 16) | 0x14);
182 interrupts
->setClock(tc
->getCpuPtr()->ticks(16));
184 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
186 tc
->setMiscReg(MISCREG_VM_CR
, 0);
187 tc
->setMiscReg(MISCREG_IGNNE
, 0);
188 tc
->setMiscReg(MISCREG_SMM_CTL
, 0);
189 tc
->setMiscReg(MISCREG_VM_HSAVE_PA
, 0);
194 void startupCPU(ThreadContext
*tc
, int cpuId
)
200 // This is an application processor (AP). It should be initialized to
201 // look like only the BIOS POST has run on it and put then put it into
211 copyMiscRegs(ThreadContext
*src
, ThreadContext
*dest
)
213 warn("copyMiscRegs is naively implemented for x86\n");
214 for (int i
= 0; i
< NUM_MISCREGS
; ++i
) {
215 if ( ( i
!= MISCREG_CR1
&&
216 !(i
> MISCREG_CR4
&& i
< MISCREG_CR8
) &&
217 !(i
> MISCREG_CR8
&& i
<= MISCREG_CR15
) ) == false) {
220 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
225 copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
227 panic("copyRegs not implemented for x86!\n");
230 copyMiscRegs(src
, dest
);
232 dest
->setPC(src
->readPC());
233 dest
->setNextPC(src
->readNextPC());
236 } //namespace X86_ISA