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58 #include "config/full_system.hh"
61 #include "arch/x86/interrupts.hh"
63 #include "arch/x86/intregs.hh"
64 #include "arch/x86/miscregs.hh"
65 #include "arch/x86/segmentregs.hh"
66 #include "arch/x86/utility.hh"
67 #include "arch/x86/x86_traits.hh"
68 #include "cpu/base.hh"
69 #include "sim/system.hh"
73 uint64_t getArgument(ThreadContext
*tc
, int number
, bool fp
) {
75 panic("getArgument() not implemented for x86!\n");
77 panic("getArgument() only implemented for FULL_SYSTEM\n");
83 void initCPU(ThreadContext
*tc
, int cpuId
)
85 // This function is essentially performing a reset. The actual INIT
86 // interrupt does a subset of this, so we'll piggyback on some of its
88 InitInterrupt
init(0);
92 tc
->setNextMicroPC(1);
94 // These next two loops zero internal microcode and implicit registers.
95 // They aren't specified by the ISA but are used internally by M5's
97 for (int index
= 0; index
< NumMicroIntRegs
; index
++) {
98 tc
->setIntReg(INTREG_MICRO(index
), 0);
101 for (int index
= 0; index
< NumImplicitIntRegs
; index
++) {
102 tc
->setIntReg(INTREG_IMPLICIT(index
), 0);
105 // Set integer register EAX to 0 to indicate that the optional BIST
106 // passed. No BIST actually runs, but software may still check this
107 // register for errors.
108 tc
->setIntReg(INTREG_RAX
, 0);
110 tc
->setMiscReg(MISCREG_CR0
, 0x0000000060000010ULL
);
111 tc
->setMiscReg(MISCREG_CR8
, 0);
113 // TODO initialize x87, 64 bit, and 128 bit media state
115 tc
->setMiscReg(MISCREG_MTRRCAP
, 0x0508);
116 for (int i
= 0; i
< 8; i
++) {
117 tc
->setMiscReg(MISCREG_MTRR_PHYS_BASE(i
), 0);
118 tc
->setMiscReg(MISCREG_MTRR_PHYS_MASK(i
), 0);
120 tc
->setMiscReg(MISCREG_MTRR_FIX_64K_00000
, 0);
121 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_80000
, 0);
122 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_A0000
, 0);
123 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C0000
, 0);
124 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C8000
, 0);
125 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D0000
, 0);
126 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D8000
, 0);
127 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E0000
, 0);
128 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E8000
, 0);
129 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F0000
, 0);
130 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F8000
, 0);
132 tc
->setMiscReg(MISCREG_DEF_TYPE
, 0);
134 tc
->setMiscReg(MISCREG_MCG_CAP
, 0x104);
135 tc
->setMiscReg(MISCREG_MCG_STATUS
, 0);
136 tc
->setMiscReg(MISCREG_MCG_CTL
, 0);
138 for (int i
= 0; i
< 5; i
++) {
139 tc
->setMiscReg(MISCREG_MC_CTL(i
), 0);
140 tc
->setMiscReg(MISCREG_MC_STATUS(i
), 0);
141 tc
->setMiscReg(MISCREG_MC_ADDR(i
), 0);
142 tc
->setMiscReg(MISCREG_MC_MISC(i
), 0);
145 tc
->setMiscReg(MISCREG_TSC
, 0);
146 tc
->setMiscReg(MISCREG_TSC_AUX
, 0);
148 for (int i
= 0; i
< 4; i
++) {
149 tc
->setMiscReg(MISCREG_PERF_EVT_SEL(i
), 0);
150 tc
->setMiscReg(MISCREG_PERF_EVT_CTR(i
), 0);
153 tc
->setMiscReg(MISCREG_STAR
, 0);
154 tc
->setMiscReg(MISCREG_LSTAR
, 0);
155 tc
->setMiscReg(MISCREG_CSTAR
, 0);
157 tc
->setMiscReg(MISCREG_SF_MASK
, 0);
159 tc
->setMiscReg(MISCREG_KERNEL_GS_BASE
, 0);
161 tc
->setMiscReg(MISCREG_SYSENTER_CS
, 0);
162 tc
->setMiscReg(MISCREG_SYSENTER_ESP
, 0);
163 tc
->setMiscReg(MISCREG_SYSENTER_EIP
, 0);
165 tc
->setMiscReg(MISCREG_PAT
, 0x0007040600070406ULL
);
167 tc
->setMiscReg(MISCREG_SYSCFG
, 0x20601);
169 tc
->setMiscReg(MISCREG_IORR_BASE0
, 0);
170 tc
->setMiscReg(MISCREG_IORR_BASE1
, 0);
172 tc
->setMiscReg(MISCREG_IORR_MASK0
, 0);
173 tc
->setMiscReg(MISCREG_IORR_MASK1
, 0);
175 tc
->setMiscReg(MISCREG_TOP_MEM
, 0x4000000);
176 tc
->setMiscReg(MISCREG_TOP_MEM2
, 0x0);
178 tc
->setMiscReg(MISCREG_DEBUG_CTL_MSR
, 0);
179 tc
->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP
, 0);
180 tc
->setMiscReg(MISCREG_LAST_BRANCH_TO_IP
, 0);
181 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP
, 0);
182 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP
, 0);
184 // Invalidate the caches (this should already be done for us)
186 LocalApicBase lApicBase
= 0;
187 lApicBase
.base
= 0xFEE00000 >> 12;
188 lApicBase
.enable
= 1;
189 lApicBase
.bsp
= (cpuId
== 0);
190 tc
->setMiscReg(MISCREG_APIC_BASE
, lApicBase
);
192 Interrupts
* interrupts
= dynamic_cast<Interrupts
*>(
193 tc
->getCpuPtr()->getInterruptController());
196 interrupts
->setRegNoEffect(APIC_ID
, cpuId
<< 24);
198 interrupts
->setRegNoEffect(APIC_VERSION
, (5 << 16) | 0x14);
200 interrupts
->setClock(tc
->getCpuPtr()->ticks(16));
202 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
204 tc
->setMiscReg(MISCREG_VM_CR
, 0);
205 tc
->setMiscReg(MISCREG_IGNNE
, 0);
206 tc
->setMiscReg(MISCREG_SMM_CTL
, 0);
207 tc
->setMiscReg(MISCREG_VM_HSAVE_PA
, 0);
212 void startupCPU(ThreadContext
*tc
, int cpuId
)
218 // This is an application processor (AP). It should be initialized to
219 // look like only the BIOS POST has run on it and put then put it into
229 copyMiscRegs(ThreadContext
*src
, ThreadContext
*dest
)
231 warn("copyMiscRegs is naively implemented for x86\n");
232 for (int i
= 0; i
< NUM_MISCREGS
; ++i
) {
233 if ( ( i
!= MISCREG_CR1
&&
234 !(i
> MISCREG_CR4
&& i
< MISCREG_CR8
) &&
235 !(i
> MISCREG_CR8
&& i
<= MISCREG_CR15
) ) == false) {
238 dest
->setMiscRegNoEffect(i
, src
->readMiscRegNoEffect(i
));
243 copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
245 panic("copyRegs not implemented for x86!\n");
248 copyMiscRegs(src
, dest
);
250 dest
->setPC(src
->readPC());
251 dest
->setNextPC(src
->readNextPC());
254 } //namespace X86_ISA