src/arch/x86/utility.cc

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
   7  * following conditions are met:
   8  *
   9  * The software must be used only for Non-Commercial Use which means any
  10  * use which is NOT directed to receiving any direct monetary
  11  * compensation for, or commercial advantage from such use.  Illustrative
  12  * examples of non-commercial use are academic research, personal study,
  13  * teaching, education and corporate research & development.
  14  * Illustrative examples of commercial use are distributing products for
  15  * commercial advantage and providing services using the software for
  16  * commercial advantage.
  17  *
  18  * If you wish to use this software or functionality therein that may be
  19  * covered by patents for commercial use, please contact:
  20  *     Director of Intellectual Property Licensing
  21  *     Office of Strategy and Technology
  22  *     Hewlett-Packard Company
  23  *     1501 Page Mill Road
  24  *     Palo Alto, California  94304
  25  *
  26  * Redistributions of source code must retain the above copyright notice,
  27  * this list of conditions and the following disclaimer.  Redistributions
  28  * in binary form must reproduce the above copyright notice, this list of
  29  * conditions and the following disclaimer in the documentation and/or
  30  * other materials provided with the distribution.  Neither the name of
  31  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  32  * contributors may be used to endorse or promote products derived from
  33  * this software without specific prior written permission.  No right of
  34  * sublicense is granted herewith.  Derivatives of the software and
  35  * output created using the software may be prepared, but only for
  36  * Non-Commercial Uses.  Derivatives of the software may be shared with
  37  * others provided: (i) the others agree to abide by the list of
  38  * conditions herein which includes the Non-Commercial Use restrictions;
  39  * and (ii) such Derivatives of the software include the above copyright
  40  * notice to acknowledge the contribution from this software where
  41  * applicable, this list of conditions and the disclaimer below.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #include "config/full_system.hh"
  59
  60 #if FULL_SYSTEM
  61 #include "arch/x86/interrupts.hh"
  62 #endif
  63 #include "arch/x86/intregs.hh"
  64 #include "arch/x86/miscregs.hh"
  65 #include "arch/x86/segmentregs.hh"
  66 #include "arch/x86/utility.hh"
  67 #include "arch/x86/x86_traits.hh"
  68 #include "cpu/base.hh"
  69 #include "sim/system.hh"
  70
  71 namespace X86ISA {
  72
  73 uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
  74 #if FULL_SYSTEM
  75     panic("getArgument() not implemented for x86!\n");
  76 #else
  77     panic("getArgument() only implemented for FULL_SYSTEM\n");
  78     M5_DUMMY_RETURN
  79 #endif
  80 }
  81
  82 # if FULL_SYSTEM
  83 void initCPU(ThreadContext *tc, int cpuId)
  84 {
  85     // This function is essentially performing a reset. The actual INIT
  86     // interrupt does a subset of this, so we'll piggyback on some of its
  87     // functionality.
  88     InitInterrupt init(0);
  89     init.invoke(tc);
  90
  91     tc->setMicroPC(0);
  92     tc->setNextMicroPC(1);
  93
  94     // These next two loops zero internal microcode and implicit registers.
  95     // They aren't specified by the ISA but are used internally by M5's
  96     // implementation.
  97     for (int index = 0; index < NumMicroIntRegs; index++) {
  98         tc->setIntReg(INTREG_MICRO(index), 0);
  99     }
 100
 101     for (int index = 0; index < NumImplicitIntRegs; index++) {
 102         tc->setIntReg(INTREG_IMPLICIT(index), 0);
 103     }
 104
 105     // Set integer register EAX to 0 to indicate that the optional BIST
 106     // passed. No BIST actually runs, but software may still check this
 107     // register for errors.
 108     tc->setIntReg(INTREG_RAX, 0);
 109
 110     tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
 111     tc->setMiscReg(MISCREG_CR8, 0);
 112
 113     // TODO initialize x87, 64 bit, and 128 bit media state
 114
 115     tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
 116     for (int i = 0; i < 8; i++) {
 117         tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
 118         tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
 119     }
 120     tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
 121     tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
 122     tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
 123     tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
 124     tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
 125     tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
 126     tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
 127     tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
 128     tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
 129     tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
 130     tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
 131
 132     tc->setMiscReg(MISCREG_DEF_TYPE, 0);
 133
 134     tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
 135     tc->setMiscReg(MISCREG_MCG_STATUS, 0);
 136     tc->setMiscReg(MISCREG_MCG_CTL, 0);
 137
 138     for (int i = 0; i < 5; i++) {
 139         tc->setMiscReg(MISCREG_MC_CTL(i), 0);
 140         tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
 141         tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
 142         tc->setMiscReg(MISCREG_MC_MISC(i), 0);
 143     }
 144
 145     tc->setMiscReg(MISCREG_TSC, 0);
 146     tc->setMiscReg(MISCREG_TSC_AUX, 0);
 147
 148     for (int i = 0; i < 4; i++) {
 149         tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
 150         tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
 151     }
 152
 153     tc->setMiscReg(MISCREG_STAR, 0);
 154     tc->setMiscReg(MISCREG_LSTAR, 0);
 155     tc->setMiscReg(MISCREG_CSTAR, 0);
 156
 157     tc->setMiscReg(MISCREG_SF_MASK, 0);
 158
 159     tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
 160
 161     tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
 162     tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
 163     tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
 164
 165     tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
 166
 167     tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
 168
 169     tc->setMiscReg(MISCREG_IORR_BASE0, 0);
 170     tc->setMiscReg(MISCREG_IORR_BASE1, 0);
 171
 172     tc->setMiscReg(MISCREG_IORR_MASK0, 0);
 173     tc->setMiscReg(MISCREG_IORR_MASK1, 0);
 174
 175     tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
 176     tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
 177
 178     tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
 179     tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
 180     tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
 181     tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
 182     tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
 183
 184     // Invalidate the caches (this should already be done for us)
 185
 186     LocalApicBase lApicBase = 0;
 187     lApicBase.base = 0xFEE00000 >> 12;
 188     lApicBase.enable = 1;
 189     lApicBase.bsp = (cpuId == 0);
 190     tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
 191
 192     Interrupts * interrupts = dynamic_cast<Interrupts *>(
 193             tc->getCpuPtr()->getInterruptController());
 194     assert(interrupts);
 195
 196     interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
 197
 198     interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
 199
 200     interrupts->setClock(tc->getCpuPtr()->ticks(16));
 201
 202     // TODO Set the SMRAM base address (SMBASE) to 0x00030000
 203
 204     tc->setMiscReg(MISCREG_VM_CR, 0);
 205     tc->setMiscReg(MISCREG_IGNNE, 0);
 206     tc->setMiscReg(MISCREG_SMM_CTL, 0);
 207     tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
 208 }
 209
 210 #endif
 211
 212 void startupCPU(ThreadContext *tc, int cpuId)
 213 {
 214 #if FULL_SYSTEM
 215     if (cpuId == 0) {
 216         tc->activate(0);
 217     } else {
 218         // This is an application processor (AP). It should be initialized to
 219         // look like only the BIOS POST has run on it and put then put it into
 220         // a halted state.
 221         tc->suspend(0);
 222     }
 223 #else
 224     tc->activate(0);
 225 #endif
 226 }
 227
 228 void
 229 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 230 {
 231     warn("copyMiscRegs is naively implemented for x86\n");
 232     for (int i = 0; i < NUM_MISCREGS; ++i) {
 233         if ( ( i != MISCREG_CR1 &&
 234              !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
 235              !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
 236              continue;
 237         }
 238         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 239     }
 240 }
 241
 242 void
 243 copyRegs(ThreadContext *src, ThreadContext *dest)
 244 {
 245     panic("copyRegs not implemented for x86!\n");
 246     //copy int regs
 247     //copy float regs
 248     copyMiscRegs(src, dest);
 249
 250     dest->setPC(src->readPC());
 251     dest->setNextPC(src->readNextPC());
 252 }
 253
 254 } //namespace X86_ISA