src/arch/x86/utility.cc

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * Copyright (c) 2011 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions are
  17  * met: redistributions of source code must retain the above copyright
  18  * notice, this list of conditions and the following disclaimer;
  19  * redistributions in binary form must reproduce the above copyright
  20  * notice, this list of conditions and the following disclaimer in the
  21  * documentation and/or other materials provided with the distribution;
  22  * neither the name of the copyright holders nor the names of its
  23  * contributors may be used to endorse or promote products derived from
  24  * this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  *
  38  * Authors: Gabe Black
  39  */
  40
  41 #include "arch/x86/utility.hh"
  42
  43 #include "arch/x86/interrupts.hh"
  44 #include "arch/x86/registers.hh"
  45 #include "arch/x86/x86_traits.hh"
  46 #include "cpu/base.hh"
  47 #include "fputils/fp80.h"
  48 #include "sim/full_system.hh"
  49
  50 namespace X86ISA {
  51
  52 uint64_t
  53 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
  54 {
  55     if (fp) {
  56         panic("getArgument(): Floating point arguments not implemented\n");
  57     } else if (size != 8) {
  58         panic("getArgument(): Can only handle 64-bit arguments.\n");
  59     }
  60
  61     // The first 6 integer arguments are passed in registers, the rest
  62     // are passed on the stack.
  63     const int int_reg_map[] = {
  64         INTREG_RDI, INTREG_RSI, INTREG_RDX,
  65         INTREG_RCX, INTREG_R8, INTREG_R9
  66     };
  67     if (number < sizeof(int_reg_map) / sizeof(*int_reg_map)) {
  68         return tc->readIntReg(int_reg_map[number]);
  69     } else {
  70         panic("getArgument(): Don't know how to handle stack arguments.\n");
  71     }
  72 }
  73
  74 void
  75 initCPU(ThreadContext *tc, int cpuId)
  76 {
  77     // This function is essentially performing a reset. The actual INIT
  78     // interrupt does a subset of this, so we'll piggyback on some of its
  79     // functionality.
  80     InitInterrupt init(0);
  81     init.invoke(tc);
  82
  83     // Set integer register EAX to 0 to indicate that the optional BIST
  84     // passed. No BIST actually runs, but software may still check this
  85     // register for errors.
  86     tc->setIntReg(INTREG_RAX, 0);
  87
  88     Interrupts * interrupts = dynamic_cast<Interrupts *>(
  89             tc->getCpuPtr()->getInterruptController(0));
  90     assert(interrupts);
  91
  92     interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
  93
  94     interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
  95 }
  96
  97 void startupCPU(ThreadContext *tc, int cpuId)
  98 {
  99     if (cpuId == 0 || !FullSystem) {
 100         tc->activate();
 101     } else {
 102         // This is an application processor (AP). It should be initialized to
 103         // look like only the BIOS POST has run on it and put then put it into
 104         // a halted state.
 105         tc->suspend();
 106     }
 107 }
 108
 109 void
 110 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 111 {
 112     // This function assumes no side effects other than TLB invalidation
 113     // need to be considered while copying state. That will likely not be
 114     // true in the future.
 115     for (int i = 0; i < NUM_MISCREGS; ++i) {
 116         if (!isValidMiscReg(i))
 117              continue;
 118
 119         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 120     }
 121
 122     // The TSC has to be updated with side-effects if the CPUs in a
 123     // CPU switch have different frequencies.
 124     dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
 125
 126     dest->getITBPtr()->flushAll();
 127     dest->getDTBPtr()->flushAll();
 128 }
 129
 130 void
 131 copyRegs(ThreadContext *src, ThreadContext *dest)
 132 {
 133     //copy int regs
 134     for (int i = 0; i < NumIntRegs; ++i)
 135          dest->setIntRegFlat(i, src->readIntRegFlat(i));
 136     //copy float regs
 137     for (int i = 0; i < NumFloatRegs; ++i)
 138          dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
 139     //copy condition-code regs
 140     for (int i = 0; i < NumCCRegs; ++i)
 141          dest->setCCRegFlat(i, src->readCCRegFlat(i));
 142     copyMiscRegs(src, dest);
 143     dest->pcState(src->pcState());
 144 }
 145
 146 void
 147 skipFunction(ThreadContext *tc)
 148 {
 149     panic("Not implemented for x86\n");
 150 }
 151
 152 uint64_t
 153 getRFlags(ThreadContext *tc)
 154 {
 155     const uint64_t ncc_flags(tc->readMiscRegNoEffect(MISCREG_RFLAGS));
 156     const uint64_t cc_flags(tc->readCCReg(X86ISA::CCREG_ZAPS));
 157     const uint64_t cfof_bits(tc->readCCReg(X86ISA::CCREG_CFOF));
 158     const uint64_t df_bit(tc->readCCReg(X86ISA::CCREG_DF));
 159     // ecf (PSEUDO(3)) & ezf (PSEUDO(4)) are only visible to
 160     // microcode, so we can safely ignore them.
 161
 162     // Reconstruct the real rflags state, mask out internal flags, and
 163     // make sure reserved bits have the expected values.
 164     return ((ncc_flags | cc_flags | cfof_bits | df_bit) & 0x3F7FD5)
 165         | 0x2;
 166 }
 167
 168 void
 169 setRFlags(ThreadContext *tc, uint64_t val)
 170 {
 171     tc->setCCReg(X86ISA::CCREG_ZAPS, val & ccFlagMask);
 172     tc->setCCReg(X86ISA::CCREG_CFOF, val & cfofMask);
 173     tc->setCCReg(X86ISA::CCREG_DF, val & DFBit);
 174
 175     // Internal microcode registers (ECF & EZF)
 176     tc->setCCReg(X86ISA::CCREG_ECF, 0);
 177     tc->setCCReg(X86ISA::CCREG_EZF, 0);
 178
 179     // Update the RFLAGS misc reg with whatever didn't go into the
 180     // magic registers.
 181     tc->setMiscReg(MISCREG_RFLAGS, val & ~(ccFlagMask | cfofMask | DFBit));
 182 }
 183
 184 uint8_t
 185 convX87TagsToXTags(uint16_t ftw)
 186 {
 187     uint8_t ftwx(0);
 188     for (int i = 0; i < 8; ++i) {
 189         // Extract the tag for the current element on the FP stack
 190         const unsigned tag((ftw >> (2 * i)) & 0x3);
 191
 192         /*
 193          * Check the type of the current FP element. Valid values are:
 194          * 0 == Valid
 195          * 1 == Zero
 196          * 2 == Special (Nan, unsupported, infinity, denormal)
 197          * 3 == Empty
 198          */
 199         // The xsave version of the tag word only keeps track of
 200         // whether the element is empty or not. Set the corresponding
 201         // bit in the ftwx if it's not empty,
 202         if (tag != 0x3)
 203             ftwx |= 1 << i;
 204     }
 205
 206     return ftwx;
 207 }
 208
 209 uint16_t
 210 convX87XTagsToTags(uint8_t ftwx)
 211 {
 212     uint16_t ftw(0);
 213     for (int i = 0; i < 8; ++i) {
 214         const unsigned xtag(((ftwx >> i) & 0x1));
 215
 216         // The xtag for an x87 stack position is 0 for empty stack positions.
 217         if (!xtag) {
 218             // Set the tag word to 3 (empty) for the current element.
 219             ftw |= 0x3 << (2 * i);
 220         } else {
 221             // TODO: We currently assume that non-empty elements are
 222             // valid (0x0), but we should ideally reconstruct the full
 223             // state (valid/zero/special).
 224         }
 225     }
 226
 227     return ftw;
 228 }
 229
 230 uint16_t
 231 genX87Tags(uint16_t ftw, uint8_t top, int8_t spm)
 232 {
 233     const uint8_t new_top((top + spm + 8) % 8);
 234
 235     if (spm > 0) {
 236         // Removing elements from the stack. Flag the elements as empty.
 237         for (int i = top; i != new_top; i = (i + 1 + 8) % 8)
 238             ftw |= 0x3 << (2 * i);
 239     } else if (spm < 0) {
 240         // Adding elements to the stack. Flag the new elements as
 241         // valid. We should ideally decode them and "do the right
 242         // thing".
 243         for (int i = new_top; i != top; i = (i + 1 + 8) % 8)
 244             ftw &= ~(0x3 << (2 * i));
 245     }
 246
 247     return ftw;
 248 }
 249
 250 double
 251 loadFloat80(const void *_mem)
 252 {
 253     fp80_t fp80;
 254     memcpy(fp80.bits, _mem, 10);
 255
 256     return fp80_cvtd(fp80);
 257 }
 258
 259 void
 260 storeFloat80(void *_mem, double value)
 261 {
 262     fp80_t fp80 = fp80_cvfd(value);
 263     memcpy(_mem, fp80.bits, 10);
 264 }
 265
 266 } // namespace X86_ISA