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58 #include "arch/x86/intregs.hh"
59 #include "arch/x86/miscregs.hh"
60 #include "arch/x86/segmentregs.hh"
61 #include "arch/x86/utility.hh"
62 #include "arch/x86/x86_traits.hh"
66 uint64_t getArgument(ThreadContext
*tc
, int number
, bool fp
) {
68 panic("getArgument() not implemented for x86!\n");
70 panic("getArgument() only implemented for FULL_SYSTEM\n");
76 void initCPU(ThreadContext
*tc
, int cpuId
)
78 // TODO Figure out what the attribute registers should be set to. How this
79 // information is stored isn't specified, but it's values are in table
82 // The otherwise unmodified integer registers should be set to 0.
83 for (int index
= 0; index
< NUM_INTREGS
; index
++) {
84 tc
->setIntReg(index
, 0);
87 // These next two loops zero internal microcode and implicit registers.
88 // They aren't specified by the ISA but are used internally by M5's
90 for (int index
= 0; index
< NumMicroIntRegs
; index
++) {
91 tc
->setIntReg(INTREG_MICRO(index
), 0);
94 for (int index
= 0; index
< NumImplicitIntRegs
; index
++) {
95 tc
->setIntReg(INTREG_IMPLICIT(index
), 0);
98 // Set integer register EAX to 0 to indicate that the optional BIST
99 // passed. No BIST actually runs, but software may still check this
100 // register for errors.
101 tc
->setIntReg(INTREG_RAX
, 0);
103 //The following values are dictated by the architecture for after a RESET#
104 tc
->setMiscReg(MISCREG_CR0
, 0x0000000060000010);
105 tc
->setMiscReg(MISCREG_CR2
, 0);
106 tc
->setMiscReg(MISCREG_CR3
, 0);
107 tc
->setMiscReg(MISCREG_CR4
, 0);
108 tc
->setMiscReg(MISCREG_CR8
, 0);
110 tc
->setMiscReg(MISCREG_RFLAGS
, 0x0000000000000002);
112 tc
->setMiscReg(MISCREG_EFER
, 0);
114 for (int seg
= 0; seg
!= NUM_SEGMENTREGS
; seg
++) {
115 tc
->setMiscReg(MISCREG_SEG_SEL(seg
), 0);
116 tc
->setMiscReg(MISCREG_SEG_BASE(seg
), 0);
117 tc
->setMiscReg(MISCREG_SEG_LIMIT(seg
), 0xffff);
118 tc
->setMiscReg(MISCREG_SEG_ATTR(seg
), 0);
121 tc
->setMiscReg(MISCREG_CS
, 0xf000);
122 tc
->setMiscReg(MISCREG_CS_BASE
, 0x00000000ffff0000);
123 // This has the base value pre-added.
124 tc
->setMiscReg(MISCREG_CS_LIMIT
, 0xffffffff);
125 tc
->setMiscReg(MISCREG_CS_ATTR
, 0);
127 tc
->setPC(0x000000000000fff0 +
128 tc
->readMiscReg(MISCREG_CS_BASE
));
129 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
131 tc
->setMiscReg(MISCREG_GDTR_BASE
, 0);
132 tc
->setMiscReg(MISCREG_GDTR_LIMIT
, 0xffff);
134 tc
->setMiscReg(MISCREG_IDTR_BASE
, 0);
135 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
137 tc
->setMiscReg(MISCREG_LDTR
, 0);
138 tc
->setMiscReg(MISCREG_LDTR_BASE
, 0);
139 tc
->setMiscReg(MISCREG_LDTR_LIMIT
, 0xffff);
140 tc
->setMiscReg(MISCREG_LDTR_ATTR
, 0);
142 tc
->setMiscReg(MISCREG_TR
, 0);
143 tc
->setMiscReg(MISCREG_TR_BASE
, 0);
144 tc
->setMiscReg(MISCREG_TR_LIMIT
, 0xffff);
145 tc
->setMiscReg(MISCREG_TR_ATTR
, 0);
147 // This value should be the family/model/stepping of the processor.
148 // (page 418). It should be consistent with the value from CPUID, but the
149 // actual value probably doesn't matter much.
150 tc
->setIntReg(INTREG_RDX
, 0);
152 // TODO initialize x87, 64 bit, and 128 bit media state
154 // TODO Set up MTRRs (page 512)
156 // TODO Set up machine check registers (page 515)
158 tc
->setMiscReg(MISCREG_DR0
, 0);
159 tc
->setMiscReg(MISCREG_DR1
, 0);
160 tc
->setMiscReg(MISCREG_DR2
, 0);
161 tc
->setMiscReg(MISCREG_DR3
, 0);
163 tc
->setMiscReg(MISCREG_DR6
, 0x00000000ffff0ff0);
164 tc
->setMiscReg(MISCREG_DR7
, 0x0000000000000400);
166 // TODO Set time stamp counter to 0
168 // TODO Set up performance monitoring registers (page 517)
170 // TODO Set up the rest of the MSRs (page 507)
172 // Invalidate the caches (this should already be done for us)
174 // TODO Turn on the APIC. This should be handled elsewhere but it isn't
175 // currently being handled at all.
177 // Set the SMRAM base address (SMBASE) to 0x00030000
182 void startupCPU(ThreadContext
*tc
, int cpuId
)
185 // This is the boot strap processor (BSP). Initialize it to look like
186 // the boot loader has just turned control over to the 64 bit OS.
188 // Enable paging, turn on long mode, etc.
192 // This is an application processor (AP). It should be initialized to
193 // look like only the BIOS POST has run on it and put then put it into
198 } //namespace X86_ISA