src/arch/x86/utility.cc

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * Copyright (c) 2011 Advanced Micro Devices, Inc.
   4  * All rights reserved.
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions are
  17  * met: redistributions of source code must retain the above copyright
  18  * notice, this list of conditions and the following disclaimer;
  19  * redistributions in binary form must reproduce the above copyright
  20  * notice, this list of conditions and the following disclaimer in the
  21  * documentation and/or other materials provided with the distribution;
  22  * neither the name of the copyright holders nor the names of its
  23  * contributors may be used to endorse or promote products derived from
  24  * this software without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  27  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  28  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  29  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  30  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  31  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  32  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  33  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  34  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  36  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  *
  38  * Authors: Gabe Black
  39  */
  40
  41 #include "arch/x86/utility.hh"
  42
  43 #include "arch/x86/interrupts.hh"
  44 #include "arch/x86/registers.hh"
  45 #include "arch/x86/x86_traits.hh"
  46 #include "cpu/base.hh"
  47 #include "fputils/fp80.h"
  48 #include "sim/full_system.hh"
  49
  50 namespace X86ISA {
  51
  52 uint64_t
  53 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
  54 {
  55     if (fp) {
  56         panic("getArgument(): Floating point arguments not implemented\n");
  57     } else if (size != 8) {
  58         panic("getArgument(): Can only handle 64-bit arguments.\n");
  59     }
  60
  61     // The first 6 integer arguments are passed in registers, the rest
  62     // are passed on the stack.
  63     const int int_reg_map[] = {
  64         INTREG_RDI, INTREG_RSI, INTREG_RDX,
  65         INTREG_RCX, INTREG_R8, INTREG_R9
  66     };
  67     if (number < sizeof(int_reg_map) / sizeof(*int_reg_map)) {
  68         return tc->readIntReg(int_reg_map[number]);
  69     } else {
  70         panic("getArgument(): Don't know how to handle stack arguments.\n");
  71     }
  72 }
  73
  74 void
  75 initCPU(ThreadContext *tc, int cpuId)
  76 {
  77     // This function is essentially performing a reset. The actual INIT
  78     // interrupt does a subset of this, so we'll piggyback on some of its
  79     // functionality.
  80     InitInterrupt init(0);
  81     init.invoke(tc);
  82
  83     // Set integer register EAX to 0 to indicate that the optional BIST
  84     // passed. No BIST actually runs, but software may still check this
  85     // register for errors.
  86     tc->setIntReg(INTREG_RAX, 0);
  87 }
  88
  89 void startupCPU(ThreadContext *tc, int cpuId)
  90 {
  91     if (cpuId == 0 || !FullSystem) {
  92         tc->activate();
  93     } else {
  94         // This is an application processor (AP). It should be initialized to
  95         // look like only the BIOS POST has run on it and put then put it into
  96         // a halted state.
  97         tc->suspend();
  98     }
  99 }
 100
 101 void
 102 copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 103 {
 104     // This function assumes no side effects other than TLB invalidation
 105     // need to be considered while copying state. That will likely not be
 106     // true in the future.
 107     for (int i = 0; i < NUM_MISCREGS; ++i) {
 108         if (!isValidMiscReg(i))
 109              continue;
 110
 111         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 112     }
 113
 114     // The TSC has to be updated with side-effects if the CPUs in a
 115     // CPU switch have different frequencies.
 116     dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC));
 117
 118     dest->getITBPtr()->flushAll();
 119     dest->getDTBPtr()->flushAll();
 120 }
 121
 122 void
 123 copyRegs(ThreadContext *src, ThreadContext *dest)
 124 {
 125     //copy int regs
 126     for (int i = 0; i < NumIntRegs; ++i)
 127          dest->setIntRegFlat(i, src->readIntRegFlat(i));
 128     //copy float regs
 129     for (int i = 0; i < NumFloatRegs; ++i)
 130          dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
 131     //copy condition-code regs
 132     for (int i = 0; i < NumCCRegs; ++i)
 133          dest->setCCRegFlat(i, src->readCCRegFlat(i));
 134     copyMiscRegs(src, dest);
 135     dest->pcState(src->pcState());
 136 }
 137
 138 void
 139 skipFunction(ThreadContext *tc)
 140 {
 141     panic("Not implemented for x86\n");
 142 }
 143
 144 uint64_t
 145 getRFlags(ThreadContext *tc)
 146 {
 147     const uint64_t ncc_flags(tc->readMiscRegNoEffect(MISCREG_RFLAGS));
 148     const uint64_t cc_flags(tc->readCCReg(X86ISA::CCREG_ZAPS));
 149     const uint64_t cfof_bits(tc->readCCReg(X86ISA::CCREG_CFOF));
 150     const uint64_t df_bit(tc->readCCReg(X86ISA::CCREG_DF));
 151     // ecf (PSEUDO(3)) & ezf (PSEUDO(4)) are only visible to
 152     // microcode, so we can safely ignore them.
 153
 154     // Reconstruct the real rflags state, mask out internal flags, and
 155     // make sure reserved bits have the expected values.
 156     return ((ncc_flags | cc_flags | cfof_bits | df_bit) & 0x3F7FD5)
 157         | 0x2;
 158 }
 159
 160 void
 161 setRFlags(ThreadContext *tc, uint64_t val)
 162 {
 163     tc->setCCReg(X86ISA::CCREG_ZAPS, val & ccFlagMask);
 164     tc->setCCReg(X86ISA::CCREG_CFOF, val & cfofMask);
 165     tc->setCCReg(X86ISA::CCREG_DF, val & DFBit);
 166
 167     // Internal microcode registers (ECF & EZF)
 168     tc->setCCReg(X86ISA::CCREG_ECF, 0);
 169     tc->setCCReg(X86ISA::CCREG_EZF, 0);
 170
 171     // Update the RFLAGS misc reg with whatever didn't go into the
 172     // magic registers.
 173     tc->setMiscReg(MISCREG_RFLAGS, val & ~(ccFlagMask | cfofMask | DFBit));
 174 }
 175
 176 uint8_t
 177 convX87TagsToXTags(uint16_t ftw)
 178 {
 179     uint8_t ftwx(0);
 180     for (int i = 0; i < 8; ++i) {
 181         // Extract the tag for the current element on the FP stack
 182         const unsigned tag((ftw >> (2 * i)) & 0x3);
 183
 184         /*
 185          * Check the type of the current FP element. Valid values are:
 186          * 0 == Valid
 187          * 1 == Zero
 188          * 2 == Special (Nan, unsupported, infinity, denormal)
 189          * 3 == Empty
 190          */
 191         // The xsave version of the tag word only keeps track of
 192         // whether the element is empty or not. Set the corresponding
 193         // bit in the ftwx if it's not empty,
 194         if (tag != 0x3)
 195             ftwx |= 1 << i;
 196     }
 197
 198     return ftwx;
 199 }
 200
 201 uint16_t
 202 convX87XTagsToTags(uint8_t ftwx)
 203 {
 204     uint16_t ftw(0);
 205     for (int i = 0; i < 8; ++i) {
 206         const unsigned xtag(((ftwx >> i) & 0x1));
 207
 208         // The xtag for an x87 stack position is 0 for empty stack positions.
 209         if (!xtag) {
 210             // Set the tag word to 3 (empty) for the current element.
 211             ftw |= 0x3 << (2 * i);
 212         } else {
 213             // TODO: We currently assume that non-empty elements are
 214             // valid (0x0), but we should ideally reconstruct the full
 215             // state (valid/zero/special).
 216         }
 217     }
 218
 219     return ftw;
 220 }
 221
 222 uint16_t
 223 genX87Tags(uint16_t ftw, uint8_t top, int8_t spm)
 224 {
 225     const uint8_t new_top((top + spm + 8) % 8);
 226
 227     if (spm > 0) {
 228         // Removing elements from the stack. Flag the elements as empty.
 229         for (int i = top; i != new_top; i = (i + 1 + 8) % 8)
 230             ftw |= 0x3 << (2 * i);
 231     } else if (spm < 0) {
 232         // Adding elements to the stack. Flag the new elements as
 233         // valid. We should ideally decode them and "do the right
 234         // thing".
 235         for (int i = new_top; i != top; i = (i + 1 + 8) % 8)
 236             ftw &= ~(0x3 << (2 * i));
 237     }
 238
 239     return ftw;
 240 }
 241
 242 double
 243 loadFloat80(const void *_mem)
 244 {
 245     fp80_t fp80;
 246     memcpy(fp80.bits, _mem, 10);
 247
 248     return fp80_cvtd(fp80);
 249 }
 250
 251 void
 252 storeFloat80(void *_mem, double value)
 253 {
 254     fp80_t fp80 = fp80_cvfd(value);
 255     memcpy(_mem, fp80.bits, 10);
 256 }
 257
 258 } // namespace X86_ISA