2 * Copyright (c) 2007 The Hewlett-Packard Development Company
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58 #include "arch/x86/intregs.hh"
59 #include "arch/x86/miscregs.hh"
60 #include "arch/x86/segmentregs.hh"
61 #include "arch/x86/utility.hh"
62 #include "arch/x86/x86_traits.hh"
63 #include "sim/system.hh"
67 uint64_t getArgument(ThreadContext
*tc
, int number
, bool fp
) {
69 panic("getArgument() not implemented for x86!\n");
71 panic("getArgument() only implemented for FULL_SYSTEM\n");
77 void initCPU(ThreadContext
*tc
, int cpuId
)
79 // The otherwise unmodified integer registers should be set to 0.
80 for (int index
= 0; index
< NUM_INTREGS
; index
++) {
81 tc
->setIntReg(index
, 0);
84 // These next two loops zero internal microcode and implicit registers.
85 // They aren't specified by the ISA but are used internally by M5's
87 for (int index
= 0; index
< NumMicroIntRegs
; index
++) {
88 tc
->setIntReg(INTREG_MICRO(index
), 0);
91 for (int index
= 0; index
< NumImplicitIntRegs
; index
++) {
92 tc
->setIntReg(INTREG_IMPLICIT(index
), 0);
95 // Set integer register EAX to 0 to indicate that the optional BIST
96 // passed. No BIST actually runs, but software may still check this
97 // register for errors.
98 tc
->setIntReg(INTREG_RAX
, 0);
100 //The following values are dictated by the architecture for after a RESET#
101 tc
->setMiscReg(MISCREG_CR0
, 0x0000000060000010ULL
);
102 tc
->setMiscReg(MISCREG_CR2
, 0);
103 tc
->setMiscReg(MISCREG_CR3
, 0);
104 tc
->setMiscReg(MISCREG_CR4
, 0);
105 tc
->setMiscReg(MISCREG_CR8
, 0);
107 tc
->setMiscReg(MISCREG_RFLAGS
, 0x0000000000000002ULL
);
109 tc
->setMiscReg(MISCREG_EFER
, 0);
111 SegAttr dataAttr
= 0;
112 dataAttr
.writable
= 1;
113 dataAttr
.readable
= 1;
114 dataAttr
.expandDown
= 0;
116 dataAttr
.defaultSize
= 0;
118 for (int seg
= 0; seg
!= NUM_SEGMENTREGS
; seg
++) {
119 tc
->setMiscReg(MISCREG_SEG_SEL(seg
), 0);
120 tc
->setMiscReg(MISCREG_SEG_BASE(seg
), 0);
121 tc
->setMiscReg(MISCREG_SEG_LIMIT(seg
), 0xffff);
122 tc
->setMiscReg(MISCREG_SEG_ATTR(seg
), dataAttr
);
125 SegAttr codeAttr
= 0;
126 codeAttr
.writable
= 0;
127 codeAttr
.readable
= 1;
128 codeAttr
.expandDown
= 0;
130 codeAttr
.defaultSize
= 0;
132 tc
->setMiscReg(MISCREG_CS
, 0xf000);
133 tc
->setMiscReg(MISCREG_CS_BASE
, 0x00000000ffff0000ULL
);
134 // This has the base value pre-added.
135 tc
->setMiscReg(MISCREG_CS_LIMIT
, 0xffffffff);
136 tc
->setMiscReg(MISCREG_CS_ATTR
, codeAttr
);
138 tc
->setPC(0x000000000000fff0ULL
+
139 tc
->readMiscReg(MISCREG_CS_BASE
));
140 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
142 tc
->setMiscReg(MISCREG_GDTR_BASE
, 0);
143 tc
->setMiscReg(MISCREG_GDTR_LIMIT
, 0xffff);
145 tc
->setMiscReg(MISCREG_IDTR_BASE
, 0);
146 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
148 tc
->setMiscReg(MISCREG_LDTR
, 0);
149 tc
->setMiscReg(MISCREG_LDTR_BASE
, 0);
150 tc
->setMiscReg(MISCREG_LDTR_LIMIT
, 0xffff);
151 tc
->setMiscReg(MISCREG_LDTR_ATTR
, 0);
153 tc
->setMiscReg(MISCREG_TR
, 0);
154 tc
->setMiscReg(MISCREG_TR_BASE
, 0);
155 tc
->setMiscReg(MISCREG_TR_LIMIT
, 0xffff);
156 tc
->setMiscReg(MISCREG_TR_ATTR
, 0);
158 // This value should be the family/model/stepping of the processor.
159 // (page 418). It should be consistent with the value from CPUID, but the
160 // actual value probably doesn't matter much.
161 tc
->setIntReg(INTREG_RDX
, 0);
163 // TODO initialize x87, 64 bit, and 128 bit media state
165 tc
->setMiscReg(MISCREG_MTRRCAP
, 0x0508);
166 for (int i
= 0; i
< 8; i
++) {
167 tc
->setMiscReg(MISCREG_MTRR_PHYS_BASE(i
), 0);
168 tc
->setMiscReg(MISCREG_MTRR_PHYS_MASK(i
), 0);
170 tc
->setMiscReg(MISCREG_MTRR_FIX_64K_00000
, 0);
171 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_80000
, 0);
172 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_A0000
, 0);
173 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C0000
, 0);
174 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C8000
, 0);
175 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D0000
, 0);
176 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D8000
, 0);
177 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E0000
, 0);
178 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E8000
, 0);
179 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F0000
, 0);
180 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F8000
, 0);
182 tc
->setMiscReg(MISCREG_DEF_TYPE
, 0);
184 tc
->setMiscReg(MISCREG_MCG_CAP
, 0x104);
185 tc
->setMiscReg(MISCREG_MCG_STATUS
, 0);
186 tc
->setMiscReg(MISCREG_MCG_CTL
, 0);
188 for (int i
= 0; i
< 5; i
++) {
189 tc
->setMiscReg(MISCREG_MC_CTL(i
), 0);
190 tc
->setMiscReg(MISCREG_MC_STATUS(i
), 0);
191 tc
->setMiscReg(MISCREG_MC_ADDR(i
), 0);
192 tc
->setMiscReg(MISCREG_MC_MISC(i
), 0);
195 tc
->setMiscReg(MISCREG_DR0
, 0);
196 tc
->setMiscReg(MISCREG_DR1
, 0);
197 tc
->setMiscReg(MISCREG_DR2
, 0);
198 tc
->setMiscReg(MISCREG_DR3
, 0);
200 tc
->setMiscReg(MISCREG_DR6
, 0x00000000ffff0ff0ULL
);
201 tc
->setMiscReg(MISCREG_DR7
, 0x0000000000000400ULL
);
203 tc
->setMiscReg(MISCREG_TSC
, 0);
204 tc
->setMiscReg(MISCREG_TSC_AUX
, 0);
206 for (int i
= 0; i
< 4; i
++) {
207 tc
->setMiscReg(MISCREG_PERF_EVT_SEL(i
), 0);
208 tc
->setMiscReg(MISCREG_PERF_EVT_CTR(i
), 0);
211 tc
->setMiscReg(MISCREG_STAR
, 0);
212 tc
->setMiscReg(MISCREG_LSTAR
, 0);
213 tc
->setMiscReg(MISCREG_CSTAR
, 0);
215 tc
->setMiscReg(MISCREG_SF_MASK
, 0);
217 tc
->setMiscReg(MISCREG_KERNEL_GS_BASE
, 0);
219 tc
->setMiscReg(MISCREG_SYSENTER_CS
, 0);
220 tc
->setMiscReg(MISCREG_SYSENTER_ESP
, 0);
221 tc
->setMiscReg(MISCREG_SYSENTER_EIP
, 0);
223 tc
->setMiscReg(MISCREG_PAT
, 0x0007040600070406ULL
);
225 tc
->setMiscReg(MISCREG_SYSCFG
, 0x20601);
227 tc
->setMiscReg(MISCREG_IORR_BASE0
, 0);
228 tc
->setMiscReg(MISCREG_IORR_BASE1
, 0);
230 tc
->setMiscReg(MISCREG_IORR_MASK0
, 0);
231 tc
->setMiscReg(MISCREG_IORR_MASK1
, 0);
233 tc
->setMiscReg(MISCREG_TOP_MEM
, 0x4000000);
234 tc
->setMiscReg(MISCREG_TOP_MEM2
, 0x0);
236 tc
->setMiscReg(MISCREG_DEBUG_CTL_MSR
, 0);
237 tc
->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP
, 0);
238 tc
->setMiscReg(MISCREG_LAST_BRANCH_TO_IP
, 0);
239 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP
, 0);
240 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP
, 0);
242 // Invalidate the caches (this should already be done for us)
244 // TODO Turn on the APIC. This should be handled elsewhere but it isn't
245 // currently being handled at all.
247 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
249 tc
->setMiscReg(MISCREG_VM_CR
, 0);
250 tc
->setMiscReg(MISCREG_IGNNE
, 0);
251 tc
->setMiscReg(MISCREG_SMM_CTL
, 0);
252 tc
->setMiscReg(MISCREG_VM_HSAVE_PA
, 0);
258 void startupCPU(ThreadContext
*tc
, int cpuId
)
261 // This is the boot strap processor (BSP). Initialize it to look like
262 // the boot loader has just turned control over to the 64 bit OS. We
263 // won't actually set up real mode or legacy protected mode descriptor
264 // tables because we aren't executing any code that would require
265 // them. We do, however toggle the control bits in the correct order
266 // while allowing consistency checks and the underlying mechansims
269 const int NumPDTs
= 4;
271 const Addr PageMapLevel4
= 0x70000;
272 const Addr PageDirPtrTable
= 0x71000;
273 const Addr PageDirTable
[NumPDTs
] =
274 {0x72000, 0x73000, 0x74000, 0x75000};
275 const Addr GDTBase
= 0x76000;
277 const int PML4Bits
= 9;
278 const int PDPTBits
= 9;
279 const int PDTBits
= 9;
281 // Get a port to write the page tables and descriptor tables.
282 FunctionalPort
* physPort
= tc
->getPhysPort();
287 // Place holder at selector 0
288 uint64_t nullDescriptor
= 0;
289 physPort
->writeBlob(GDTBase
, (uint8_t *)(&nullDescriptor
), 8);
291 //64 bit code segment
292 SegDescriptor csDesc
= 0;
293 csDesc
.type
.c
= 0; // Not conforming
294 csDesc
.dpl
= 0; // Privelege level 0
295 csDesc
.p
= 1; // Present
296 csDesc
.l
= 1; // 64 bit
297 csDesc
.d
= 0; // default operand size
298 //Because we're dealing with a pointer and I don't think it's
299 //guaranteed that there isn't anything in a nonvirtual class between
300 //it's beginning in memory and it's actual data, we'll use an
302 uint64_t csDescVal
= csDesc
;
303 physPort
->writeBlob(GDTBase
, (uint8_t *)(&csDescVal
), 8);
305 tc
->setMiscReg(MISCREG_GDTR_BASE
, GDTBase
);
306 tc
->setMiscReg(MISCREG_GDTR_LIMIT
, 0xF);
309 * Identity map the first 4GB of memory. In order to map this region
310 * of memory in long mode, there needs to be one actual page map level
311 * 4 entry which points to one page directory pointer table which
312 * points to 4 different page directory tables which are full of two
313 * megabyte pages. All of the other entries in valid tables are set
314 * to indicate that they don't pertain to anything valid and will
315 * cause a fault if used.
318 // Put valid values in all of the various table entries which indicate
319 // that those entries don't point to further tables or pages. Then
320 // set the values of those entries which are needed.
324 // read/write, user, not present
325 uint64_t pml4e
= X86ISA::htog(0x6);
326 for (int offset
= 0; offset
< (1 << PML4Bits
) * 8; offset
+= 8) {
327 physPort
->writeBlob(PageMapLevel4
+ offset
, (uint8_t *)(&pml4e
), 8);
329 // Point to the only PDPT
330 pml4e
= X86ISA::htog(0x7 | PageDirPtrTable
);
331 physPort
->writeBlob(PageMapLevel4
, (uint8_t *)(&pml4e
), 8);
333 // Page Directory Pointer Table
335 // read/write, user, not present
336 uint64_t pdpe
= X86ISA::htog(0x6);
337 for (int offset
= 0; offset
< (1 << PDPTBits
) * 8; offset
+= 8) {
338 physPort
->writeBlob(PageDirPtrTable
+ offset
,
339 (uint8_t *)(&pdpe
), 8);
342 for (int table
= 0; table
< NumPDTs
; table
++) {
343 pdpe
= X86ISA::htog(0x7 | PageDirTable
[table
]);
344 physPort
->writeBlob(PageDirPtrTable
+ table
* 8,
345 (uint8_t *)(&pdpe
), 8);
348 // Page Directory Tables
351 const Addr pageSize
= 2 << 20;
352 for (int table
= 0; table
< NumPDTs
; table
++) {
353 for (int offset
= 0; offset
< (1 << PDTBits
) * 8; offset
+= 8) {
354 // read/write, user, present, 4MB
355 uint64_t pdte
= X86ISA::htog(0x87 | base
);
356 physPort
->writeBlob(PageDirTable
[table
] + offset
,
357 (uint8_t *)(&pdte
), 8);
363 * Transition from real mode all the way up to Long mode
365 CR0 cr0
= tc
->readMiscRegNoEffect(MISCREG_CR0
);
368 tc
->setMiscReg(MISCREG_CR0
, cr0
);
369 //Turn on protected mode.
371 tc
->setMiscReg(MISCREG_CR0
, cr0
);
373 CR4 cr4
= tc
->readMiscRegNoEffect(MISCREG_CR4
);
376 tc
->setMiscReg(MISCREG_CR4
, cr4
);
378 //Point to the page tables.
379 tc
->setMiscReg(MISCREG_CR3
, PageMapLevel4
);
381 Efer efer
= tc
->readMiscRegNoEffect(MISCREG_EFER
);
384 tc
->setMiscReg(MISCREG_EFER
, efer
);
386 //Activate long mode.
388 tc
->setMiscReg(MISCREG_CR0
, cr0
);
391 * Far jump into 64 bit mode.
394 tc
->setMiscReg(MISCREG_CS
, 1);
395 // Manually set up the segment attributes. In the future when there's
396 // other existing functionality to do this, that could be used
401 csAttr
.expandDown
= 0;
403 csAttr
.defaultSize
= 0;
405 tc
->setMiscReg(MISCREG_CS_ATTR
, csAttr
);
407 tc
->setPC(tc
->getSystemPtr()->kernelEntry
);
408 tc
->setNextPC(tc
->readPC());
410 // We should now be in long mode. Yay!
414 // This is an application processor (AP). It should be initialized to
415 // look like only the BIOS POST has run on it and put then put it into
423 void startupCPU(ThreadContext
*tc
, int cpuId
)
430 } //namespace X86_ISA