2 * Copyright (c) 2007 The Hewlett-Packard Development Company
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
24 * Palo Alto, California 94304
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58 #include "config/full_system.hh"
61 #include "arch/x86/interrupts.hh"
63 #include "arch/x86/intregs.hh"
64 #include "arch/x86/miscregs.hh"
65 #include "arch/x86/segmentregs.hh"
66 #include "arch/x86/utility.hh"
67 #include "arch/x86/x86_traits.hh"
68 #include "cpu/base.hh"
69 #include "sim/system.hh"
73 uint64_t getArgument(ThreadContext
*tc
, int number
, bool fp
) {
75 panic("getArgument() not implemented for x86!\n");
77 panic("getArgument() only implemented for FULL_SYSTEM\n");
83 void initCPU(ThreadContext
*tc
, int cpuId
)
85 // The otherwise unmodified integer registers should be set to 0.
86 for (int index
= 0; index
< NUM_INTREGS
; index
++) {
87 tc
->setIntReg(index
, 0);
90 // These next two loops zero internal microcode and implicit registers.
91 // They aren't specified by the ISA but are used internally by M5's
93 for (int index
= 0; index
< NumMicroIntRegs
; index
++) {
94 tc
->setIntReg(INTREG_MICRO(index
), 0);
97 for (int index
= 0; index
< NumImplicitIntRegs
; index
++) {
98 tc
->setIntReg(INTREG_IMPLICIT(index
), 0);
101 // Set integer register EAX to 0 to indicate that the optional BIST
102 // passed. No BIST actually runs, but software may still check this
103 // register for errors.
104 tc
->setIntReg(INTREG_RAX
, 0);
106 //The following values are dictated by the architecture for after a RESET#
107 tc
->setMiscReg(MISCREG_CR0
, 0x0000000060000010ULL
);
108 tc
->setMiscReg(MISCREG_CR2
, 0);
109 tc
->setMiscReg(MISCREG_CR3
, 0);
110 tc
->setMiscReg(MISCREG_CR4
, 0);
111 tc
->setMiscReg(MISCREG_CR8
, 0);
113 tc
->setMiscReg(MISCREG_RFLAGS
, 0x0000000000000002ULL
);
115 tc
->setMiscReg(MISCREG_EFER
, 0);
117 SegAttr dataAttr
= 0;
118 dataAttr
.writable
= 1;
119 dataAttr
.readable
= 1;
120 dataAttr
.expandDown
= 0;
122 dataAttr
.defaultSize
= 0;
124 for (int seg
= 0; seg
!= NUM_SEGMENTREGS
; seg
++) {
125 tc
->setMiscReg(MISCREG_SEG_SEL(seg
), 0);
126 tc
->setMiscReg(MISCREG_SEG_BASE(seg
), 0);
127 tc
->setMiscReg(MISCREG_SEG_EFF_BASE(seg
), 0);
128 tc
->setMiscReg(MISCREG_SEG_LIMIT(seg
), 0xffff);
129 tc
->setMiscReg(MISCREG_SEG_ATTR(seg
), dataAttr
);
132 SegAttr codeAttr
= 0;
133 codeAttr
.writable
= 0;
134 codeAttr
.readable
= 1;
135 codeAttr
.expandDown
= 0;
137 codeAttr
.defaultSize
= 0;
139 tc
->setMiscReg(MISCREG_CS
, 0xf000);
140 tc
->setMiscReg(MISCREG_CS_BASE
,
141 0x00000000ffff0000ULL
);
142 tc
->setMiscReg(MISCREG_CS_EFF_BASE
,
143 0x00000000ffff0000ULL
);
144 // This has the base value pre-added.
145 tc
->setMiscReg(MISCREG_CS_LIMIT
, 0xffffffff);
146 tc
->setMiscReg(MISCREG_CS_ATTR
, codeAttr
);
148 tc
->setPC(0x000000000000fff0ULL
+
149 tc
->readMiscReg(MISCREG_CS_BASE
));
150 tc
->setNextPC(tc
->readPC() + sizeof(MachInst
));
152 tc
->setMiscReg(MISCREG_TSG_BASE
, 0);
153 tc
->setMiscReg(MISCREG_TSG_LIMIT
, 0xffff);
155 tc
->setMiscReg(MISCREG_IDTR_BASE
, 0);
156 tc
->setMiscReg(MISCREG_IDTR_LIMIT
, 0xffff);
158 tc
->setMiscReg(MISCREG_TSL
, 0);
159 tc
->setMiscReg(MISCREG_TSL_BASE
, 0);
160 tc
->setMiscReg(MISCREG_TSL_LIMIT
, 0xffff);
161 tc
->setMiscReg(MISCREG_TSL_ATTR
, 0);
163 tc
->setMiscReg(MISCREG_TR
, 0);
164 tc
->setMiscReg(MISCREG_TR_BASE
, 0);
165 tc
->setMiscReg(MISCREG_TR_LIMIT
, 0xffff);
166 tc
->setMiscReg(MISCREG_TR_ATTR
, 0);
168 // This value should be the family/model/stepping of the processor.
169 // (page 418). It should be consistent with the value from CPUID, but the
170 // actual value probably doesn't matter much.
171 tc
->setIntReg(INTREG_RDX
, 0);
173 // TODO initialize x87, 64 bit, and 128 bit media state
175 tc
->setMiscReg(MISCREG_MTRRCAP
, 0x0508);
176 for (int i
= 0; i
< 8; i
++) {
177 tc
->setMiscReg(MISCREG_MTRR_PHYS_BASE(i
), 0);
178 tc
->setMiscReg(MISCREG_MTRR_PHYS_MASK(i
), 0);
180 tc
->setMiscReg(MISCREG_MTRR_FIX_64K_00000
, 0);
181 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_80000
, 0);
182 tc
->setMiscReg(MISCREG_MTRR_FIX_16K_A0000
, 0);
183 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C0000
, 0);
184 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_C8000
, 0);
185 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D0000
, 0);
186 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_D8000
, 0);
187 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E0000
, 0);
188 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_E8000
, 0);
189 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F0000
, 0);
190 tc
->setMiscReg(MISCREG_MTRR_FIX_4K_F8000
, 0);
192 tc
->setMiscReg(MISCREG_DEF_TYPE
, 0);
194 tc
->setMiscReg(MISCREG_MCG_CAP
, 0x104);
195 tc
->setMiscReg(MISCREG_MCG_STATUS
, 0);
196 tc
->setMiscReg(MISCREG_MCG_CTL
, 0);
198 for (int i
= 0; i
< 5; i
++) {
199 tc
->setMiscReg(MISCREG_MC_CTL(i
), 0);
200 tc
->setMiscReg(MISCREG_MC_STATUS(i
), 0);
201 tc
->setMiscReg(MISCREG_MC_ADDR(i
), 0);
202 tc
->setMiscReg(MISCREG_MC_MISC(i
), 0);
205 tc
->setMiscReg(MISCREG_DR0
, 0);
206 tc
->setMiscReg(MISCREG_DR1
, 0);
207 tc
->setMiscReg(MISCREG_DR2
, 0);
208 tc
->setMiscReg(MISCREG_DR3
, 0);
210 tc
->setMiscReg(MISCREG_DR6
, 0x00000000ffff0ff0ULL
);
211 tc
->setMiscReg(MISCREG_DR7
, 0x0000000000000400ULL
);
213 tc
->setMiscReg(MISCREG_TSC
, 0);
214 tc
->setMiscReg(MISCREG_TSC_AUX
, 0);
216 for (int i
= 0; i
< 4; i
++) {
217 tc
->setMiscReg(MISCREG_PERF_EVT_SEL(i
), 0);
218 tc
->setMiscReg(MISCREG_PERF_EVT_CTR(i
), 0);
221 tc
->setMiscReg(MISCREG_STAR
, 0);
222 tc
->setMiscReg(MISCREG_LSTAR
, 0);
223 tc
->setMiscReg(MISCREG_CSTAR
, 0);
225 tc
->setMiscReg(MISCREG_SF_MASK
, 0);
227 tc
->setMiscReg(MISCREG_KERNEL_GS_BASE
, 0);
229 tc
->setMiscReg(MISCREG_SYSENTER_CS
, 0);
230 tc
->setMiscReg(MISCREG_SYSENTER_ESP
, 0);
231 tc
->setMiscReg(MISCREG_SYSENTER_EIP
, 0);
233 tc
->setMiscReg(MISCREG_PAT
, 0x0007040600070406ULL
);
235 tc
->setMiscReg(MISCREG_SYSCFG
, 0x20601);
237 tc
->setMiscReg(MISCREG_IORR_BASE0
, 0);
238 tc
->setMiscReg(MISCREG_IORR_BASE1
, 0);
240 tc
->setMiscReg(MISCREG_IORR_MASK0
, 0);
241 tc
->setMiscReg(MISCREG_IORR_MASK1
, 0);
243 tc
->setMiscReg(MISCREG_TOP_MEM
, 0x4000000);
244 tc
->setMiscReg(MISCREG_TOP_MEM2
, 0x0);
246 tc
->setMiscReg(MISCREG_DEBUG_CTL_MSR
, 0);
247 tc
->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP
, 0);
248 tc
->setMiscReg(MISCREG_LAST_BRANCH_TO_IP
, 0);
249 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP
, 0);
250 tc
->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP
, 0);
252 // Invalidate the caches (this should already be done for us)
254 // TODO Turn on the APIC. This should be handled elsewhere but it isn't
255 // currently being handled at all.
257 LocalApicBase lApicBase
= 0;
258 lApicBase
.base
= 0xFEE00000 >> 12;
259 lApicBase
.enable
= 1;
260 lApicBase
.bsp
= (cpuId
== 0);
261 tc
->setMiscReg(MISCREG_APIC_BASE
, lApicBase
);
263 Interrupts
* interrupts
= dynamic_cast<Interrupts
*>(
264 tc
->getCpuPtr()->getInterruptController());
267 interrupts
->setRegNoEffect(APIC_ID
, cpuId
<< 24);
269 interrupts
->setRegNoEffect(APIC_VERSION
, (5 << 16) | 0x14);
271 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
273 tc
->setMiscReg(MISCREG_VM_CR
, 0);
274 tc
->setMiscReg(MISCREG_IGNNE
, 0);
275 tc
->setMiscReg(MISCREG_SMM_CTL
, 0);
276 tc
->setMiscReg(MISCREG_VM_HSAVE_PA
, 0);
282 void startupCPU(ThreadContext
*tc
, int cpuId
)
287 // This is an application processor (AP). It should be initialized to
288 // look like only the BIOS POST has run on it and put then put it into
296 void startupCPU(ThreadContext
*tc
, int cpuId
)
303 } //namespace X86_ISA