2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
36 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
39 resize_qreg_array(struct v3d_compile
*c
,
44 if (*size
>= decl_size
)
47 uint32_t old_size
= *size
;
48 *size
= MAX2(*size
* 2, decl_size
);
49 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
51 fprintf(stderr
, "Malloc failure\n");
55 for (uint32_t i
= old_size
; i
< *size
; i
++)
56 (*regs
)[i
] = c
->undef
;
60 vir_emit_thrsw(struct v3d_compile
*c
)
65 /* Always thread switch after each texture operation for now.
67 * We could do better by batching a bunch of texture fetches up and
68 * then doing one thread switch and collecting all their results
71 c
->last_thrsw
= vir_NOP(c
);
72 c
->last_thrsw
->qpu
.sig
.thrsw
= true;
73 c
->last_thrsw_at_top_level
= (c
->execute
.file
== QFILE_NULL
);
77 vir_SFU(struct v3d_compile
*c
, int waddr
, struct qreg src
)
79 vir_FMOV_dest(c
, vir_reg(QFILE_MAGIC
, waddr
), src
);
80 return vir_FMOV(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R4
));
84 indirect_uniform_load(struct v3d_compile
*c
, nir_intrinsic_instr
*intr
)
86 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
87 uint32_t offset
= nir_intrinsic_base(intr
);
88 struct v3d_ubo_range
*range
= NULL
;
91 for (i
= 0; i
< c
->num_ubo_ranges
; i
++) {
92 range
= &c
->ubo_ranges
[i
];
93 if (offset
>= range
->src_offset
&&
94 offset
< range
->src_offset
+ range
->size
) {
98 /* The driver-location-based offset always has to be within a declared
101 assert(i
!= c
->num_ubo_ranges
);
102 if (!c
->ubo_range_used
[i
]) {
103 c
->ubo_range_used
[i
] = true;
104 range
->dst_offset
= c
->next_ubo_dst_offset
;
105 c
->next_ubo_dst_offset
+= range
->size
;
108 offset
-= range
->src_offset
;
110 if (range
->dst_offset
+ offset
!= 0) {
111 indirect_offset
= vir_ADD(c
, indirect_offset
,
112 vir_uniform_ui(c
, range
->dst_offset
+
116 /* Adjust for where we stored the TGSI register base. */
118 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
),
119 vir_uniform(c
, QUNIFORM_UBO_ADDR
, 0),
127 ntq_init_ssa_def(struct v3d_compile
*c
, nir_ssa_def
*def
)
129 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
130 def
->num_components
);
131 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
136 * This function is responsible for getting VIR results into the associated
137 * storage for a NIR instruction.
139 * If it's a NIR SSA def, then we just set the associated hash table entry to
142 * If it's a NIR reg, then we need to update the existing qreg assigned to the
143 * NIR destination with the incoming value. To do that without introducing
144 * new MOVs, we require that the incoming qreg either be a uniform, or be
145 * SSA-defined by the previous VIR instruction in the block and rewritable by
146 * this function. That lets us sneak ahead and insert the SF flag beforehand
147 * (knowing that the previous instruction doesn't depend on flags) and rewrite
148 * its destination to be the NIR reg's destination
151 ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
154 struct qinst
*last_inst
= NULL
;
155 if (!list_empty(&c
->cur_block
->instructions
))
156 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
158 assert(result
.file
== QFILE_UNIF
||
159 (result
.file
== QFILE_TEMP
&&
160 last_inst
&& last_inst
== c
->defs
[result
.index
]));
163 assert(chan
< dest
->ssa
.num_components
);
166 struct hash_entry
*entry
=
167 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
172 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
174 qregs
[chan
] = result
;
176 nir_register
*reg
= dest
->reg
.reg
;
177 assert(dest
->reg
.base_offset
== 0);
178 assert(reg
->num_array_elems
== 0);
179 struct hash_entry
*entry
=
180 _mesa_hash_table_search(c
->def_ht
, reg
);
181 struct qreg
*qregs
= entry
->data
;
183 /* Insert a MOV if the source wasn't an SSA def in the
184 * previous instruction.
186 if (result
.file
== QFILE_UNIF
) {
187 result
= vir_MOV(c
, result
);
188 last_inst
= c
->defs
[result
.index
];
191 /* We know they're both temps, so just rewrite index. */
192 c
->defs
[last_inst
->dst
.index
] = NULL
;
193 last_inst
->dst
.index
= qregs
[chan
].index
;
195 /* If we're in control flow, then make this update of the reg
196 * conditional on the execution mask.
198 if (c
->execute
.file
!= QFILE_NULL
) {
199 last_inst
->dst
.index
= qregs
[chan
].index
;
201 /* Set the flags to the current exec mask. To insert
202 * the flags push, we temporarily remove our SSA
205 list_del(&last_inst
->link
);
206 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
207 list_addtail(&last_inst
->link
,
208 &c
->cur_block
->instructions
);
210 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
211 last_inst
->cond_is_exec_mask
= true;
217 ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
)
219 struct hash_entry
*entry
;
221 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
222 assert(i
< src
.ssa
->num_components
);
224 nir_register
*reg
= src
.reg
.reg
;
225 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
226 assert(reg
->num_array_elems
== 0);
227 assert(src
.reg
.base_offset
== 0);
228 assert(i
< reg
->num_components
);
231 struct qreg
*qregs
= entry
->data
;
236 ntq_get_alu_src(struct v3d_compile
*c
, nir_alu_instr
*instr
,
239 assert(util_is_power_of_two(instr
->dest
.write_mask
));
240 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
241 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
242 instr
->src
[src
].swizzle
[chan
]);
244 assert(!instr
->src
[src
].abs
);
245 assert(!instr
->src
[src
].negate
);
250 static inline struct qreg
251 vir_SAT(struct v3d_compile
*c
, struct qreg val
)
254 vir_FMIN(c
, val
, vir_uniform_f(c
, 1.0)),
255 vir_uniform_f(c
, 0.0));
259 ntq_umul(struct v3d_compile
*c
, struct qreg src0
, struct qreg src1
)
261 vir_MULTOP(c
, src0
, src1
);
262 return vir_UMUL24(c
, src0
, src1
);
266 ntq_minify(struct v3d_compile
*c
, struct qreg size
, struct qreg level
)
268 return vir_MAX(c
, vir_SHR(c
, size
, level
), vir_uniform_ui(c
, 1));
272 ntq_emit_txs(struct v3d_compile
*c
, nir_tex_instr
*instr
)
274 unsigned unit
= instr
->texture_index
;
275 int lod_index
= nir_tex_instr_src_index(instr
, nir_tex_src_lod
);
276 int dest_size
= nir_tex_instr_dest_size(instr
);
278 struct qreg lod
= c
->undef
;
280 lod
= ntq_get_src(c
, instr
->src
[lod_index
].src
, 0);
282 for (int i
= 0; i
< dest_size
; i
++) {
284 enum quniform_contents contents
;
286 if (instr
->is_array
&& i
== dest_size
- 1)
287 contents
= QUNIFORM_TEXTURE_ARRAY_SIZE
;
289 contents
= QUNIFORM_TEXTURE_WIDTH
+ i
;
291 struct qreg size
= vir_uniform(c
, contents
, unit
);
293 switch (instr
->sampler_dim
) {
294 case GLSL_SAMPLER_DIM_1D
:
295 case GLSL_SAMPLER_DIM_2D
:
296 case GLSL_SAMPLER_DIM_3D
:
297 case GLSL_SAMPLER_DIM_CUBE
:
298 /* Don't minify the array size. */
299 if (!(instr
->is_array
&& i
== dest_size
- 1)) {
300 size
= ntq_minify(c
, size
, lod
);
304 case GLSL_SAMPLER_DIM_RECT
:
305 /* There's no LOD field for rects */
309 unreachable("Bad sampler type");
312 ntq_store_dest(c
, &instr
->dest
, i
, size
);
317 ntq_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
)
319 unsigned unit
= instr
->texture_index
;
321 /* Since each texture sampling op requires uploading uniforms to
322 * reference the texture, there's no HW support for texture size and
323 * you just upload uniforms containing the size.
326 case nir_texop_query_levels
:
327 ntq_store_dest(c
, &instr
->dest
, 0,
328 vir_uniform(c
, QUNIFORM_TEXTURE_LEVELS
, unit
));
331 ntq_emit_txs(c
, instr
);
337 if (c
->devinfo
->ver
>= 40)
338 v3d40_vir_emit_tex(c
, instr
);
340 v3d33_vir_emit_tex(c
, instr
);
344 ntq_fsincos(struct v3d_compile
*c
, struct qreg src
, bool is_cos
)
346 struct qreg input
= vir_FMUL(c
, src
, vir_uniform_f(c
, 1.0f
/ M_PI
));
348 input
= vir_FADD(c
, input
, vir_uniform_f(c
, 0.5));
350 struct qreg periods
= vir_FROUND(c
, input
);
351 struct qreg sin_output
= vir_SFU(c
, V3D_QPU_WADDR_SIN
,
352 vir_FSUB(c
, input
, periods
));
353 return vir_XOR(c
, sin_output
, vir_SHL(c
,
354 vir_FTOIN(c
, periods
),
355 vir_uniform_ui(c
, -1)));
359 ntq_fsign(struct v3d_compile
*c
, struct qreg src
)
361 struct qreg t
= vir_get_temp(c
);
363 vir_MOV_dest(c
, t
, vir_uniform_f(c
, 0.0));
364 vir_PF(c
, vir_FMOV(c
, src
), V3D_QPU_PF_PUSHZ
);
365 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_f(c
, 1.0));
366 vir_PF(c
, vir_FMOV(c
, src
), V3D_QPU_PF_PUSHN
);
367 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_f(c
, -1.0));
368 return vir_MOV(c
, t
);
372 ntq_isign(struct v3d_compile
*c
, struct qreg src
)
374 struct qreg t
= vir_get_temp(c
);
376 vir_MOV_dest(c
, t
, vir_uniform_ui(c
, 0));
377 vir_PF(c
, vir_MOV(c
, src
), V3D_QPU_PF_PUSHZ
);
378 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_ui(c
, 1));
379 vir_PF(c
, vir_MOV(c
, src
), V3D_QPU_PF_PUSHN
);
380 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_ui(c
, -1));
381 return vir_MOV(c
, t
);
385 emit_fragcoord_input(struct v3d_compile
*c
, int attr
)
387 c
->inputs
[attr
* 4 + 0] = vir_FXCD(c
);
388 c
->inputs
[attr
* 4 + 1] = vir_FYCD(c
);
389 c
->inputs
[attr
* 4 + 2] = c
->payload_z
;
390 c
->inputs
[attr
* 4 + 3] = vir_SFU(c
, V3D_QPU_WADDR_RECIP
,
395 emit_fragment_varying(struct v3d_compile
*c
, nir_variable
*var
,
398 struct qreg r3
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R3
);
399 struct qreg r5
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R5
);
402 if (c
->devinfo
->ver
>= 41) {
403 struct qinst
*ldvary
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
405 ldvary
->qpu
.sig
.ldvary
= true;
406 vary
= vir_emit_def(c
, ldvary
);
408 vir_NOP(c
)->qpu
.sig
.ldvary
= true;
412 /* For gl_PointCoord input or distance along a line, we'll be called
413 * with no nir_variable, and we don't count toward VPM size so we
414 * don't track an input slot.
417 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
420 int i
= c
->num_inputs
++;
421 c
->input_slots
[i
] = v3d_slot_from_slot_and_component(var
->data
.location
,
424 switch (var
->data
.interpolation
) {
425 case INTERP_MODE_NONE
:
426 /* If a gl_FrontColor or gl_BackColor input has no interp
427 * qualifier, then if we're using glShadeModel(GL_FLAT) it
428 * needs to be flat shaded.
430 switch (var
->data
.location
) {
431 case VARYING_SLOT_COL0
:
432 case VARYING_SLOT_COL1
:
433 case VARYING_SLOT_BFC0
:
434 case VARYING_SLOT_BFC1
:
435 if (c
->fs_key
->shade_model_flat
) {
436 BITSET_SET(c
->flat_shade_flags
, i
);
437 vir_MOV_dest(c
, c
->undef
, vary
);
438 return vir_MOV(c
, r5
);
440 return vir_FADD(c
, vir_FMUL(c
, vary
,
447 case INTERP_MODE_SMOOTH
:
448 if (var
->data
.centroid
) {
449 return vir_FADD(c
, vir_FMUL(c
, vary
,
450 c
->payload_w_centroid
), r5
);
452 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
454 case INTERP_MODE_NOPERSPECTIVE
:
455 /* C appears after the mov from the varying.
456 XXX: improve ldvary setup.
458 return vir_FADD(c
, vir_MOV(c
, vary
), r5
);
459 case INTERP_MODE_FLAT
:
460 BITSET_SET(c
->flat_shade_flags
, i
);
461 vir_MOV_dest(c
, c
->undef
, vary
);
462 return vir_MOV(c
, r5
);
464 unreachable("Bad interp mode");
469 emit_fragment_input(struct v3d_compile
*c
, int attr
, nir_variable
*var
)
471 for (int i
= 0; i
< glsl_get_vector_elements(var
->type
); i
++) {
472 int chan
= var
->data
.location_frac
+ i
;
473 c
->inputs
[attr
* 4 + chan
] =
474 emit_fragment_varying(c
, var
, chan
);
479 add_output(struct v3d_compile
*c
,
480 uint32_t decl_offset
,
484 uint32_t old_array_size
= c
->outputs_array_size
;
485 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
488 if (old_array_size
!= c
->outputs_array_size
) {
489 c
->output_slots
= reralloc(c
,
491 struct v3d_varying_slot
,
492 c
->outputs_array_size
);
495 c
->output_slots
[decl_offset
] =
496 v3d_slot_from_slot_and_component(slot
, swizzle
);
500 declare_uniform_range(struct v3d_compile
*c
, uint32_t start
, uint32_t size
)
502 unsigned array_id
= c
->num_ubo_ranges
++;
503 if (array_id
>= c
->ubo_ranges_array_size
) {
504 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
506 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
507 struct v3d_ubo_range
,
508 c
->ubo_ranges_array_size
);
509 c
->ubo_range_used
= reralloc(c
, c
->ubo_range_used
,
511 c
->ubo_ranges_array_size
);
514 c
->ubo_ranges
[array_id
].dst_offset
= 0;
515 c
->ubo_ranges
[array_id
].src_offset
= start
;
516 c
->ubo_ranges
[array_id
].size
= size
;
517 c
->ubo_range_used
[array_id
] = false;
521 * If compare_instr is a valid comparison instruction, emits the
522 * compare_instr's comparison and returns the sel_instr's return value based
523 * on the compare_instr's result.
526 ntq_emit_comparison(struct v3d_compile
*c
, struct qreg
*dest
,
527 nir_alu_instr
*compare_instr
,
528 nir_alu_instr
*sel_instr
)
530 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
531 struct qreg src1
= ntq_get_alu_src(c
, compare_instr
, 1);
532 bool cond_invert
= false;
534 switch (compare_instr
->op
) {
537 vir_PF(c
, vir_FCMP(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
540 vir_PF(c
, vir_XOR(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
545 vir_PF(c
, vir_FCMP(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
549 vir_PF(c
, vir_XOR(c
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
555 vir_PF(c
, vir_FCMP(c
, src1
, src0
), V3D_QPU_PF_PUSHC
);
558 vir_PF(c
, vir_MIN(c
, src1
, src0
), V3D_QPU_PF_PUSHC
);
562 vir_PF(c
, vir_SUB(c
, src0
, src1
), V3D_QPU_PF_PUSHC
);
568 vir_PF(c
, vir_FCMP(c
, src0
, src1
), V3D_QPU_PF_PUSHN
);
571 vir_PF(c
, vir_MIN(c
, src1
, src0
), V3D_QPU_PF_PUSHC
);
574 vir_PF(c
, vir_SUB(c
, src0
, src1
), V3D_QPU_PF_PUSHC
);
581 enum v3d_qpu_cond cond
= (cond_invert
?
585 switch (sel_instr
->op
) {
590 *dest
= vir_SEL(c
, cond
,
591 vir_uniform_f(c
, 1.0), vir_uniform_f(c
, 0.0));
595 *dest
= vir_SEL(c
, cond
,
596 ntq_get_alu_src(c
, sel_instr
, 1),
597 ntq_get_alu_src(c
, sel_instr
, 2));
601 *dest
= vir_SEL(c
, cond
,
602 vir_uniform_ui(c
, ~0), vir_uniform_ui(c
, 0));
606 /* Make the temporary for nir_store_dest(). */
607 *dest
= vir_MOV(c
, *dest
);
613 * Attempts to fold a comparison generating a boolean result into the
614 * condition code for selecting between two values, instead of comparing the
615 * boolean result against 0 to generate the condition code.
617 static struct qreg
ntq_emit_bcsel(struct v3d_compile
*c
, nir_alu_instr
*instr
,
620 if (!instr
->src
[0].src
.is_ssa
)
622 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
624 nir_alu_instr
*compare
=
625 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
630 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
634 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
635 return vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
, src
[1], src
[2]));
640 ntq_emit_alu(struct v3d_compile
*c
, nir_alu_instr
*instr
)
642 /* This should always be lowered to ALU operations for V3D. */
643 assert(!instr
->dest
.saturate
);
645 /* Vectors are special in that they have non-scalarized writemasks,
646 * and just take the first swizzle channel for each argument in order
647 * into each writemask channel.
649 if (instr
->op
== nir_op_vec2
||
650 instr
->op
== nir_op_vec3
||
651 instr
->op
== nir_op_vec4
) {
653 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
654 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
655 instr
->src
[i
].swizzle
[0]);
656 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
657 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
658 vir_MOV(c
, srcs
[i
]));
662 /* General case: We can just grab the one used channel per src. */
663 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
664 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
665 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
673 result
= vir_MOV(c
, src
[0]);
677 result
= vir_XOR(c
, src
[0], vir_uniform_ui(c
, 1 << 31));
680 result
= vir_NEG(c
, src
[0]);
684 result
= vir_FMUL(c
, src
[0], src
[1]);
687 result
= vir_FADD(c
, src
[0], src
[1]);
690 result
= vir_FSUB(c
, src
[0], src
[1]);
693 result
= vir_FMIN(c
, src
[0], src
[1]);
696 result
= vir_FMAX(c
, src
[0], src
[1]);
700 result
= vir_FTOIZ(c
, src
[0]);
703 result
= vir_FTOUZ(c
, src
[0]);
706 result
= vir_ITOF(c
, src
[0]);
709 result
= vir_UTOF(c
, src
[0]);
712 result
= vir_AND(c
, src
[0], vir_uniform_f(c
, 1.0));
715 result
= vir_AND(c
, src
[0], vir_uniform_ui(c
, 1));
719 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
720 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
721 vir_uniform_ui(c
, ~0),
722 vir_uniform_ui(c
, 0)));
726 result
= vir_ADD(c
, src
[0], src
[1]);
729 result
= vir_SHR(c
, src
[0], src
[1]);
732 result
= vir_SUB(c
, src
[0], src
[1]);
735 result
= vir_ASR(c
, src
[0], src
[1]);
738 result
= vir_SHL(c
, src
[0], src
[1]);
741 result
= vir_MIN(c
, src
[0], src
[1]);
744 result
= vir_UMIN(c
, src
[0], src
[1]);
747 result
= vir_MAX(c
, src
[0], src
[1]);
750 result
= vir_UMAX(c
, src
[0], src
[1]);
753 result
= vir_AND(c
, src
[0], src
[1]);
756 result
= vir_OR(c
, src
[0], src
[1]);
759 result
= vir_XOR(c
, src
[0], src
[1]);
762 result
= vir_NOT(c
, src
[0]);
766 result
= ntq_umul(c
, src
[0], src
[1]);
783 if (!ntq_emit_comparison(c
, &result
, instr
, instr
)) {
784 fprintf(stderr
, "Bad comparison instruction\n");
789 result
= ntq_emit_bcsel(c
, instr
, src
);
792 vir_PF(c
, src
[0], V3D_QPU_PF_PUSHZ
);
793 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
798 result
= vir_SFU(c
, V3D_QPU_WADDR_RECIP
, src
[0]);
801 result
= vir_SFU(c
, V3D_QPU_WADDR_RSQRT
, src
[0]);
804 result
= vir_SFU(c
, V3D_QPU_WADDR_EXP
, src
[0]);
807 result
= vir_SFU(c
, V3D_QPU_WADDR_LOG
, src
[0]);
811 result
= vir_FCEIL(c
, src
[0]);
814 result
= vir_FFLOOR(c
, src
[0]);
816 case nir_op_fround_even
:
817 result
= vir_FROUND(c
, src
[0]);
820 result
= vir_FTRUNC(c
, src
[0]);
823 result
= vir_FSUB(c
, src
[0], vir_FFLOOR(c
, src
[0]));
827 result
= ntq_fsincos(c
, src
[0], false);
830 result
= ntq_fsincos(c
, src
[0], true);
834 result
= ntq_fsign(c
, src
[0]);
837 result
= ntq_isign(c
, src
[0]);
841 result
= vir_FMOV(c
, src
[0]);
842 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_ABS
);
847 result
= vir_MAX(c
, src
[0],
848 vir_SUB(c
, vir_uniform_ui(c
, 0), src
[0]));
852 case nir_op_fddx_coarse
:
853 case nir_op_fddx_fine
:
854 result
= vir_FDX(c
, src
[0]);
858 case nir_op_fddy_coarse
:
859 case nir_op_fddy_fine
:
860 result
= vir_FDY(c
, src
[0]);
864 fprintf(stderr
, "unknown NIR ALU inst: ");
865 nir_print_instr(&instr
->instr
, stderr
);
866 fprintf(stderr
, "\n");
870 /* We have a scalar result, so the instruction should only have a
871 * single channel written to.
873 assert(util_is_power_of_two(instr
->dest
.write_mask
));
874 ntq_store_dest(c
, &instr
->dest
.dest
,
875 ffs(instr
->dest
.write_mask
) - 1, result
);
878 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
879 * specifier. They come from a register that's preloaded with 0xffffffff
880 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
881 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
883 #define TLB_TYPE_F16_COLOR (3 << 6)
884 #define TLB_TYPE_I32_COLOR (1 << 6)
885 #define TLB_TYPE_F32_COLOR (0 << 6)
886 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
887 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
888 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
889 #define TLB_F16_SWAP_HI_LO (1 << 1)
890 #define TLB_VEC_SIZE_4_F16 (1 << 0)
891 #define TLB_VEC_SIZE_2_F16 (0 << 0)
892 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
894 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
897 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
898 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
899 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
901 /* Stencil is a single 32-bit write. */
902 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
905 emit_frag_end(struct v3d_compile
*c
)
908 if (c->output_sample_mask_index != -1) {
909 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
913 bool has_any_tlb_color_write
= false;
914 for (int rt
= 0; rt
< c
->fs_key
->nr_cbufs
; rt
++) {
915 if (c
->output_color_var
[rt
])
916 has_any_tlb_color_write
= true;
919 if (c
->output_position_index
!= -1) {
920 struct qinst
*inst
= vir_MOV_dest(c
,
921 vir_reg(QFILE_TLBU
, 0),
922 c
->outputs
[c
->output_position_index
]);
924 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
927 TLB_DEPTH_TYPE_PER_PIXEL
|
929 } else if (c
->s
->info
.fs
.uses_discard
|| !has_any_tlb_color_write
) {
930 /* Emit passthrough Z if it needed to be delayed until shader
931 * end due to potential discards.
933 * Since (single-threaded) fragment shaders always need a TLB
934 * write, emit passthrouh Z if we didn't have any color
935 * buffers and flag us as potentially discarding, so that we
936 * can use Z as the TLB write.
938 c
->s
->info
.fs
.uses_discard
= true;
940 struct qinst
*inst
= vir_MOV_dest(c
,
941 vir_reg(QFILE_TLBU
, 0),
942 vir_reg(QFILE_NULL
, 0));
944 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
947 TLB_DEPTH_TYPE_INVARIANT
|
951 /* XXX: Performance improvement: Merge Z write and color writes TLB
955 for (int rt
= 0; rt
< c
->fs_key
->nr_cbufs
; rt
++) {
956 if (!c
->output_color_var
[rt
])
959 nir_variable
*var
= c
->output_color_var
[rt
];
960 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
961 int num_components
= glsl_get_vector_elements(var
->type
);
962 uint32_t conf
= 0xffffff00;
965 conf
|= TLB_SAMPLE_MODE_PER_PIXEL
;
966 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
968 assert(num_components
!= 0);
969 switch (glsl_get_base_type(var
->type
)) {
972 /* The F32 vs I32 distinction was dropped in 4.2. */
973 if (c
->devinfo
->ver
< 42)
974 conf
|= TLB_TYPE_I32_COLOR
;
976 conf
|= TLB_TYPE_F32_COLOR
;
977 conf
|= ((num_components
- 1) <<
978 TLB_VEC_SIZE_MINUS_1_SHIFT
);
980 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLBU
, 0), color
[0]);
981 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
982 vir_uniform_ui(c
, conf
);
984 for (int i
= 1; i
< num_components
; i
++) {
985 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0),
991 struct qreg r
= color
[0];
992 struct qreg g
= color
[1];
993 struct qreg b
= color
[2];
994 struct qreg a
= color
[3];
996 if (c
->fs_key
->f32_color_rb
) {
997 conf
|= TLB_TYPE_F32_COLOR
;
998 conf
|= ((num_components
- 1) <<
999 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1001 conf
|= TLB_TYPE_F16_COLOR
;
1002 conf
|= TLB_F16_SWAP_HI_LO
;
1003 if (num_components
>= 3)
1004 conf
|= TLB_VEC_SIZE_4_F16
;
1006 conf
|= TLB_VEC_SIZE_2_F16
;
1009 if (c
->fs_key
->swap_color_rb
& (1 << rt
)) {
1014 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1015 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLBU
, 0), color
[0]);
1016 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1017 vir_uniform_ui(c
, conf
);
1019 for (int i
= 1; i
< num_components
; i
++) {
1020 inst
= vir_MOV_dest(c
, vir_reg(QFILE_TLB
, 0),
1024 inst
= vir_VFPACK_dest(c
, vir_reg(QFILE_TLB
, 0), r
, g
);
1026 inst
->dst
.file
= QFILE_TLBU
;
1027 inst
->src
[vir_get_implicit_uniform_src(inst
)] =
1028 vir_uniform_ui(c
, conf
);
1031 if (num_components
>= 3)
1032 inst
= vir_VFPACK_dest(c
, vir_reg(QFILE_TLB
, 0), b
, a
);
1041 vir_VPM_WRITE(struct v3d_compile
*c
, struct qreg val
, uint32_t *vpm_index
)
1043 if (c
->devinfo
->ver
>= 40) {
1044 vir_STVPMV(c
, vir_uniform_ui(c
, *vpm_index
), val
);
1045 *vpm_index
= *vpm_index
+ 1;
1047 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_VPM
), val
);
1050 c
->num_vpm_writes
++;
1054 emit_scaled_viewport_write(struct v3d_compile
*c
, struct qreg rcp_w
,
1055 uint32_t *vpm_index
)
1057 for (int i
= 0; i
< 2; i
++) {
1058 struct qreg coord
= c
->outputs
[c
->output_position_index
+ i
];
1059 coord
= vir_FMUL(c
, coord
,
1060 vir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
,
1062 coord
= vir_FMUL(c
, coord
, rcp_w
);
1063 vir_VPM_WRITE(c
, vir_FTOIN(c
, coord
), vpm_index
);
1069 emit_zs_write(struct v3d_compile
*c
, struct qreg rcp_w
, uint32_t *vpm_index
)
1071 struct qreg zscale
= vir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1072 struct qreg zoffset
= vir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1074 struct qreg z
= c
->outputs
[c
->output_position_index
+ 2];
1075 z
= vir_FMUL(c
, z
, zscale
);
1076 z
= vir_FMUL(c
, z
, rcp_w
);
1077 z
= vir_FADD(c
, z
, zoffset
);
1078 vir_VPM_WRITE(c
, z
, vpm_index
);
1082 emit_rcp_wc_write(struct v3d_compile
*c
, struct qreg rcp_w
, uint32_t *vpm_index
)
1084 vir_VPM_WRITE(c
, rcp_w
, vpm_index
);
1088 emit_point_size_write(struct v3d_compile
*c
, uint32_t *vpm_index
)
1090 struct qreg point_size
;
1092 if (c
->output_point_size_index
!= -1)
1093 point_size
= c
->outputs
[c
->output_point_size_index
];
1095 point_size
= vir_uniform_f(c
, 1.0);
1097 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1100 point_size
= vir_FMAX(c
, point_size
, vir_uniform_f(c
, .125));
1102 vir_VPM_WRITE(c
, point_size
, vpm_index
);
1106 emit_vpm_write_setup(struct v3d_compile
*c
)
1108 if (c
->devinfo
->ver
>= 40)
1111 v3d33_vir_vpm_write_setup(c
);
1115 emit_vert_end(struct v3d_compile
*c
)
1117 uint32_t vpm_index
= 0;
1118 struct qreg rcp_w
= vir_SFU(c
, V3D_QPU_WADDR_RECIP
,
1119 c
->outputs
[c
->output_position_index
+ 3]);
1121 emit_vpm_write_setup(c
);
1123 if (c
->vs_key
->is_coord
) {
1124 for (int i
= 0; i
< 4; i
++)
1125 vir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
],
1127 emit_scaled_viewport_write(c
, rcp_w
, &vpm_index
);
1128 if (c
->vs_key
->per_vertex_point_size
) {
1129 emit_point_size_write(c
, &vpm_index
);
1130 /* emit_rcp_wc_write(c, rcp_w); */
1132 /* XXX: Z-only rendering */
1134 emit_zs_write(c
, rcp_w
, &vpm_index
);
1136 emit_scaled_viewport_write(c
, rcp_w
, &vpm_index
);
1137 emit_zs_write(c
, rcp_w
, &vpm_index
);
1138 emit_rcp_wc_write(c
, rcp_w
, &vpm_index
);
1139 if (c
->vs_key
->per_vertex_point_size
)
1140 emit_point_size_write(c
, &vpm_index
);
1143 for (int i
= 0; i
< c
->vs_key
->num_fs_inputs
; i
++) {
1144 struct v3d_varying_slot input
= c
->vs_key
->fs_inputs
[i
];
1147 for (j
= 0; j
< c
->num_outputs
; j
++) {
1148 struct v3d_varying_slot output
= c
->output_slots
[j
];
1150 if (!memcmp(&input
, &output
, sizeof(input
))) {
1151 vir_VPM_WRITE(c
, c
->outputs
[j
],
1156 /* Emit padding if we didn't find a declared VS output for
1159 if (j
== c
->num_outputs
)
1160 vir_VPM_WRITE(c
, vir_uniform_f(c
, 0.0),
1164 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1166 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1171 v3d_optimize_nir(struct nir_shader
*s
)
1178 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1179 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
);
1180 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1181 NIR_PASS(progress
, s
, nir_copy_prop
);
1182 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1183 NIR_PASS(progress
, s
, nir_opt_dce
);
1184 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1185 NIR_PASS(progress
, s
, nir_opt_cse
);
1186 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8);
1187 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1188 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1189 NIR_PASS(progress
, s
, nir_opt_undef
);
1194 driver_location_compare(const void *in_a
, const void *in_b
)
1196 const nir_variable
*const *a
= in_a
;
1197 const nir_variable
*const *b
= in_b
;
1199 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1203 ntq_emit_vpm_read(struct v3d_compile
*c
,
1204 uint32_t *num_components_queued
,
1205 uint32_t *remaining
,
1208 struct qreg vpm
= vir_reg(QFILE_VPM
, vpm_index
);
1210 if (c
->devinfo
->ver
>= 40 ) {
1211 return vir_LDVPMV_IN(c
,
1213 (*num_components_queued
)++));
1216 if (*num_components_queued
!= 0) {
1217 (*num_components_queued
)--;
1219 return vir_MOV(c
, vpm
);
1222 uint32_t num_components
= MIN2(*remaining
, 32);
1224 v3d33_vir_vpm_read_setup(c
, num_components
);
1226 *num_components_queued
= num_components
- 1;
1227 *remaining
-= num_components
;
1230 return vir_MOV(c
, vpm
);
1234 ntq_setup_inputs(struct v3d_compile
*c
)
1236 unsigned num_entries
= 0;
1237 unsigned num_components
= 0;
1238 nir_foreach_variable(var
, &c
->s
->inputs
) {
1240 num_components
+= glsl_get_components(var
->type
);
1243 nir_variable
*vars
[num_entries
];
1246 nir_foreach_variable(var
, &c
->s
->inputs
)
1249 /* Sort the variables so that we emit the input setup in
1250 * driver_location order. This is required for VPM reads, whose data
1251 * is fetched into the VPM in driver_location (TGSI register index)
1254 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1256 uint32_t vpm_components_queued
= 0;
1257 if (c
->s
->info
.stage
== MESA_SHADER_VERTEX
) {
1258 bool uses_iid
= c
->s
->info
.system_values_read
&
1259 (1ull << SYSTEM_VALUE_INSTANCE_ID
);
1260 bool uses_vid
= c
->s
->info
.system_values_read
&
1261 (1ull << SYSTEM_VALUE_VERTEX_ID
);
1263 num_components
+= uses_iid
;
1264 num_components
+= uses_vid
;
1267 c
->iid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1268 &num_components
, ~0);
1272 c
->vid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1273 &num_components
, ~0);
1277 for (unsigned i
= 0; i
< num_entries
; i
++) {
1278 nir_variable
*var
= vars
[i
];
1279 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1280 unsigned loc
= var
->data
.driver_location
;
1282 assert(array_len
== 1);
1284 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1287 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1288 if (var
->data
.location
== VARYING_SLOT_POS
) {
1289 emit_fragcoord_input(c
, loc
);
1290 } else if (var
->data
.location
== VARYING_SLOT_PNTC
||
1291 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1292 (c
->fs_key
->point_sprite_mask
&
1293 (1 << (var
->data
.location
-
1294 VARYING_SLOT_VAR0
))))) {
1295 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1296 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1298 emit_fragment_input(c
, loc
, var
);
1301 int var_components
= glsl_get_components(var
->type
);
1303 for (int i
= 0; i
< var_components
; i
++) {
1304 c
->inputs
[loc
* 4 + i
] =
1305 ntq_emit_vpm_read(c
,
1306 &vpm_components_queued
,
1311 c
->vattr_sizes
[loc
] = var_components
;
1315 if (c
->s
->info
.stage
== MESA_SHADER_VERTEX
) {
1316 if (c
->devinfo
->ver
>= 40) {
1317 assert(vpm_components_queued
== num_components
);
1319 assert(vpm_components_queued
== 0);
1320 assert(num_components
== 0);
1326 ntq_setup_outputs(struct v3d_compile
*c
)
1328 nir_foreach_variable(var
, &c
->s
->outputs
) {
1329 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1330 unsigned loc
= var
->data
.driver_location
* 4;
1332 assert(array_len
== 1);
1335 for (int i
= 0; i
< glsl_get_vector_elements(var
->type
); i
++) {
1336 add_output(c
, loc
+ var
->data
.location_frac
+ i
,
1338 var
->data
.location_frac
+ i
);
1341 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1342 switch (var
->data
.location
) {
1343 case FRAG_RESULT_COLOR
:
1344 c
->output_color_var
[0] = var
;
1345 c
->output_color_var
[1] = var
;
1346 c
->output_color_var
[2] = var
;
1347 c
->output_color_var
[3] = var
;
1349 case FRAG_RESULT_DATA0
:
1350 case FRAG_RESULT_DATA1
:
1351 case FRAG_RESULT_DATA2
:
1352 case FRAG_RESULT_DATA3
:
1353 c
->output_color_var
[var
->data
.location
-
1354 FRAG_RESULT_DATA0
] = var
;
1356 case FRAG_RESULT_DEPTH
:
1357 c
->output_position_index
= loc
;
1359 case FRAG_RESULT_SAMPLE_MASK
:
1360 c
->output_sample_mask_index
= loc
;
1364 switch (var
->data
.location
) {
1365 case VARYING_SLOT_POS
:
1366 c
->output_position_index
= loc
;
1368 case VARYING_SLOT_PSIZ
:
1369 c
->output_point_size_index
= loc
;
1377 ntq_setup_uniforms(struct v3d_compile
*c
)
1379 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1380 uint32_t vec4_count
= glsl_count_attribute_slots(var
->type
,
1382 unsigned vec4_size
= 4 * sizeof(float);
1384 declare_uniform_range(c
, var
->data
.driver_location
* vec4_size
,
1385 vec4_count
* vec4_size
);
1391 * Sets up the mapping from nir_register to struct qreg *.
1393 * Each nir_register gets a struct qreg per 32-bit component being stored.
1396 ntq_setup_registers(struct v3d_compile
*c
, struct exec_list
*list
)
1398 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1399 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1400 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1402 nir_reg
->num_components
);
1404 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1406 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1407 qregs
[i
] = vir_get_temp(c
);
1412 ntq_emit_load_const(struct v3d_compile
*c
, nir_load_const_instr
*instr
)
1414 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1415 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1416 qregs
[i
] = vir_uniform_ui(c
, instr
->value
.u32
[i
]);
1418 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1422 ntq_emit_ssa_undef(struct v3d_compile
*c
, nir_ssa_undef_instr
*instr
)
1424 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1426 /* VIR needs there to be *some* value, so pick 0 (same as for
1427 * ntq_setup_registers().
1429 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1430 qregs
[i
] = vir_uniform_ui(c
, 0);
1434 ntq_emit_intrinsic(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1436 nir_const_value
*const_offset
;
1439 switch (instr
->intrinsic
) {
1440 case nir_intrinsic_load_uniform
:
1441 assert(instr
->num_components
== 1);
1442 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1444 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1445 assert(offset
% 4 == 0);
1446 /* We need dwords */
1447 offset
= offset
/ 4;
1448 ntq_store_dest(c
, &instr
->dest
, 0,
1449 vir_uniform(c
, QUNIFORM_UNIFORM
,
1452 ntq_store_dest(c
, &instr
->dest
, 0,
1453 indirect_uniform_load(c
, instr
));
1457 case nir_intrinsic_load_ubo
:
1458 for (int i
= 0; i
< instr
->num_components
; i
++) {
1459 int ubo
= nir_src_as_const_value(instr
->src
[0])->u32
[0];
1461 /* Adjust for where we stored the TGSI register base. */
1463 vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
),
1464 vir_uniform(c
, QUNIFORM_UBO_ADDR
, 1 + ubo
),
1466 ntq_get_src(c
, instr
->src
[1], 0),
1467 vir_uniform_ui(c
, i
* 4)));
1471 ntq_store_dest(c
, &instr
->dest
, i
, vir_LDTMU(c
));
1475 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1477 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1478 assert(offset
% 4 == 0);
1479 /* We need dwords */
1480 offset
= offset
/ 4;
1481 ntq_store_dest(c
, &instr
->dest
, 0,
1482 vir_uniform(c
, QUNIFORM_UNIFORM
,
1485 ntq_store_dest(c
, &instr
->dest
, 0,
1486 indirect_uniform_load(c
, instr
));
1490 case nir_intrinsic_load_user_clip_plane
:
1491 for (int i
= 0; i
< instr
->num_components
; i
++) {
1492 ntq_store_dest(c
, &instr
->dest
, i
,
1493 vir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1494 nir_intrinsic_ucp_id(instr
) *
1499 case nir_intrinsic_load_alpha_ref_float
:
1500 ntq_store_dest(c
, &instr
->dest
, 0,
1501 vir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1504 case nir_intrinsic_load_sample_mask_in
:
1505 ntq_store_dest(c
, &instr
->dest
, 0,
1506 vir_uniform(c
, QUNIFORM_SAMPLE_MASK
, 0));
1509 case nir_intrinsic_load_front_face
:
1510 /* The register contains 0 (front) or 1 (back), and we need to
1511 * turn it into a NIR bool where true means front.
1513 ntq_store_dest(c
, &instr
->dest
, 0,
1515 vir_uniform_ui(c
, -1),
1519 case nir_intrinsic_load_instance_id
:
1520 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->iid
));
1523 case nir_intrinsic_load_vertex_id
:
1524 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->vid
));
1527 case nir_intrinsic_load_input
:
1528 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1529 assert(const_offset
&& "v3d doesn't support indirect inputs");
1530 for (int i
= 0; i
< instr
->num_components
; i
++) {
1531 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1532 int comp
= nir_intrinsic_component(instr
) + i
;
1533 ntq_store_dest(c
, &instr
->dest
, i
,
1534 vir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1538 case nir_intrinsic_store_output
:
1539 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1540 assert(const_offset
&& "v3d doesn't support indirect outputs");
1541 offset
= ((nir_intrinsic_base(instr
) +
1542 const_offset
->u32
[0]) * 4 +
1543 nir_intrinsic_component(instr
));
1545 for (int i
= 0; i
< instr
->num_components
; i
++) {
1546 c
->outputs
[offset
+ i
] =
1547 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
1549 c
->num_outputs
= MAX2(c
->num_outputs
,
1550 offset
+ instr
->num_components
);
1553 case nir_intrinsic_discard
:
1554 if (c
->execute
.file
!= QFILE_NULL
) {
1555 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1556 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1557 vir_uniform_ui(c
, 0)),
1560 vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1561 vir_uniform_ui(c
, 0));
1565 case nir_intrinsic_discard_if
: {
1566 /* true (~0) if we're discarding */
1567 struct qreg cond
= ntq_get_src(c
, instr
->src
[0], 0);
1569 if (c
->execute
.file
!= QFILE_NULL
) {
1570 /* execute == 0 means the channel is active. Invert
1571 * the condition so that we can use zero as "executing
1574 vir_PF(c
, vir_OR(c
, c
->execute
, vir_NOT(c
, cond
)),
1576 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1577 vir_uniform_ui(c
, 0)),
1580 vir_PF(c
, cond
, V3D_QPU_PF_PUSHZ
);
1581 vir_set_cond(vir_SETMSF_dest(c
, vir_reg(QFILE_NULL
, 0),
1582 vir_uniform_ui(c
, 0)),
1590 fprintf(stderr
, "Unknown intrinsic: ");
1591 nir_print_instr(&instr
->instr
, stderr
);
1592 fprintf(stderr
, "\n");
1597 /* Clears (activates) the execute flags for any channels whose jump target
1598 * matches this block.
1601 ntq_activate_execute_for_block(struct v3d_compile
*c
)
1603 vir_PF(c
, vir_XOR(c
, c
->execute
, vir_uniform_ui(c
, c
->cur_block
->index
)),
1606 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
1610 ntq_emit_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
1612 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
1613 bool empty_else_block
=
1614 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
1615 exec_list_is_empty(&nir_else_block
->instr_list
));
1617 struct qblock
*then_block
= vir_new_block(c
);
1618 struct qblock
*after_block
= vir_new_block(c
);
1619 struct qblock
*else_block
;
1620 if (empty_else_block
)
1621 else_block
= after_block
;
1623 else_block
= vir_new_block(c
);
1625 bool was_top_level
= false;
1626 if (c
->execute
.file
== QFILE_NULL
) {
1627 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
1628 was_top_level
= true;
1631 /* Set A for executing (execute == 0) and jumping (if->condition ==
1632 * 0) channels, and then update execute flags for those to point to
1637 ntq_get_src(c
, if_stmt
->condition
, 0)),
1639 vir_MOV_cond(c
, V3D_QPU_COND_IFA
,
1641 vir_uniform_ui(c
, else_block
->index
));
1643 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1646 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1647 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLNA
);
1648 vir_link_blocks(c
->cur_block
, else_block
);
1649 vir_link_blocks(c
->cur_block
, then_block
);
1651 /* Process the THEN block. */
1652 vir_set_emit_block(c
, then_block
);
1653 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1655 if (!empty_else_block
) {
1656 /* Handle the end of the THEN block. First, all currently
1657 * active channels update their execute flags to point to
1660 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1661 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1662 vir_uniform_ui(c
, after_block
->index
));
1664 /* If everything points at ENDIF, then jump there immediately. */
1665 vir_PF(c
, vir_XOR(c
, c
->execute
,
1666 vir_uniform_ui(c
, after_block
->index
)),
1668 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLA
);
1669 vir_link_blocks(c
->cur_block
, after_block
);
1670 vir_link_blocks(c
->cur_block
, else_block
);
1672 vir_set_emit_block(c
, else_block
);
1673 ntq_activate_execute_for_block(c
);
1674 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1677 vir_link_blocks(c
->cur_block
, after_block
);
1679 vir_set_emit_block(c
, after_block
);
1681 c
->execute
= c
->undef
;
1683 ntq_activate_execute_for_block(c
);
1687 ntq_emit_jump(struct v3d_compile
*c
, nir_jump_instr
*jump
)
1689 switch (jump
->type
) {
1690 case nir_jump_break
:
1691 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1692 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1693 vir_uniform_ui(c
, c
->loop_break_block
->index
));
1696 case nir_jump_continue
:
1697 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1698 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
1699 vir_uniform_ui(c
, c
->loop_cont_block
->index
));
1702 case nir_jump_return
:
1703 unreachable("All returns shouold be lowered\n");
1708 ntq_emit_instr(struct v3d_compile
*c
, nir_instr
*instr
)
1710 switch (instr
->type
) {
1711 case nir_instr_type_alu
:
1712 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1715 case nir_instr_type_intrinsic
:
1716 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1719 case nir_instr_type_load_const
:
1720 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1723 case nir_instr_type_ssa_undef
:
1724 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1727 case nir_instr_type_tex
:
1728 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1731 case nir_instr_type_jump
:
1732 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
1736 fprintf(stderr
, "Unknown NIR instr type: ");
1737 nir_print_instr(instr
, stderr
);
1738 fprintf(stderr
, "\n");
1744 ntq_emit_block(struct v3d_compile
*c
, nir_block
*block
)
1746 nir_foreach_instr(instr
, block
) {
1747 ntq_emit_instr(c
, instr
);
1751 static void ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
1754 ntq_emit_loop(struct v3d_compile
*c
, nir_loop
*loop
)
1756 bool was_top_level
= false;
1757 if (c
->execute
.file
== QFILE_NULL
) {
1758 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
1759 was_top_level
= true;
1762 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
1763 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
1765 c
->loop_cont_block
= vir_new_block(c
);
1766 c
->loop_break_block
= vir_new_block(c
);
1768 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1769 vir_set_emit_block(c
, c
->loop_cont_block
);
1770 ntq_activate_execute_for_block(c
);
1772 ntq_emit_cf_list(c
, &loop
->body
);
1774 /* Re-enable any previous continues now, so our ANYA check below
1777 * XXX: Use the .ORZ flags update, instead.
1779 vir_PF(c
, vir_XOR(c
,
1781 vir_uniform_ui(c
, c
->loop_cont_block
->index
)),
1783 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
1785 vir_PF(c
, c
->execute
, V3D_QPU_PF_PUSHZ
);
1787 struct qinst
*branch
= vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ANYA
);
1788 /* Pixels that were not dispatched or have been discarded should not
1789 * contribute to looping again.
1791 branch
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_P
;
1792 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
1793 vir_link_blocks(c
->cur_block
, c
->loop_break_block
);
1795 vir_set_emit_block(c
, c
->loop_break_block
);
1797 c
->execute
= c
->undef
;
1799 ntq_activate_execute_for_block(c
);
1801 c
->loop_break_block
= save_loop_break_block
;
1802 c
->loop_cont_block
= save_loop_cont_block
;
1806 ntq_emit_function(struct v3d_compile
*c
, nir_function_impl
*func
)
1808 fprintf(stderr
, "FUNCTIONS not handled.\n");
1813 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
)
1815 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
1816 switch (node
->type
) {
1817 case nir_cf_node_block
:
1818 ntq_emit_block(c
, nir_cf_node_as_block(node
));
1821 case nir_cf_node_if
:
1822 ntq_emit_if(c
, nir_cf_node_as_if(node
));
1825 case nir_cf_node_loop
:
1826 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
1829 case nir_cf_node_function
:
1830 ntq_emit_function(c
, nir_cf_node_as_function(node
));
1834 fprintf(stderr
, "Unknown NIR node type\n");
1841 ntq_emit_impl(struct v3d_compile
*c
, nir_function_impl
*impl
)
1843 ntq_setup_registers(c
, &impl
->registers
);
1844 ntq_emit_cf_list(c
, &impl
->body
);
1848 nir_to_vir(struct v3d_compile
*c
)
1850 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1851 c
->payload_w
= vir_MOV(c
, vir_reg(QFILE_REG
, 0));
1852 c
->payload_w_centroid
= vir_MOV(c
, vir_reg(QFILE_REG
, 1));
1853 c
->payload_z
= vir_MOV(c
, vir_reg(QFILE_REG
, 2));
1855 if (c
->fs_key
->is_points
) {
1856 c
->point_x
= emit_fragment_varying(c
, NULL
, 0);
1857 c
->point_y
= emit_fragment_varying(c
, NULL
, 0);
1858 } else if (c
->fs_key
->is_lines
) {
1859 c
->line_x
= emit_fragment_varying(c
, NULL
, 0);
1863 ntq_setup_inputs(c
);
1864 ntq_setup_outputs(c
);
1865 ntq_setup_uniforms(c
);
1866 ntq_setup_registers(c
, &c
->s
->registers
);
1868 /* Find the main function and emit the body. */
1869 nir_foreach_function(function
, c
->s
) {
1870 assert(strcmp(function
->name
, "main") == 0);
1871 assert(function
->impl
);
1872 ntq_emit_impl(c
, function
->impl
);
1876 const nir_shader_compiler_options v3d_nir_options
= {
1877 .lower_all_io_to_temps
= true,
1878 .lower_extract_byte
= true,
1879 .lower_extract_word
= true,
1880 .lower_bitfield_insert
= true,
1881 .lower_bitfield_extract
= true,
1882 .lower_pack_unorm_2x16
= true,
1883 .lower_pack_snorm_2x16
= true,
1884 .lower_pack_unorm_4x8
= true,
1885 .lower_pack_snorm_4x8
= true,
1886 .lower_unpack_unorm_4x8
= true,
1887 .lower_unpack_snorm_4x8
= true,
1890 .lower_flrp32
= true,
1893 .lower_fsqrt
= true,
1894 .native_integers
= true,
1900 count_nir_instrs(nir_shader
*nir
)
1903 nir_foreach_function(function
, nir
) {
1904 if (!function
->impl
)
1906 nir_foreach_block(block
, function
->impl
) {
1907 nir_foreach_instr(instr
, block
)
1916 * When demoting a shader down to single-threaded, removes the THRSW
1917 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
1921 vir_remove_thrsw(struct v3d_compile
*c
)
1923 vir_for_each_block(block
, c
) {
1924 vir_for_each_inst_safe(inst
, block
) {
1925 if (inst
->qpu
.sig
.thrsw
)
1926 vir_remove_instruction(c
, inst
);
1930 c
->last_thrsw
= NULL
;
1934 vir_emit_last_thrsw(struct v3d_compile
*c
)
1936 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
1937 * switching, so disable threads if we didn't do any TMU ops (each of
1938 * which would have emitted a THRSW).
1940 if (!c
->last_thrsw_at_top_level
&& c
->devinfo
->ver
< 41) {
1943 vir_remove_thrsw(c
);
1947 /* If we're threaded and the last THRSW was in conditional code, then
1948 * we need to emit another one so that we can flag it as the last
1951 if (c
->last_thrsw
&& !c
->last_thrsw_at_top_level
) {
1952 assert(c
->devinfo
->ver
>= 41);
1956 /* If we're threaded, then we need to mark the last THRSW instruction
1957 * so we can emit a pair of them at QPU emit time.
1959 * For V3D 4.x, we can spawn the non-fragment shaders already in the
1960 * post-last-THRSW state, so we can skip this.
1962 if (!c
->last_thrsw
&& c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
1963 assert(c
->devinfo
->ver
>= 41);
1968 c
->last_thrsw
->is_last_thrsw
= true;
1972 v3d_nir_to_vir(struct v3d_compile
*c
)
1974 if (V3D_DEBUG
& (V3D_DEBUG_NIR
|
1975 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
1976 fprintf(stderr
, "%s prog %d/%d NIR:\n",
1977 vir_get_stage_name(c
),
1978 c
->program_id
, c
->variant_id
);
1979 nir_print_shader(c
->s
, stderr
);
1984 /* Emit the last THRSW before STVPM and TLB writes. */
1985 vir_emit_last_thrsw(c
);
1987 switch (c
->s
->info
.stage
) {
1988 case MESA_SHADER_FRAGMENT
:
1991 case MESA_SHADER_VERTEX
:
1995 unreachable("bad stage");
1998 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
1999 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2000 fprintf(stderr
, "%s prog %d/%d pre-opt VIR:\n",
2001 vir_get_stage_name(c
),
2002 c
->program_id
, c
->variant_id
);
2004 fprintf(stderr
, "\n");
2008 vir_lower_uniforms(c
);
2010 /* XXX: vir_schedule_instructions(c); */
2012 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2013 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2014 fprintf(stderr
, "%s prog %d/%d VIR:\n",
2015 vir_get_stage_name(c
),
2016 c
->program_id
, c
->variant_id
);
2018 fprintf(stderr
, "\n");
2021 /* Compute the live ranges so we can figure out interference. */
2022 vir_calculate_live_intervals(c
);
2024 /* Attempt to allocate registers for the temporaries. If we fail,
2025 * reduce thread count and try again.
2027 int min_threads
= (c
->devinfo
->ver
>= 41) ? 2 : 1;
2028 struct qpu_reg
*temp_registers
;
2030 temp_registers
= v3d_register_allocate(c
);
2035 if (c
->threads
== min_threads
) {
2036 fprintf(stderr
, "Failed to register allocate at %d threads:\n",
2045 if (c
->threads
== 1)
2046 vir_remove_thrsw(c
);
2049 v3d_vir_to_qpu(c
, temp_registers
);