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v3d: Implement noperspective varyings on V3D 4.x.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 static void
36 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
37
38 static void
39 resize_qreg_array(struct v3d_compile *c,
40 struct qreg **regs,
41 uint32_t *size,
42 uint32_t decl_size)
43 {
44 if (*size >= decl_size)
45 return;
46
47 uint32_t old_size = *size;
48 *size = MAX2(*size * 2, decl_size);
49 *regs = reralloc(c, *regs, struct qreg, *size);
50 if (!*regs) {
51 fprintf(stderr, "Malloc failure\n");
52 abort();
53 }
54
55 for (uint32_t i = old_size; i < *size; i++)
56 (*regs)[i] = c->undef;
57 }
58
59 void
60 vir_emit_thrsw(struct v3d_compile *c)
61 {
62 if (c->threads == 1)
63 return;
64
65 /* Always thread switch after each texture operation for now.
66 *
67 * We could do better by batching a bunch of texture fetches up and
68 * then doing one thread switch and collecting all their results
69 * afterward.
70 */
71 c->last_thrsw = vir_NOP(c);
72 c->last_thrsw->qpu.sig.thrsw = true;
73 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
74 }
75
76 static struct qreg
77 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
78 {
79 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
80 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
81 }
82
83 static struct qreg
84 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
85 {
86 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
87 uint32_t offset = nir_intrinsic_base(intr);
88 struct v3d_ubo_range *range = NULL;
89 unsigned i;
90
91 for (i = 0; i < c->num_ubo_ranges; i++) {
92 range = &c->ubo_ranges[i];
93 if (offset >= range->src_offset &&
94 offset < range->src_offset + range->size) {
95 break;
96 }
97 }
98 /* The driver-location-based offset always has to be within a declared
99 * uniform range.
100 */
101 assert(i != c->num_ubo_ranges);
102 if (!c->ubo_range_used[i]) {
103 c->ubo_range_used[i] = true;
104 range->dst_offset = c->next_ubo_dst_offset;
105 c->next_ubo_dst_offset += range->size;
106 }
107
108 offset -= range->src_offset;
109
110 if (range->dst_offset + offset != 0) {
111 indirect_offset = vir_ADD(c, indirect_offset,
112 vir_uniform_ui(c, range->dst_offset +
113 offset));
114 }
115
116 /* Adjust for where we stored the TGSI register base. */
117 vir_ADD_dest(c,
118 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
119 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
120 indirect_offset);
121
122 vir_emit_thrsw(c);
123 return vir_LDTMU(c);
124 }
125
126 static struct qreg *
127 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
128 {
129 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
130 def->num_components);
131 _mesa_hash_table_insert(c->def_ht, def, qregs);
132 return qregs;
133 }
134
135 /**
136 * This function is responsible for getting VIR results into the associated
137 * storage for a NIR instruction.
138 *
139 * If it's a NIR SSA def, then we just set the associated hash table entry to
140 * the new result.
141 *
142 * If it's a NIR reg, then we need to update the existing qreg assigned to the
143 * NIR destination with the incoming value. To do that without introducing
144 * new MOVs, we require that the incoming qreg either be a uniform, or be
145 * SSA-defined by the previous VIR instruction in the block and rewritable by
146 * this function. That lets us sneak ahead and insert the SF flag beforehand
147 * (knowing that the previous instruction doesn't depend on flags) and rewrite
148 * its destination to be the NIR reg's destination
149 */
150 void
151 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
152 struct qreg result)
153 {
154 struct qinst *last_inst = NULL;
155 if (!list_empty(&c->cur_block->instructions))
156 last_inst = (struct qinst *)c->cur_block->instructions.prev;
157
158 assert(result.file == QFILE_UNIF ||
159 (result.file == QFILE_TEMP &&
160 last_inst && last_inst == c->defs[result.index]));
161
162 if (dest->is_ssa) {
163 assert(chan < dest->ssa.num_components);
164
165 struct qreg *qregs;
166 struct hash_entry *entry =
167 _mesa_hash_table_search(c->def_ht, &dest->ssa);
168
169 if (entry)
170 qregs = entry->data;
171 else
172 qregs = ntq_init_ssa_def(c, &dest->ssa);
173
174 qregs[chan] = result;
175 } else {
176 nir_register *reg = dest->reg.reg;
177 assert(dest->reg.base_offset == 0);
178 assert(reg->num_array_elems == 0);
179 struct hash_entry *entry =
180 _mesa_hash_table_search(c->def_ht, reg);
181 struct qreg *qregs = entry->data;
182
183 /* Insert a MOV if the source wasn't an SSA def in the
184 * previous instruction.
185 */
186 if (result.file == QFILE_UNIF) {
187 result = vir_MOV(c, result);
188 last_inst = c->defs[result.index];
189 }
190
191 /* We know they're both temps, so just rewrite index. */
192 c->defs[last_inst->dst.index] = NULL;
193 last_inst->dst.index = qregs[chan].index;
194
195 /* If we're in control flow, then make this update of the reg
196 * conditional on the execution mask.
197 */
198 if (c->execute.file != QFILE_NULL) {
199 last_inst->dst.index = qregs[chan].index;
200
201 /* Set the flags to the current exec mask.
202 */
203 c->cursor = vir_before_inst(last_inst);
204 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
205 c->cursor = vir_after_inst(last_inst);
206
207 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
208 last_inst->cond_is_exec_mask = true;
209 }
210 }
211 }
212
213 struct qreg
214 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
215 {
216 struct hash_entry *entry;
217 if (src.is_ssa) {
218 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
219 assert(i < src.ssa->num_components);
220 } else {
221 nir_register *reg = src.reg.reg;
222 entry = _mesa_hash_table_search(c->def_ht, reg);
223 assert(reg->num_array_elems == 0);
224 assert(src.reg.base_offset == 0);
225 assert(i < reg->num_components);
226 }
227
228 struct qreg *qregs = entry->data;
229 return qregs[i];
230 }
231
232 static struct qreg
233 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
234 unsigned src)
235 {
236 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
237 unsigned chan = ffs(instr->dest.write_mask) - 1;
238 struct qreg r = ntq_get_src(c, instr->src[src].src,
239 instr->src[src].swizzle[chan]);
240
241 assert(!instr->src[src].abs);
242 assert(!instr->src[src].negate);
243
244 return r;
245 };
246
247 static inline struct qreg
248 vir_SAT(struct v3d_compile *c, struct qreg val)
249 {
250 return vir_FMAX(c,
251 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
252 vir_uniform_f(c, 0.0));
253 }
254
255 static struct qreg
256 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
257 {
258 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
259 }
260
261 static void
262 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
263 {
264 unsigned unit = instr->texture_index;
265 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
266 int dest_size = nir_tex_instr_dest_size(instr);
267
268 struct qreg lod = c->undef;
269 if (lod_index != -1)
270 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
271
272 for (int i = 0; i < dest_size; i++) {
273 assert(i < 3);
274 enum quniform_contents contents;
275
276 if (instr->is_array && i == dest_size - 1)
277 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
278 else
279 contents = QUNIFORM_TEXTURE_WIDTH + i;
280
281 struct qreg size = vir_uniform(c, contents, unit);
282
283 switch (instr->sampler_dim) {
284 case GLSL_SAMPLER_DIM_1D:
285 case GLSL_SAMPLER_DIM_2D:
286 case GLSL_SAMPLER_DIM_3D:
287 case GLSL_SAMPLER_DIM_CUBE:
288 /* Don't minify the array size. */
289 if (!(instr->is_array && i == dest_size - 1)) {
290 size = ntq_minify(c, size, lod);
291 }
292 break;
293
294 case GLSL_SAMPLER_DIM_RECT:
295 /* There's no LOD field for rects */
296 break;
297
298 default:
299 unreachable("Bad sampler type");
300 }
301
302 ntq_store_dest(c, &instr->dest, i, size);
303 }
304 }
305
306 static void
307 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
308 {
309 unsigned unit = instr->texture_index;
310
311 /* Since each texture sampling op requires uploading uniforms to
312 * reference the texture, there's no HW support for texture size and
313 * you just upload uniforms containing the size.
314 */
315 switch (instr->op) {
316 case nir_texop_query_levels:
317 ntq_store_dest(c, &instr->dest, 0,
318 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
319 return;
320 case nir_texop_txs:
321 ntq_emit_txs(c, instr);
322 return;
323 default:
324 break;
325 }
326
327 if (c->devinfo->ver >= 40)
328 v3d40_vir_emit_tex(c, instr);
329 else
330 v3d33_vir_emit_tex(c, instr);
331 }
332
333 static struct qreg
334 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
335 {
336 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
337 if (is_cos)
338 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
339
340 struct qreg periods = vir_FROUND(c, input);
341 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
342 vir_FSUB(c, input, periods));
343 return vir_XOR(c, sin_output, vir_SHL(c,
344 vir_FTOIN(c, periods),
345 vir_uniform_ui(c, -1)));
346 }
347
348 static struct qreg
349 ntq_fsign(struct v3d_compile *c, struct qreg src)
350 {
351 struct qreg t = vir_get_temp(c);
352
353 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
354 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
355 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
356 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
357 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
358 return vir_MOV(c, t);
359 }
360
361 static struct qreg
362 ntq_isign(struct v3d_compile *c, struct qreg src)
363 {
364 struct qreg t = vir_get_temp(c);
365
366 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
367 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
368 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
369 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
370 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
371 return vir_MOV(c, t);
372 }
373
374 static void
375 emit_fragcoord_input(struct v3d_compile *c, int attr)
376 {
377 c->inputs[attr * 4 + 0] = vir_FXCD(c);
378 c->inputs[attr * 4 + 1] = vir_FYCD(c);
379 c->inputs[attr * 4 + 2] = c->payload_z;
380 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
381 c->payload_w);
382 }
383
384 static struct qreg
385 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
386 uint8_t swizzle)
387 {
388 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
389 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
390
391 struct qreg vary;
392 if (c->devinfo->ver >= 41) {
393 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
394 c->undef, c->undef);
395 ldvary->qpu.sig.ldvary = true;
396 vary = vir_emit_def(c, ldvary);
397 } else {
398 vir_NOP(c)->qpu.sig.ldvary = true;
399 vary = r3;
400 }
401
402 /* For gl_PointCoord input or distance along a line, we'll be called
403 * with no nir_variable, and we don't count toward VPM size so we
404 * don't track an input slot.
405 */
406 if (!var) {
407 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
408 }
409
410 int i = c->num_inputs++;
411 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
412 swizzle);
413
414 switch (var->data.interpolation) {
415 case INTERP_MODE_NONE:
416 /* If a gl_FrontColor or gl_BackColor input has no interp
417 * qualifier, then if we're using glShadeModel(GL_FLAT) it
418 * needs to be flat shaded.
419 */
420 switch (var->data.location) {
421 case VARYING_SLOT_COL0:
422 case VARYING_SLOT_COL1:
423 case VARYING_SLOT_BFC0:
424 case VARYING_SLOT_BFC1:
425 if (c->fs_key->shade_model_flat) {
426 BITSET_SET(c->flat_shade_flags, i);
427 vir_MOV_dest(c, c->undef, vary);
428 return vir_MOV(c, r5);
429 } else {
430 return vir_FADD(c, vir_FMUL(c, vary,
431 c->payload_w), r5);
432 }
433 default:
434 break;
435 }
436 /* FALLTHROUGH */
437 case INTERP_MODE_SMOOTH:
438 if (var->data.centroid) {
439 BITSET_SET(c->centroid_flags, i);
440 return vir_FADD(c, vir_FMUL(c, vary,
441 c->payload_w_centroid), r5);
442 } else {
443 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
444 }
445 case INTERP_MODE_NOPERSPECTIVE:
446 BITSET_SET(c->noperspective_flags, i);
447 return vir_FADD(c, vir_MOV(c, vary), r5);
448 case INTERP_MODE_FLAT:
449 BITSET_SET(c->flat_shade_flags, i);
450 vir_MOV_dest(c, c->undef, vary);
451 return vir_MOV(c, r5);
452 default:
453 unreachable("Bad interp mode");
454 }
455 }
456
457 static void
458 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
459 {
460 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
461 int chan = var->data.location_frac + i;
462 c->inputs[attr * 4 + chan] =
463 emit_fragment_varying(c, var, chan);
464 }
465 }
466
467 static void
468 add_output(struct v3d_compile *c,
469 uint32_t decl_offset,
470 uint8_t slot,
471 uint8_t swizzle)
472 {
473 uint32_t old_array_size = c->outputs_array_size;
474 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
475 decl_offset + 1);
476
477 if (old_array_size != c->outputs_array_size) {
478 c->output_slots = reralloc(c,
479 c->output_slots,
480 struct v3d_varying_slot,
481 c->outputs_array_size);
482 }
483
484 c->output_slots[decl_offset] =
485 v3d_slot_from_slot_and_component(slot, swizzle);
486 }
487
488 static void
489 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
490 {
491 unsigned array_id = c->num_ubo_ranges++;
492 if (array_id >= c->ubo_ranges_array_size) {
493 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
494 array_id + 1);
495 c->ubo_ranges = reralloc(c, c->ubo_ranges,
496 struct v3d_ubo_range,
497 c->ubo_ranges_array_size);
498 c->ubo_range_used = reralloc(c, c->ubo_range_used,
499 bool,
500 c->ubo_ranges_array_size);
501 }
502
503 c->ubo_ranges[array_id].dst_offset = 0;
504 c->ubo_ranges[array_id].src_offset = start;
505 c->ubo_ranges[array_id].size = size;
506 c->ubo_range_used[array_id] = false;
507 }
508
509 /**
510 * If compare_instr is a valid comparison instruction, emits the
511 * compare_instr's comparison and returns the sel_instr's return value based
512 * on the compare_instr's result.
513 */
514 static bool
515 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
516 nir_alu_instr *compare_instr,
517 nir_alu_instr *sel_instr)
518 {
519 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
520 struct qreg src1;
521 if (nir_op_infos[compare_instr->op].num_inputs > 1)
522 src1 = ntq_get_alu_src(c, compare_instr, 1);
523 bool cond_invert = false;
524
525 switch (compare_instr->op) {
526 case nir_op_feq:
527 case nir_op_seq:
528 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
529 break;
530 case nir_op_ieq:
531 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
532 break;
533
534 case nir_op_fne:
535 case nir_op_sne:
536 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
537 cond_invert = true;
538 break;
539 case nir_op_ine:
540 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
541 cond_invert = true;
542 break;
543
544 case nir_op_fge:
545 case nir_op_sge:
546 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
547 break;
548 case nir_op_ige:
549 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
550 cond_invert = true;
551 break;
552 case nir_op_uge:
553 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
554 cond_invert = true;
555 break;
556
557 case nir_op_slt:
558 case nir_op_flt:
559 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
560 break;
561 case nir_op_ilt:
562 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
563 break;
564 case nir_op_ult:
565 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
566 break;
567
568 default:
569 return false;
570 }
571
572 enum v3d_qpu_cond cond = (cond_invert ?
573 V3D_QPU_COND_IFNA :
574 V3D_QPU_COND_IFA);
575
576 switch (sel_instr->op) {
577 case nir_op_seq:
578 case nir_op_sne:
579 case nir_op_sge:
580 case nir_op_slt:
581 *dest = vir_SEL(c, cond,
582 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
583 break;
584
585 case nir_op_bcsel:
586 *dest = vir_SEL(c, cond,
587 ntq_get_alu_src(c, sel_instr, 1),
588 ntq_get_alu_src(c, sel_instr, 2));
589 break;
590
591 default:
592 *dest = vir_SEL(c, cond,
593 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
594 break;
595 }
596
597 /* Make the temporary for nir_store_dest(). */
598 *dest = vir_MOV(c, *dest);
599
600 return true;
601 }
602
603 /**
604 * Attempts to fold a comparison generating a boolean result into the
605 * condition code for selecting between two values, instead of comparing the
606 * boolean result against 0 to generate the condition code.
607 */
608 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
609 struct qreg *src)
610 {
611 if (!instr->src[0].src.is_ssa)
612 goto out;
613 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
614 goto out;
615 nir_alu_instr *compare =
616 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
617 if (!compare)
618 goto out;
619
620 struct qreg dest;
621 if (ntq_emit_comparison(c, &dest, compare, instr))
622 return dest;
623
624 out:
625 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
626 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
627 }
628
629
630 static void
631 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
632 {
633 /* This should always be lowered to ALU operations for V3D. */
634 assert(!instr->dest.saturate);
635
636 /* Vectors are special in that they have non-scalarized writemasks,
637 * and just take the first swizzle channel for each argument in order
638 * into each writemask channel.
639 */
640 if (instr->op == nir_op_vec2 ||
641 instr->op == nir_op_vec3 ||
642 instr->op == nir_op_vec4) {
643 struct qreg srcs[4];
644 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
645 srcs[i] = ntq_get_src(c, instr->src[i].src,
646 instr->src[i].swizzle[0]);
647 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
648 ntq_store_dest(c, &instr->dest.dest, i,
649 vir_MOV(c, srcs[i]));
650 return;
651 }
652
653 /* General case: We can just grab the one used channel per src. */
654 struct qreg src[nir_op_infos[instr->op].num_inputs];
655 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
656 src[i] = ntq_get_alu_src(c, instr, i);
657 }
658
659 struct qreg result;
660
661 switch (instr->op) {
662 case nir_op_fmov:
663 case nir_op_imov:
664 result = vir_MOV(c, src[0]);
665 break;
666
667 case nir_op_fneg:
668 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
669 break;
670 case nir_op_ineg:
671 result = vir_NEG(c, src[0]);
672 break;
673
674 case nir_op_fmul:
675 result = vir_FMUL(c, src[0], src[1]);
676 break;
677 case nir_op_fadd:
678 result = vir_FADD(c, src[0], src[1]);
679 break;
680 case nir_op_fsub:
681 result = vir_FSUB(c, src[0], src[1]);
682 break;
683 case nir_op_fmin:
684 result = vir_FMIN(c, src[0], src[1]);
685 break;
686 case nir_op_fmax:
687 result = vir_FMAX(c, src[0], src[1]);
688 break;
689
690 case nir_op_f2i32:
691 result = vir_FTOIZ(c, src[0]);
692 break;
693 case nir_op_f2u32:
694 result = vir_FTOUZ(c, src[0]);
695 break;
696 case nir_op_i2f32:
697 result = vir_ITOF(c, src[0]);
698 break;
699 case nir_op_u2f32:
700 result = vir_UTOF(c, src[0]);
701 break;
702 case nir_op_b2f:
703 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
704 break;
705 case nir_op_b2i:
706 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
707 break;
708 case nir_op_i2b:
709 case nir_op_f2b:
710 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
711 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
712 vir_uniform_ui(c, ~0),
713 vir_uniform_ui(c, 0)));
714 break;
715
716 case nir_op_iadd:
717 result = vir_ADD(c, src[0], src[1]);
718 break;
719 case nir_op_ushr:
720 result = vir_SHR(c, src[0], src[1]);
721 break;
722 case nir_op_isub:
723 result = vir_SUB(c, src[0], src[1]);
724 break;
725 case nir_op_ishr:
726 result = vir_ASR(c, src[0], src[1]);
727 break;
728 case nir_op_ishl:
729 result = vir_SHL(c, src[0], src[1]);
730 break;
731 case nir_op_imin:
732 result = vir_MIN(c, src[0], src[1]);
733 break;
734 case nir_op_umin:
735 result = vir_UMIN(c, src[0], src[1]);
736 break;
737 case nir_op_imax:
738 result = vir_MAX(c, src[0], src[1]);
739 break;
740 case nir_op_umax:
741 result = vir_UMAX(c, src[0], src[1]);
742 break;
743 case nir_op_iand:
744 result = vir_AND(c, src[0], src[1]);
745 break;
746 case nir_op_ior:
747 result = vir_OR(c, src[0], src[1]);
748 break;
749 case nir_op_ixor:
750 result = vir_XOR(c, src[0], src[1]);
751 break;
752 case nir_op_inot:
753 result = vir_NOT(c, src[0]);
754 break;
755
756 case nir_op_ufind_msb:
757 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
758 break;
759
760 case nir_op_imul:
761 result = vir_UMUL(c, src[0], src[1]);
762 break;
763
764 case nir_op_seq:
765 case nir_op_sne:
766 case nir_op_sge:
767 case nir_op_slt:
768 case nir_op_feq:
769 case nir_op_fne:
770 case nir_op_fge:
771 case nir_op_flt:
772 case nir_op_ieq:
773 case nir_op_ine:
774 case nir_op_ige:
775 case nir_op_uge:
776 case nir_op_ilt:
777 case nir_op_ult:
778 if (!ntq_emit_comparison(c, &result, instr, instr)) {
779 fprintf(stderr, "Bad comparison instruction\n");
780 }
781 break;
782
783 case nir_op_bcsel:
784 result = ntq_emit_bcsel(c, instr, src);
785 break;
786 case nir_op_fcsel:
787 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
788 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
789 src[1], src[2]));
790 break;
791
792 case nir_op_frcp:
793 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
794 break;
795 case nir_op_frsq:
796 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
797 break;
798 case nir_op_fexp2:
799 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
800 break;
801 case nir_op_flog2:
802 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
803 break;
804
805 case nir_op_fceil:
806 result = vir_FCEIL(c, src[0]);
807 break;
808 case nir_op_ffloor:
809 result = vir_FFLOOR(c, src[0]);
810 break;
811 case nir_op_fround_even:
812 result = vir_FROUND(c, src[0]);
813 break;
814 case nir_op_ftrunc:
815 result = vir_FTRUNC(c, src[0]);
816 break;
817 case nir_op_ffract:
818 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
819 break;
820
821 case nir_op_fsin:
822 result = ntq_fsincos(c, src[0], false);
823 break;
824 case nir_op_fcos:
825 result = ntq_fsincos(c, src[0], true);
826 break;
827
828 case nir_op_fsign:
829 result = ntq_fsign(c, src[0]);
830 break;
831 case nir_op_isign:
832 result = ntq_isign(c, src[0]);
833 break;
834
835 case nir_op_fabs: {
836 result = vir_FMOV(c, src[0]);
837 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
838 break;
839 }
840
841 case nir_op_iabs:
842 result = vir_MAX(c, src[0],
843 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
844 break;
845
846 case nir_op_fddx:
847 case nir_op_fddx_coarse:
848 case nir_op_fddx_fine:
849 result = vir_FDX(c, src[0]);
850 break;
851
852 case nir_op_fddy:
853 case nir_op_fddy_coarse:
854 case nir_op_fddy_fine:
855 result = vir_FDY(c, src[0]);
856 break;
857
858 case nir_op_uadd_carry:
859 vir_PF(c, vir_ADD(c, src[0], src[1]), V3D_QPU_PF_PUSHC);
860 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
861 vir_uniform_ui(c, ~0),
862 vir_uniform_ui(c, 0)));
863 break;
864
865 default:
866 fprintf(stderr, "unknown NIR ALU inst: ");
867 nir_print_instr(&instr->instr, stderr);
868 fprintf(stderr, "\n");
869 abort();
870 }
871
872 /* We have a scalar result, so the instruction should only have a
873 * single channel written to.
874 */
875 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
876 ntq_store_dest(c, &instr->dest.dest,
877 ffs(instr->dest.write_mask) - 1, result);
878 }
879
880 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
881 * specifier. They come from a register that's preloaded with 0xffffffff
882 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
883 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
884 */
885 #define TLB_TYPE_F16_COLOR (3 << 6)
886 #define TLB_TYPE_I32_COLOR (1 << 6)
887 #define TLB_TYPE_F32_COLOR (0 << 6)
888 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
889 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
890 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
891 #define TLB_F16_SWAP_HI_LO (1 << 1)
892 #define TLB_VEC_SIZE_4_F16 (1 << 0)
893 #define TLB_VEC_SIZE_2_F16 (0 << 0)
894 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
895
896 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
897 * flag is set.
898 */
899 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
900 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
901 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
902
903 /* Stencil is a single 32-bit write. */
904 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
905
906 static void
907 emit_frag_end(struct v3d_compile *c)
908 {
909 /* XXX
910 if (c->output_sample_mask_index != -1) {
911 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
912 }
913 */
914
915 bool has_any_tlb_color_write = false;
916 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
917 if (c->output_color_var[rt])
918 has_any_tlb_color_write = true;
919 }
920
921 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
922 struct nir_variable *var = c->output_color_var[0];
923 struct qreg *color = &c->outputs[var->data.driver_location * 4];
924
925 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
926 vir_AND(c,
927 vir_MSF(c),
928 vir_FTOC(c, color[3])));
929 }
930
931 if (c->output_position_index != -1) {
932 struct qinst *inst = vir_MOV_dest(c,
933 vir_reg(QFILE_TLBU, 0),
934 c->outputs[c->output_position_index]);
935
936 inst->src[vir_get_implicit_uniform_src(inst)] =
937 vir_uniform_ui(c,
938 TLB_TYPE_DEPTH |
939 TLB_DEPTH_TYPE_PER_PIXEL |
940 0xffffff00);
941 } else if (c->s->info.fs.uses_discard ||
942 c->fs_key->sample_alpha_to_coverage ||
943 !has_any_tlb_color_write) {
944 /* Emit passthrough Z if it needed to be delayed until shader
945 * end due to potential discards.
946 *
947 * Since (single-threaded) fragment shaders always need a TLB
948 * write, emit passthrouh Z if we didn't have any color
949 * buffers and flag us as potentially discarding, so that we
950 * can use Z as the TLB write.
951 */
952 c->s->info.fs.uses_discard = true;
953
954 struct qinst *inst = vir_MOV_dest(c,
955 vir_reg(QFILE_TLBU, 0),
956 vir_reg(QFILE_NULL, 0));
957
958 inst->src[vir_get_implicit_uniform_src(inst)] =
959 vir_uniform_ui(c,
960 TLB_TYPE_DEPTH |
961 TLB_DEPTH_TYPE_INVARIANT |
962 0xffffff00);
963 }
964
965 /* XXX: Performance improvement: Merge Z write and color writes TLB
966 * uniform setup
967 */
968
969 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
970 if (!c->output_color_var[rt])
971 continue;
972
973 nir_variable *var = c->output_color_var[rt];
974 struct qreg *color = &c->outputs[var->data.driver_location * 4];
975 int num_components = glsl_get_vector_elements(var->type);
976 uint32_t conf = 0xffffff00;
977 struct qinst *inst;
978
979 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
980 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
981
982 if (c->fs_key->swap_color_rb & (1 << rt))
983 num_components = MAX2(num_components, 3);
984
985 assert(num_components != 0);
986 switch (glsl_get_base_type(var->type)) {
987 case GLSL_TYPE_UINT:
988 case GLSL_TYPE_INT:
989 /* The F32 vs I32 distinction was dropped in 4.2. */
990 if (c->devinfo->ver < 42)
991 conf |= TLB_TYPE_I32_COLOR;
992 else
993 conf |= TLB_TYPE_F32_COLOR;
994 conf |= ((num_components - 1) <<
995 TLB_VEC_SIZE_MINUS_1_SHIFT);
996
997 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
998 inst->src[vir_get_implicit_uniform_src(inst)] =
999 vir_uniform_ui(c, conf);
1000
1001 for (int i = 1; i < num_components; i++) {
1002 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1003 color[i]);
1004 }
1005 break;
1006
1007 default: {
1008 struct qreg r = color[0];
1009 struct qreg g = color[1];
1010 struct qreg b = color[2];
1011 struct qreg a = color[3];
1012
1013 if (c->fs_key->f32_color_rb & (1 << rt)) {
1014 conf |= TLB_TYPE_F32_COLOR;
1015 conf |= ((num_components - 1) <<
1016 TLB_VEC_SIZE_MINUS_1_SHIFT);
1017 } else {
1018 conf |= TLB_TYPE_F16_COLOR;
1019 conf |= TLB_F16_SWAP_HI_LO;
1020 if (num_components >= 3)
1021 conf |= TLB_VEC_SIZE_4_F16;
1022 else
1023 conf |= TLB_VEC_SIZE_2_F16;
1024 }
1025
1026 if (c->fs_key->swap_color_rb & (1 << rt)) {
1027 r = color[2];
1028 b = color[0];
1029 }
1030
1031 if (c->fs_key->sample_alpha_to_one)
1032 a = vir_uniform_f(c, 1.0);
1033
1034 if (c->fs_key->f32_color_rb & (1 << rt)) {
1035 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1036 inst->src[vir_get_implicit_uniform_src(inst)] =
1037 vir_uniform_ui(c, conf);
1038
1039 if (num_components >= 2)
1040 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1041 if (num_components >= 3)
1042 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1043 if (num_components >= 4)
1044 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1045 } else {
1046 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1047 if (conf != ~0) {
1048 inst->dst.file = QFILE_TLBU;
1049 inst->src[vir_get_implicit_uniform_src(inst)] =
1050 vir_uniform_ui(c, conf);
1051 }
1052
1053 if (num_components >= 3)
1054 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1055 }
1056 break;
1057 }
1058 }
1059 }
1060 }
1061
1062 static void
1063 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1064 {
1065 if (c->devinfo->ver >= 40) {
1066 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1067 *vpm_index = *vpm_index + 1;
1068 } else {
1069 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1070 }
1071
1072 c->num_vpm_writes++;
1073 }
1074
1075 static void
1076 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1077 uint32_t *vpm_index)
1078 {
1079 for (int i = 0; i < 2; i++) {
1080 struct qreg coord = c->outputs[c->output_position_index + i];
1081 coord = vir_FMUL(c, coord,
1082 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1083 0));
1084 coord = vir_FMUL(c, coord, rcp_w);
1085 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1086 }
1087
1088 }
1089
1090 static void
1091 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1092 {
1093 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1094 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1095
1096 struct qreg z = c->outputs[c->output_position_index + 2];
1097 z = vir_FMUL(c, z, zscale);
1098 z = vir_FMUL(c, z, rcp_w);
1099 z = vir_FADD(c, z, zoffset);
1100 vir_VPM_WRITE(c, z, vpm_index);
1101 }
1102
1103 static void
1104 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1105 {
1106 vir_VPM_WRITE(c, rcp_w, vpm_index);
1107 }
1108
1109 static void
1110 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1111 {
1112 struct qreg point_size;
1113
1114 if (c->output_point_size_index != -1)
1115 point_size = c->outputs[c->output_point_size_index];
1116 else
1117 point_size = vir_uniform_f(c, 1.0);
1118
1119 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1120 * BCM21553).
1121 */
1122 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1123
1124 vir_VPM_WRITE(c, point_size, vpm_index);
1125 }
1126
1127 static void
1128 emit_vpm_write_setup(struct v3d_compile *c)
1129 {
1130 if (c->devinfo->ver >= 40)
1131 return;
1132
1133 v3d33_vir_vpm_write_setup(c);
1134 }
1135
1136 /**
1137 * Sets up c->outputs[c->output_position_index] for the vertex shader
1138 * epilogue, if an output vertex position wasn't specified in the user's
1139 * shader. This may be the case for transform feedback with rasterizer
1140 * discard enabled.
1141 */
1142 static void
1143 setup_default_position(struct v3d_compile *c)
1144 {
1145 if (c->output_position_index != -1)
1146 return;
1147
1148 c->output_position_index = c->outputs_array_size;
1149 for (int i = 0; i < 4; i++) {
1150 add_output(c,
1151 c->output_position_index + i,
1152 VARYING_SLOT_POS, i);
1153 }
1154 }
1155
1156 static void
1157 emit_vert_end(struct v3d_compile *c)
1158 {
1159 setup_default_position(c);
1160
1161 uint32_t vpm_index = 0;
1162 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1163 c->outputs[c->output_position_index + 3]);
1164
1165 emit_vpm_write_setup(c);
1166
1167 if (c->vs_key->is_coord) {
1168 for (int i = 0; i < 4; i++)
1169 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1170 &vpm_index);
1171 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1172 if (c->vs_key->per_vertex_point_size) {
1173 emit_point_size_write(c, &vpm_index);
1174 /* emit_rcp_wc_write(c, rcp_w); */
1175 }
1176 /* XXX: Z-only rendering */
1177 if (0)
1178 emit_zs_write(c, rcp_w, &vpm_index);
1179 } else {
1180 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1181 emit_zs_write(c, rcp_w, &vpm_index);
1182 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1183 if (c->vs_key->per_vertex_point_size)
1184 emit_point_size_write(c, &vpm_index);
1185 }
1186
1187 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1188 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1189 int j;
1190
1191 for (j = 0; j < c->num_outputs; j++) {
1192 struct v3d_varying_slot output = c->output_slots[j];
1193
1194 if (!memcmp(&input, &output, sizeof(input))) {
1195 vir_VPM_WRITE(c, c->outputs[j],
1196 &vpm_index);
1197 break;
1198 }
1199 }
1200 /* Emit padding if we didn't find a declared VS output for
1201 * this FS input.
1202 */
1203 if (j == c->num_outputs)
1204 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1205 &vpm_index);
1206 }
1207
1208 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1209 */
1210 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1211 vir_VPMWT(c);
1212 }
1213
1214 void
1215 v3d_optimize_nir(struct nir_shader *s)
1216 {
1217 bool progress;
1218
1219 do {
1220 progress = false;
1221
1222 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1223 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1224 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1225 NIR_PASS(progress, s, nir_copy_prop);
1226 NIR_PASS(progress, s, nir_opt_remove_phis);
1227 NIR_PASS(progress, s, nir_opt_dce);
1228 NIR_PASS(progress, s, nir_opt_dead_cf);
1229 NIR_PASS(progress, s, nir_opt_cse);
1230 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1231 NIR_PASS(progress, s, nir_opt_algebraic);
1232 NIR_PASS(progress, s, nir_opt_constant_folding);
1233 NIR_PASS(progress, s, nir_opt_undef);
1234 } while (progress);
1235
1236 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1237 }
1238
1239 static int
1240 driver_location_compare(const void *in_a, const void *in_b)
1241 {
1242 const nir_variable *const *a = in_a;
1243 const nir_variable *const *b = in_b;
1244
1245 return (*a)->data.driver_location - (*b)->data.driver_location;
1246 }
1247
1248 static struct qreg
1249 ntq_emit_vpm_read(struct v3d_compile *c,
1250 uint32_t *num_components_queued,
1251 uint32_t *remaining,
1252 uint32_t vpm_index)
1253 {
1254 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1255
1256 if (c->devinfo->ver >= 40 ) {
1257 return vir_LDVPMV_IN(c,
1258 vir_uniform_ui(c,
1259 (*num_components_queued)++));
1260 }
1261
1262 if (*num_components_queued != 0) {
1263 (*num_components_queued)--;
1264 c->num_inputs++;
1265 return vir_MOV(c, vpm);
1266 }
1267
1268 uint32_t num_components = MIN2(*remaining, 32);
1269
1270 v3d33_vir_vpm_read_setup(c, num_components);
1271
1272 *num_components_queued = num_components - 1;
1273 *remaining -= num_components;
1274 c->num_inputs++;
1275
1276 return vir_MOV(c, vpm);
1277 }
1278
1279 static void
1280 ntq_setup_inputs(struct v3d_compile *c)
1281 {
1282 unsigned num_entries = 0;
1283 unsigned num_components = 0;
1284 nir_foreach_variable(var, &c->s->inputs) {
1285 num_entries++;
1286 num_components += glsl_get_components(var->type);
1287 }
1288
1289 nir_variable *vars[num_entries];
1290
1291 unsigned i = 0;
1292 nir_foreach_variable(var, &c->s->inputs)
1293 vars[i++] = var;
1294
1295 /* Sort the variables so that we emit the input setup in
1296 * driver_location order. This is required for VPM reads, whose data
1297 * is fetched into the VPM in driver_location (TGSI register index)
1298 * order.
1299 */
1300 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1301
1302 uint32_t vpm_components_queued = 0;
1303 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1304 bool uses_iid = c->s->info.system_values_read &
1305 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1306 bool uses_vid = c->s->info.system_values_read &
1307 (1ull << SYSTEM_VALUE_VERTEX_ID);
1308
1309 num_components += uses_iid;
1310 num_components += uses_vid;
1311
1312 if (uses_iid) {
1313 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1314 &num_components, ~0);
1315 }
1316
1317 if (uses_vid) {
1318 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1319 &num_components, ~0);
1320 }
1321 }
1322
1323 for (unsigned i = 0; i < num_entries; i++) {
1324 nir_variable *var = vars[i];
1325 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1326 unsigned loc = var->data.driver_location;
1327
1328 assert(array_len == 1);
1329 (void)array_len;
1330 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1331 (loc + 1) * 4);
1332
1333 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1334 if (var->data.location == VARYING_SLOT_POS) {
1335 emit_fragcoord_input(c, loc);
1336 } else if (var->data.location == VARYING_SLOT_PNTC ||
1337 (var->data.location >= VARYING_SLOT_VAR0 &&
1338 (c->fs_key->point_sprite_mask &
1339 (1 << (var->data.location -
1340 VARYING_SLOT_VAR0))))) {
1341 c->inputs[loc * 4 + 0] = c->point_x;
1342 c->inputs[loc * 4 + 1] = c->point_y;
1343 } else {
1344 emit_fragment_input(c, loc, var);
1345 }
1346 } else {
1347 int var_components = glsl_get_components(var->type);
1348
1349 for (int i = 0; i < var_components; i++) {
1350 c->inputs[loc * 4 + i] =
1351 ntq_emit_vpm_read(c,
1352 &vpm_components_queued,
1353 &num_components,
1354 loc * 4 + i);
1355
1356 }
1357 c->vattr_sizes[loc] = var_components;
1358 }
1359 }
1360
1361 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1362 if (c->devinfo->ver >= 40) {
1363 assert(vpm_components_queued == num_components);
1364 } else {
1365 assert(vpm_components_queued == 0);
1366 assert(num_components == 0);
1367 }
1368 }
1369 }
1370
1371 static void
1372 ntq_setup_outputs(struct v3d_compile *c)
1373 {
1374 nir_foreach_variable(var, &c->s->outputs) {
1375 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1376 unsigned loc = var->data.driver_location * 4;
1377
1378 assert(array_len == 1);
1379 (void)array_len;
1380
1381 for (int i = 0; i < 4; i++) {
1382 add_output(c, loc + var->data.location_frac + i,
1383 var->data.location,
1384 var->data.location_frac + i);
1385 }
1386
1387 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1388 switch (var->data.location) {
1389 case FRAG_RESULT_COLOR:
1390 c->output_color_var[0] = var;
1391 c->output_color_var[1] = var;
1392 c->output_color_var[2] = var;
1393 c->output_color_var[3] = var;
1394 break;
1395 case FRAG_RESULT_DATA0:
1396 case FRAG_RESULT_DATA1:
1397 case FRAG_RESULT_DATA2:
1398 case FRAG_RESULT_DATA3:
1399 c->output_color_var[var->data.location -
1400 FRAG_RESULT_DATA0] = var;
1401 break;
1402 case FRAG_RESULT_DEPTH:
1403 c->output_position_index = loc;
1404 break;
1405 case FRAG_RESULT_SAMPLE_MASK:
1406 c->output_sample_mask_index = loc;
1407 break;
1408 }
1409 } else {
1410 switch (var->data.location) {
1411 case VARYING_SLOT_POS:
1412 c->output_position_index = loc;
1413 break;
1414 case VARYING_SLOT_PSIZ:
1415 c->output_point_size_index = loc;
1416 break;
1417 }
1418 }
1419 }
1420 }
1421
1422 static void
1423 ntq_setup_uniforms(struct v3d_compile *c)
1424 {
1425 nir_foreach_variable(var, &c->s->uniforms) {
1426 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1427 false);
1428 unsigned vec4_size = 4 * sizeof(float);
1429
1430 declare_uniform_range(c, var->data.driver_location * vec4_size,
1431 vec4_count * vec4_size);
1432
1433 }
1434 }
1435
1436 /**
1437 * Sets up the mapping from nir_register to struct qreg *.
1438 *
1439 * Each nir_register gets a struct qreg per 32-bit component being stored.
1440 */
1441 static void
1442 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1443 {
1444 foreach_list_typed(nir_register, nir_reg, node, list) {
1445 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1446 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1447 array_len *
1448 nir_reg->num_components);
1449
1450 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1451
1452 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1453 qregs[i] = vir_get_temp(c);
1454 }
1455 }
1456
1457 static void
1458 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1459 {
1460 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1461 for (int i = 0; i < instr->def.num_components; i++)
1462 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1463
1464 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1465 }
1466
1467 static void
1468 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1469 {
1470 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1471
1472 /* VIR needs there to be *some* value, so pick 0 (same as for
1473 * ntq_setup_registers().
1474 */
1475 for (int i = 0; i < instr->def.num_components; i++)
1476 qregs[i] = vir_uniform_ui(c, 0);
1477 }
1478
1479 static void
1480 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1481 {
1482 nir_const_value *const_offset;
1483 unsigned offset;
1484
1485 switch (instr->intrinsic) {
1486 case nir_intrinsic_load_uniform:
1487 assert(instr->num_components == 1);
1488 const_offset = nir_src_as_const_value(instr->src[0]);
1489 if (const_offset) {
1490 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1491 assert(offset % 4 == 0);
1492 /* We need dwords */
1493 offset = offset / 4;
1494 ntq_store_dest(c, &instr->dest, 0,
1495 vir_uniform(c, QUNIFORM_UNIFORM,
1496 offset));
1497 } else {
1498 ntq_store_dest(c, &instr->dest, 0,
1499 indirect_uniform_load(c, instr));
1500 }
1501 break;
1502
1503 case nir_intrinsic_load_ubo:
1504 for (int i = 0; i < instr->num_components; i++) {
1505 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1506
1507 /* Adjust for where we stored the TGSI register base. */
1508 vir_ADD_dest(c,
1509 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1510 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1511 vir_ADD(c,
1512 ntq_get_src(c, instr->src[1], 0),
1513 vir_uniform_ui(c, i * 4)));
1514
1515 vir_emit_thrsw(c);
1516
1517 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1518 }
1519 break;
1520
1521 const_offset = nir_src_as_const_value(instr->src[0]);
1522 if (const_offset) {
1523 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1524 assert(offset % 4 == 0);
1525 /* We need dwords */
1526 offset = offset / 4;
1527 ntq_store_dest(c, &instr->dest, 0,
1528 vir_uniform(c, QUNIFORM_UNIFORM,
1529 offset));
1530 } else {
1531 ntq_store_dest(c, &instr->dest, 0,
1532 indirect_uniform_load(c, instr));
1533 }
1534 break;
1535
1536 case nir_intrinsic_load_user_clip_plane:
1537 for (int i = 0; i < instr->num_components; i++) {
1538 ntq_store_dest(c, &instr->dest, i,
1539 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1540 nir_intrinsic_ucp_id(instr) *
1541 4 + i));
1542 }
1543 break;
1544
1545 case nir_intrinsic_load_alpha_ref_float:
1546 ntq_store_dest(c, &instr->dest, 0,
1547 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1548 break;
1549
1550 case nir_intrinsic_load_sample_mask_in:
1551 ntq_store_dest(c, &instr->dest, 0,
1552 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1553 break;
1554
1555 case nir_intrinsic_load_front_face:
1556 /* The register contains 0 (front) or 1 (back), and we need to
1557 * turn it into a NIR bool where true means front.
1558 */
1559 ntq_store_dest(c, &instr->dest, 0,
1560 vir_ADD(c,
1561 vir_uniform_ui(c, -1),
1562 vir_REVF(c)));
1563 break;
1564
1565 case nir_intrinsic_load_instance_id:
1566 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1567 break;
1568
1569 case nir_intrinsic_load_vertex_id:
1570 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1571 break;
1572
1573 case nir_intrinsic_load_input:
1574 const_offset = nir_src_as_const_value(instr->src[0]);
1575 assert(const_offset && "v3d doesn't support indirect inputs");
1576 for (int i = 0; i < instr->num_components; i++) {
1577 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1578 int comp = nir_intrinsic_component(instr) + i;
1579 ntq_store_dest(c, &instr->dest, i,
1580 vir_MOV(c, c->inputs[offset * 4 + comp]));
1581 }
1582 break;
1583
1584 case nir_intrinsic_store_output:
1585 const_offset = nir_src_as_const_value(instr->src[1]);
1586 assert(const_offset && "v3d doesn't support indirect outputs");
1587 offset = ((nir_intrinsic_base(instr) +
1588 const_offset->u32[0]) * 4 +
1589 nir_intrinsic_component(instr));
1590
1591 for (int i = 0; i < instr->num_components; i++) {
1592 c->outputs[offset + i] =
1593 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1594 }
1595 c->num_outputs = MAX2(c->num_outputs,
1596 offset + instr->num_components);
1597 break;
1598
1599 case nir_intrinsic_discard:
1600 if (c->execute.file != QFILE_NULL) {
1601 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1602 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1603 vir_uniform_ui(c, 0)),
1604 V3D_QPU_COND_IFA);
1605 } else {
1606 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1607 vir_uniform_ui(c, 0));
1608 }
1609 break;
1610
1611 case nir_intrinsic_discard_if: {
1612 /* true (~0) if we're discarding */
1613 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1614
1615 if (c->execute.file != QFILE_NULL) {
1616 /* execute == 0 means the channel is active. Invert
1617 * the condition so that we can use zero as "executing
1618 * and discarding."
1619 */
1620 vir_PF(c, vir_OR(c, c->execute, vir_NOT(c, cond)),
1621 V3D_QPU_PF_PUSHZ);
1622 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1623 vir_uniform_ui(c, 0)),
1624 V3D_QPU_COND_IFA);
1625 } else {
1626 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1627 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1628 vir_uniform_ui(c, 0)),
1629 V3D_QPU_COND_IFNA);
1630 }
1631
1632 break;
1633 }
1634
1635 default:
1636 fprintf(stderr, "Unknown intrinsic: ");
1637 nir_print_instr(&instr->instr, stderr);
1638 fprintf(stderr, "\n");
1639 break;
1640 }
1641 }
1642
1643 /* Clears (activates) the execute flags for any channels whose jump target
1644 * matches this block.
1645 */
1646 static void
1647 ntq_activate_execute_for_block(struct v3d_compile *c)
1648 {
1649 vir_PF(c, vir_XOR(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1650 V3D_QPU_PF_PUSHZ);
1651
1652 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1653 }
1654
1655 static void
1656 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1657 {
1658 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1659 bool empty_else_block =
1660 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1661 exec_list_is_empty(&nir_else_block->instr_list));
1662
1663 struct qblock *then_block = vir_new_block(c);
1664 struct qblock *after_block = vir_new_block(c);
1665 struct qblock *else_block;
1666 if (empty_else_block)
1667 else_block = after_block;
1668 else
1669 else_block = vir_new_block(c);
1670
1671 bool was_top_level = false;
1672 if (c->execute.file == QFILE_NULL) {
1673 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1674 was_top_level = true;
1675 }
1676
1677 /* Set A for executing (execute == 0) and jumping (if->condition ==
1678 * 0) channels, and then update execute flags for those to point to
1679 * the ELSE block.
1680 */
1681 vir_PF(c, vir_OR(c,
1682 c->execute,
1683 ntq_get_src(c, if_stmt->condition, 0)),
1684 V3D_QPU_PF_PUSHZ);
1685 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1686 c->execute,
1687 vir_uniform_ui(c, else_block->index));
1688
1689 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1690 * through.
1691 */
1692 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1693 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1694 vir_link_blocks(c->cur_block, else_block);
1695 vir_link_blocks(c->cur_block, then_block);
1696
1697 /* Process the THEN block. */
1698 vir_set_emit_block(c, then_block);
1699 ntq_emit_cf_list(c, &if_stmt->then_list);
1700
1701 if (!empty_else_block) {
1702 /* Handle the end of the THEN block. First, all currently
1703 * active channels update their execute flags to point to
1704 * ENDIF
1705 */
1706 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1707 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1708 vir_uniform_ui(c, after_block->index));
1709
1710 /* If everything points at ENDIF, then jump there immediately. */
1711 vir_PF(c, vir_XOR(c, c->execute,
1712 vir_uniform_ui(c, after_block->index)),
1713 V3D_QPU_PF_PUSHZ);
1714 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1715 vir_link_blocks(c->cur_block, after_block);
1716 vir_link_blocks(c->cur_block, else_block);
1717
1718 vir_set_emit_block(c, else_block);
1719 ntq_activate_execute_for_block(c);
1720 ntq_emit_cf_list(c, &if_stmt->else_list);
1721 }
1722
1723 vir_link_blocks(c->cur_block, after_block);
1724
1725 vir_set_emit_block(c, after_block);
1726 if (was_top_level)
1727 c->execute = c->undef;
1728 else
1729 ntq_activate_execute_for_block(c);
1730 }
1731
1732 static void
1733 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1734 {
1735 switch (jump->type) {
1736 case nir_jump_break:
1737 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1738 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1739 vir_uniform_ui(c, c->loop_break_block->index));
1740 break;
1741
1742 case nir_jump_continue:
1743 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1744 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1745 vir_uniform_ui(c, c->loop_cont_block->index));
1746 break;
1747
1748 case nir_jump_return:
1749 unreachable("All returns shouold be lowered\n");
1750 }
1751 }
1752
1753 static void
1754 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1755 {
1756 switch (instr->type) {
1757 case nir_instr_type_alu:
1758 ntq_emit_alu(c, nir_instr_as_alu(instr));
1759 break;
1760
1761 case nir_instr_type_intrinsic:
1762 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1763 break;
1764
1765 case nir_instr_type_load_const:
1766 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1767 break;
1768
1769 case nir_instr_type_ssa_undef:
1770 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1771 break;
1772
1773 case nir_instr_type_tex:
1774 ntq_emit_tex(c, nir_instr_as_tex(instr));
1775 break;
1776
1777 case nir_instr_type_jump:
1778 ntq_emit_jump(c, nir_instr_as_jump(instr));
1779 break;
1780
1781 default:
1782 fprintf(stderr, "Unknown NIR instr type: ");
1783 nir_print_instr(instr, stderr);
1784 fprintf(stderr, "\n");
1785 abort();
1786 }
1787 }
1788
1789 static void
1790 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1791 {
1792 nir_foreach_instr(instr, block) {
1793 ntq_emit_instr(c, instr);
1794 }
1795 }
1796
1797 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1798
1799 static void
1800 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1801 {
1802 bool was_top_level = false;
1803 if (c->execute.file == QFILE_NULL) {
1804 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1805 was_top_level = true;
1806 }
1807
1808 struct qblock *save_loop_cont_block = c->loop_cont_block;
1809 struct qblock *save_loop_break_block = c->loop_break_block;
1810
1811 c->loop_cont_block = vir_new_block(c);
1812 c->loop_break_block = vir_new_block(c);
1813
1814 vir_link_blocks(c->cur_block, c->loop_cont_block);
1815 vir_set_emit_block(c, c->loop_cont_block);
1816 ntq_activate_execute_for_block(c);
1817
1818 ntq_emit_cf_list(c, &loop->body);
1819
1820 /* Re-enable any previous continues now, so our ANYA check below
1821 * works.
1822 *
1823 * XXX: Use the .ORZ flags update, instead.
1824 */
1825 vir_PF(c, vir_XOR(c,
1826 c->execute,
1827 vir_uniform_ui(c, c->loop_cont_block->index)),
1828 V3D_QPU_PF_PUSHZ);
1829 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1830
1831 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1832
1833 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1834 /* Pixels that were not dispatched or have been discarded should not
1835 * contribute to looping again.
1836 */
1837 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
1838 vir_link_blocks(c->cur_block, c->loop_cont_block);
1839 vir_link_blocks(c->cur_block, c->loop_break_block);
1840
1841 vir_set_emit_block(c, c->loop_break_block);
1842 if (was_top_level)
1843 c->execute = c->undef;
1844 else
1845 ntq_activate_execute_for_block(c);
1846
1847 c->loop_break_block = save_loop_break_block;
1848 c->loop_cont_block = save_loop_cont_block;
1849 }
1850
1851 static void
1852 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1853 {
1854 fprintf(stderr, "FUNCTIONS not handled.\n");
1855 abort();
1856 }
1857
1858 static void
1859 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1860 {
1861 foreach_list_typed(nir_cf_node, node, node, list) {
1862 switch (node->type) {
1863 case nir_cf_node_block:
1864 ntq_emit_block(c, nir_cf_node_as_block(node));
1865 break;
1866
1867 case nir_cf_node_if:
1868 ntq_emit_if(c, nir_cf_node_as_if(node));
1869 break;
1870
1871 case nir_cf_node_loop:
1872 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1873 break;
1874
1875 case nir_cf_node_function:
1876 ntq_emit_function(c, nir_cf_node_as_function(node));
1877 break;
1878
1879 default:
1880 fprintf(stderr, "Unknown NIR node type\n");
1881 abort();
1882 }
1883 }
1884 }
1885
1886 static void
1887 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1888 {
1889 ntq_setup_registers(c, &impl->registers);
1890 ntq_emit_cf_list(c, &impl->body);
1891 }
1892
1893 static void
1894 nir_to_vir(struct v3d_compile *c)
1895 {
1896 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1897 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1898 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1899 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1900
1901 if (c->fs_key->is_points) {
1902 c->point_x = emit_fragment_varying(c, NULL, 0);
1903 c->point_y = emit_fragment_varying(c, NULL, 0);
1904 } else if (c->fs_key->is_lines) {
1905 c->line_x = emit_fragment_varying(c, NULL, 0);
1906 }
1907 }
1908
1909 ntq_setup_inputs(c);
1910 ntq_setup_outputs(c);
1911 ntq_setup_uniforms(c);
1912 ntq_setup_registers(c, &c->s->registers);
1913
1914 /* Find the main function and emit the body. */
1915 nir_foreach_function(function, c->s) {
1916 assert(strcmp(function->name, "main") == 0);
1917 assert(function->impl);
1918 ntq_emit_impl(c, function->impl);
1919 }
1920 }
1921
1922 const nir_shader_compiler_options v3d_nir_options = {
1923 .lower_all_io_to_temps = true,
1924 .lower_extract_byte = true,
1925 .lower_extract_word = true,
1926 .lower_bfm = true,
1927 .lower_bitfield_insert_to_shifts = true,
1928 .lower_bitfield_extract_to_shifts = true,
1929 .lower_bitfield_reverse = true,
1930 .lower_bit_count = true,
1931 .lower_pack_unorm_2x16 = true,
1932 .lower_pack_snorm_2x16 = true,
1933 .lower_pack_unorm_4x8 = true,
1934 .lower_pack_snorm_4x8 = true,
1935 .lower_unpack_unorm_4x8 = true,
1936 .lower_unpack_snorm_4x8 = true,
1937 .lower_fdiv = true,
1938 .lower_find_lsb = true,
1939 .lower_ffma = true,
1940 .lower_flrp32 = true,
1941 .lower_fpow = true,
1942 .lower_fsat = true,
1943 .lower_fsqrt = true,
1944 .lower_ifind_msb = true,
1945 .lower_ldexp = true,
1946 .lower_mul_high = true,
1947 .native_integers = true,
1948 };
1949
1950
1951 #if 0
1952 static int
1953 count_nir_instrs(nir_shader *nir)
1954 {
1955 int count = 0;
1956 nir_foreach_function(function, nir) {
1957 if (!function->impl)
1958 continue;
1959 nir_foreach_block(block, function->impl) {
1960 nir_foreach_instr(instr, block)
1961 count++;
1962 }
1963 }
1964 return count;
1965 }
1966 #endif
1967
1968 /**
1969 * When demoting a shader down to single-threaded, removes the THRSW
1970 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
1971 * program end).
1972 */
1973 static void
1974 vir_remove_thrsw(struct v3d_compile *c)
1975 {
1976 vir_for_each_block(block, c) {
1977 vir_for_each_inst_safe(inst, block) {
1978 if (inst->qpu.sig.thrsw)
1979 vir_remove_instruction(c, inst);
1980 }
1981 }
1982
1983 c->last_thrsw = NULL;
1984 }
1985
1986 void
1987 vir_emit_last_thrsw(struct v3d_compile *c)
1988 {
1989 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
1990 * switching, so disable threads if we didn't do any TMU ops (each of
1991 * which would have emitted a THRSW).
1992 */
1993 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
1994 c->threads = 1;
1995 if (c->last_thrsw)
1996 vir_remove_thrsw(c);
1997 return;
1998 }
1999
2000 /* If we're threaded and the last THRSW was in conditional code, then
2001 * we need to emit another one so that we can flag it as the last
2002 * thrsw.
2003 */
2004 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2005 assert(c->devinfo->ver >= 41);
2006 vir_emit_thrsw(c);
2007 }
2008
2009 /* If we're threaded, then we need to mark the last THRSW instruction
2010 * so we can emit a pair of them at QPU emit time.
2011 *
2012 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2013 * post-last-THRSW state, so we can skip this.
2014 */
2015 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2016 assert(c->devinfo->ver >= 41);
2017 vir_emit_thrsw(c);
2018 }
2019
2020 if (c->last_thrsw)
2021 c->last_thrsw->is_last_thrsw = true;
2022 }
2023
2024 /* There's a flag in the shader for "center W is needed for reasons other than
2025 * non-centroid varyings", so we just walk the program after VIR optimization
2026 * to see if it's used. It should be harmless to set even if we only use
2027 * center W for varyings.
2028 */
2029 static void
2030 vir_check_payload_w(struct v3d_compile *c)
2031 {
2032 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2033 return;
2034
2035 vir_for_each_inst_inorder(inst, c) {
2036 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2037 if (inst->src[i].file == QFILE_REG &&
2038 inst->src[i].index == 0) {
2039 c->uses_center_w = true;
2040 return;
2041 }
2042 }
2043 }
2044
2045 }
2046
2047 void
2048 v3d_nir_to_vir(struct v3d_compile *c)
2049 {
2050 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2051 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2052 fprintf(stderr, "%s prog %d/%d NIR:\n",
2053 vir_get_stage_name(c),
2054 c->program_id, c->variant_id);
2055 nir_print_shader(c->s, stderr);
2056 }
2057
2058 nir_to_vir(c);
2059
2060 /* Emit the last THRSW before STVPM and TLB writes. */
2061 vir_emit_last_thrsw(c);
2062
2063 switch (c->s->info.stage) {
2064 case MESA_SHADER_FRAGMENT:
2065 emit_frag_end(c);
2066 break;
2067 case MESA_SHADER_VERTEX:
2068 emit_vert_end(c);
2069 break;
2070 default:
2071 unreachable("bad stage");
2072 }
2073
2074 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2075 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2076 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2077 vir_get_stage_name(c),
2078 c->program_id, c->variant_id);
2079 vir_dump(c);
2080 fprintf(stderr, "\n");
2081 }
2082
2083 vir_optimize(c);
2084 vir_lower_uniforms(c);
2085
2086 vir_check_payload_w(c);
2087
2088 /* XXX: vir_schedule_instructions(c); */
2089
2090 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2091 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2092 fprintf(stderr, "%s prog %d/%d VIR:\n",
2093 vir_get_stage_name(c),
2094 c->program_id, c->variant_id);
2095 vir_dump(c);
2096 fprintf(stderr, "\n");
2097 }
2098
2099 /* Attempt to allocate registers for the temporaries. If we fail,
2100 * reduce thread count and try again.
2101 */
2102 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2103 struct qpu_reg *temp_registers;
2104 while (true) {
2105 bool spilled;
2106 temp_registers = v3d_register_allocate(c, &spilled);
2107 if (spilled)
2108 continue;
2109
2110 if (temp_registers)
2111 break;
2112
2113 if (c->threads == min_threads) {
2114 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2115 c->threads);
2116 vir_dump(c);
2117 c->failed = true;
2118 return;
2119 }
2120
2121 c->threads /= 2;
2122
2123 if (c->threads == 1)
2124 vir_remove_thrsw(c);
2125 }
2126
2127 v3d_vir_to_qpu(c, temp_registers);
2128 }