2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
35 /* We don't do any address packing. */
36 #define __gen_user_data void
37 #define __gen_address_type uint32_t
38 #define __gen_address_offset(reloc) (*reloc)
39 #define __gen_emit_reloc(cl, reloc)
40 #include "cle/v3d_packet_v41_pack.h"
42 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
43 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
44 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
45 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
46 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
47 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
53 #define V3D_TSY_SET_QUORUM 0
54 #define V3D_TSY_INC_WAITERS 1
55 #define V3D_TSY_DEC_WAITERS 2
56 #define V3D_TSY_INC_QUORUM 3
57 #define V3D_TSY_DEC_QUORUM 4
58 #define V3D_TSY_FREE_ALL 5
59 #define V3D_TSY_RELEASE 6
60 #define V3D_TSY_ACQUIRE 7
61 #define V3D_TSY_WAIT 8
62 #define V3D_TSY_WAIT_INC 9
63 #define V3D_TSY_WAIT_CHECK 10
64 #define V3D_TSY_WAIT_INC_CHECK 11
65 #define V3D_TSY_WAIT_CV 12
66 #define V3D_TSY_INC_SEMAPHORE 13
67 #define V3D_TSY_DEC_SEMAPHORE 14
68 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
71 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
74 resize_qreg_array(struct v3d_compile
*c
,
79 if (*size
>= decl_size
)
82 uint32_t old_size
= *size
;
83 *size
= MAX2(*size
* 2, decl_size
);
84 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
86 fprintf(stderr
, "Malloc failure\n");
90 for (uint32_t i
= old_size
; i
< *size
; i
++)
91 (*regs
)[i
] = c
->undef
;
95 vir_emit_thrsw(struct v3d_compile
*c
)
100 /* Always thread switch after each texture operation for now.
102 * We could do better by batching a bunch of texture fetches up and
103 * then doing one thread switch and collecting all their results
106 c
->last_thrsw
= vir_NOP(c
);
107 c
->last_thrsw
->qpu
.sig
.thrsw
= true;
108 c
->last_thrsw_at_top_level
= !c
->in_control_flow
;
110 /* We need to lock the scoreboard before any tlb acess happens. If this
111 * thread switch comes after we have emitted a tlb load, then it means
112 * that we can't lock on the last thread switch any more.
114 if (c
->emitted_tlb_load
)
115 c
->lock_scoreboard_on_first_thrsw
= true;
119 v3d_get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
121 if (nir_src_is_const(instr
->src
[src
])) {
122 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
124 return V3D_TMU_OP_WRITE_AND_READ_INC
;
125 else if (add_val
== -1)
126 return V3D_TMU_OP_WRITE_OR_READ_DEC
;
129 return V3D_TMU_OP_WRITE_ADD_READ_PREFETCH
;
133 v3d_general_tmu_op(nir_intrinsic_instr
*instr
)
135 switch (instr
->intrinsic
) {
136 case nir_intrinsic_load_ssbo
:
137 case nir_intrinsic_load_ubo
:
138 case nir_intrinsic_load_uniform
:
139 case nir_intrinsic_load_shared
:
140 case nir_intrinsic_load_scratch
:
141 case nir_intrinsic_store_ssbo
:
142 case nir_intrinsic_store_shared
:
143 case nir_intrinsic_store_scratch
:
144 return V3D_TMU_OP_REGULAR
;
145 case nir_intrinsic_ssbo_atomic_add
:
146 return v3d_get_op_for_atomic_add(instr
, 2);
147 case nir_intrinsic_shared_atomic_add
:
148 return v3d_get_op_for_atomic_add(instr
, 1);
149 case nir_intrinsic_ssbo_atomic_imin
:
150 case nir_intrinsic_shared_atomic_imin
:
151 return V3D_TMU_OP_WRITE_SMIN
;
152 case nir_intrinsic_ssbo_atomic_umin
:
153 case nir_intrinsic_shared_atomic_umin
:
154 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR
;
155 case nir_intrinsic_ssbo_atomic_imax
:
156 case nir_intrinsic_shared_atomic_imax
:
157 return V3D_TMU_OP_WRITE_SMAX
;
158 case nir_intrinsic_ssbo_atomic_umax
:
159 case nir_intrinsic_shared_atomic_umax
:
160 return V3D_TMU_OP_WRITE_UMAX
;
161 case nir_intrinsic_ssbo_atomic_and
:
162 case nir_intrinsic_shared_atomic_and
:
163 return V3D_TMU_OP_WRITE_AND_READ_INC
;
164 case nir_intrinsic_ssbo_atomic_or
:
165 case nir_intrinsic_shared_atomic_or
:
166 return V3D_TMU_OP_WRITE_OR_READ_DEC
;
167 case nir_intrinsic_ssbo_atomic_xor
:
168 case nir_intrinsic_shared_atomic_xor
:
169 return V3D_TMU_OP_WRITE_XOR_READ_NOT
;
170 case nir_intrinsic_ssbo_atomic_exchange
:
171 case nir_intrinsic_shared_atomic_exchange
:
172 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH
;
173 case nir_intrinsic_ssbo_atomic_comp_swap
:
174 case nir_intrinsic_shared_atomic_comp_swap
:
175 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH
;
177 unreachable("unknown intrinsic op");
182 * Implements indirect uniform loads and SSBO accesses through the TMU general
183 * memory access interface.
186 ntq_emit_tmu_general(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
,
187 bool is_shared_or_scratch
)
189 uint32_t tmu_op
= v3d_general_tmu_op(instr
);
191 /* If we were able to replace atomic_add for an inc/dec, then we
192 * need/can to do things slightly different, like not loading the
193 * amount to add/sub, as that is implicit.
195 bool atomic_add_replaced
=
196 ((instr
->intrinsic
== nir_intrinsic_ssbo_atomic_add
||
197 instr
->intrinsic
== nir_intrinsic_shared_atomic_add
) &&
198 (tmu_op
== V3D_TMU_OP_WRITE_AND_READ_INC
||
199 tmu_op
== V3D_TMU_OP_WRITE_OR_READ_DEC
));
201 bool is_store
= (instr
->intrinsic
== nir_intrinsic_store_ssbo
||
202 instr
->intrinsic
== nir_intrinsic_store_scratch
||
203 instr
->intrinsic
== nir_intrinsic_store_shared
);
205 bool is_load
= (instr
->intrinsic
== nir_intrinsic_load_uniform
||
206 instr
->intrinsic
== nir_intrinsic_load_ubo
||
207 instr
->intrinsic
== nir_intrinsic_load_ssbo
||
208 instr
->intrinsic
== nir_intrinsic_load_scratch
||
209 instr
->intrinsic
== nir_intrinsic_load_shared
);
211 bool has_index
= !is_shared_or_scratch
;
214 if (instr
->intrinsic
== nir_intrinsic_load_uniform
) {
216 } else if (instr
->intrinsic
== nir_intrinsic_load_ssbo
||
217 instr
->intrinsic
== nir_intrinsic_load_ubo
||
218 instr
->intrinsic
== nir_intrinsic_load_scratch
||
219 instr
->intrinsic
== nir_intrinsic_load_shared
||
220 atomic_add_replaced
) {
221 offset_src
= 0 + has_index
;
222 } else if (is_store
) {
223 offset_src
= 1 + has_index
;
225 offset_src
= 0 + has_index
;
228 bool dynamic_src
= !nir_src_is_const(instr
->src
[offset_src
]);
229 uint32_t const_offset
= 0;
231 const_offset
= nir_src_as_uint(instr
->src
[offset_src
]);
233 struct qreg base_offset
;
234 if (instr
->intrinsic
== nir_intrinsic_load_uniform
) {
235 const_offset
+= nir_intrinsic_base(instr
);
236 base_offset
= vir_uniform(c
, QUNIFORM_UBO_ADDR
,
237 v3d_unit_data_create(0, const_offset
));
239 } else if (instr
->intrinsic
== nir_intrinsic_load_ubo
) {
240 uint32_t index
= nir_src_as_uint(instr
->src
[0]) + 1;
241 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
242 * 1 (0 is gallium's constant buffer 0).
245 vir_uniform(c
, QUNIFORM_UBO_ADDR
,
246 v3d_unit_data_create(index
, const_offset
));
248 } else if (is_shared_or_scratch
) {
249 /* Shared and scratch variables have no buffer index, and all
250 * start from a common base that we set up at the start of
253 if (instr
->intrinsic
== nir_intrinsic_load_scratch
||
254 instr
->intrinsic
== nir_intrinsic_store_scratch
) {
255 base_offset
= c
->spill_base
;
257 base_offset
= c
->cs_shared_offset
;
258 const_offset
+= nir_intrinsic_base(instr
);
261 base_offset
= vir_uniform(c
, QUNIFORM_SSBO_OFFSET
,
262 nir_src_as_uint(instr
->src
[is_store
?
266 struct qreg tmud
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUD
);
267 unsigned writemask
= is_store
? nir_intrinsic_write_mask(instr
) : 0;
268 uint32_t base_const_offset
= const_offset
;
269 int first_component
= -1;
270 int last_component
= -1;
272 int tmu_writes
= 1; /* address */
275 /* Find the first set of consecutive components that
276 * are enabled in the writemask and emit the TMUD
277 * instructions for them.
279 first_component
= ffs(writemask
) - 1;
280 last_component
= first_component
;
281 while (writemask
& BITFIELD_BIT(last_component
+ 1))
284 assert(first_component
>= 0 &&
285 first_component
<= last_component
&&
286 last_component
< instr
->num_components
);
288 struct qreg tmud
= vir_reg(QFILE_MAGIC
,
290 for (int i
= first_component
; i
<= last_component
; i
++) {
292 ntq_get_src(c
, instr
->src
[0], i
);
293 vir_MOV_dest(c
, tmud
, data
);
297 /* Update the offset for the TMU write based on the
298 * the first component we are writing.
300 const_offset
= base_const_offset
+ first_component
* 4;
302 /* Clear these components from the writemask */
303 uint32_t written_mask
=
304 BITFIELD_RANGE(first_component
, tmu_writes
- 1);
305 writemask
&= ~written_mask
;
306 } else if (!is_load
&& !atomic_add_replaced
) {
308 ntq_get_src(c
, instr
->src
[1 + has_index
], 0);
309 vir_MOV_dest(c
, tmud
, data
);
311 if (tmu_op
== V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH
) {
312 data
= ntq_get_src(c
, instr
->src
[2 + has_index
],
314 vir_MOV_dest(c
, tmud
, data
);
319 /* Make sure we won't exceed the 16-entry TMU fifo if each
320 * thread is storing at the same time.
322 while (tmu_writes
> 16 / c
->threads
)
325 /* The spec says that for atomics, the TYPE field is ignored,
326 * but that doesn't seem to be the case for CMPXCHG. Just use
327 * the number of tmud writes we did to decide the type (or
328 * choose "32bit" for atomic reads, which has been fine).
330 uint32_t num_components
;
331 if (is_load
|| atomic_add_replaced
) {
332 num_components
= instr
->num_components
;
334 assert(tmu_writes
> 1);
335 num_components
= tmu_writes
- 1;
338 uint32_t config
= (0xffffff00 |
340 GENERAL_TMU_LOOKUP_PER_PIXEL
);
341 if (num_components
== 1) {
342 config
|= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI
;
344 config
|= GENERAL_TMU_LOOKUP_TYPE_VEC2
+
348 if (vir_in_nonuniform_control_flow(c
)) {
349 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
355 tmua
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUA
);
357 tmua
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_TMUAU
);
361 struct qreg offset
= base_offset
;
362 if (const_offset
!= 0) {
363 offset
= vir_ADD(c
, offset
,
364 vir_uniform_ui(c
, const_offset
));
367 ntq_get_src(c
, instr
->src
[offset_src
], 0);
368 tmu
= vir_ADD_dest(c
, tmua
, offset
, data
);
370 if (const_offset
!= 0) {
371 tmu
= vir_ADD_dest(c
, tmua
, base_offset
,
372 vir_uniform_ui(c
, const_offset
));
374 tmu
= vir_MOV_dest(c
, tmua
, base_offset
);
380 vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
384 if (vir_in_nonuniform_control_flow(c
))
385 vir_set_cond(tmu
, V3D_QPU_COND_IFA
);
389 /* Read the result, or wait for the TMU op to complete. */
390 for (int i
= 0; i
< nir_intrinsic_dest_components(instr
); i
++) {
391 ntq_store_dest(c
, &instr
->dest
, i
,
392 vir_MOV(c
, vir_LDTMU(c
)));
395 if (nir_intrinsic_dest_components(instr
) == 0)
397 } while (is_store
&& writemask
!= 0);
401 ntq_init_ssa_def(struct v3d_compile
*c
, nir_ssa_def
*def
)
403 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
404 def
->num_components
);
405 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
410 * This function is responsible for getting VIR results into the associated
411 * storage for a NIR instruction.
413 * If it's a NIR SSA def, then we just set the associated hash table entry to
416 * If it's a NIR reg, then we need to update the existing qreg assigned to the
417 * NIR destination with the incoming value. To do that without introducing
418 * new MOVs, we require that the incoming qreg either be a uniform, or be
419 * SSA-defined by the previous VIR instruction in the block and rewritable by
420 * this function. That lets us sneak ahead and insert the SF flag beforehand
421 * (knowing that the previous instruction doesn't depend on flags) and rewrite
422 * its destination to be the NIR reg's destination
425 ntq_store_dest(struct v3d_compile
*c
, nir_dest
*dest
, int chan
,
428 struct qinst
*last_inst
= NULL
;
429 if (!list_empty(&c
->cur_block
->instructions
))
430 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
432 assert((result
.file
== QFILE_TEMP
&&
433 last_inst
&& last_inst
== c
->defs
[result
.index
]));
436 assert(chan
< dest
->ssa
.num_components
);
439 struct hash_entry
*entry
=
440 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
445 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
447 qregs
[chan
] = result
;
449 nir_register
*reg
= dest
->reg
.reg
;
450 assert(dest
->reg
.base_offset
== 0);
451 assert(reg
->num_array_elems
== 0);
452 struct hash_entry
*entry
=
453 _mesa_hash_table_search(c
->def_ht
, reg
);
454 struct qreg
*qregs
= entry
->data
;
456 /* Insert a MOV if the source wasn't an SSA def in the
457 * previous instruction.
459 if ((vir_in_nonuniform_control_flow(c
) &&
460 c
->defs
[last_inst
->dst
.index
]->qpu
.sig
.ldunif
)) {
461 result
= vir_MOV(c
, result
);
462 last_inst
= c
->defs
[result
.index
];
465 /* We know they're both temps, so just rewrite index. */
466 c
->defs
[last_inst
->dst
.index
] = NULL
;
467 last_inst
->dst
.index
= qregs
[chan
].index
;
469 /* If we're in control flow, then make this update of the reg
470 * conditional on the execution mask.
472 if (vir_in_nonuniform_control_flow(c
)) {
473 last_inst
->dst
.index
= qregs
[chan
].index
;
475 /* Set the flags to the current exec mask.
477 c
->cursor
= vir_before_inst(last_inst
);
478 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
480 c
->cursor
= vir_after_inst(last_inst
);
482 vir_set_cond(last_inst
, V3D_QPU_COND_IFA
);
488 ntq_get_src(struct v3d_compile
*c
, nir_src src
, int i
)
490 struct hash_entry
*entry
;
492 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
493 assert(i
< src
.ssa
->num_components
);
495 nir_register
*reg
= src
.reg
.reg
;
496 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
497 assert(reg
->num_array_elems
== 0);
498 assert(src
.reg
.base_offset
== 0);
499 assert(i
< reg
->num_components
);
502 struct qreg
*qregs
= entry
->data
;
507 ntq_get_alu_src(struct v3d_compile
*c
, nir_alu_instr
*instr
,
510 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
511 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
512 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
513 instr
->src
[src
].swizzle
[chan
]);
515 assert(!instr
->src
[src
].abs
);
516 assert(!instr
->src
[src
].negate
);
522 ntq_minify(struct v3d_compile
*c
, struct qreg size
, struct qreg level
)
524 return vir_MAX(c
, vir_SHR(c
, size
, level
), vir_uniform_ui(c
, 1));
528 ntq_emit_txs(struct v3d_compile
*c
, nir_tex_instr
*instr
)
530 unsigned unit
= instr
->texture_index
;
531 int lod_index
= nir_tex_instr_src_index(instr
, nir_tex_src_lod
);
532 int dest_size
= nir_tex_instr_dest_size(instr
);
534 struct qreg lod
= c
->undef
;
536 lod
= ntq_get_src(c
, instr
->src
[lod_index
].src
, 0);
538 for (int i
= 0; i
< dest_size
; i
++) {
540 enum quniform_contents contents
;
542 if (instr
->is_array
&& i
== dest_size
- 1)
543 contents
= QUNIFORM_TEXTURE_ARRAY_SIZE
;
545 contents
= QUNIFORM_TEXTURE_WIDTH
+ i
;
547 struct qreg size
= vir_uniform(c
, contents
, unit
);
549 switch (instr
->sampler_dim
) {
550 case GLSL_SAMPLER_DIM_1D
:
551 case GLSL_SAMPLER_DIM_2D
:
552 case GLSL_SAMPLER_DIM_MS
:
553 case GLSL_SAMPLER_DIM_3D
:
554 case GLSL_SAMPLER_DIM_CUBE
:
555 /* Don't minify the array size. */
556 if (!(instr
->is_array
&& i
== dest_size
- 1)) {
557 size
= ntq_minify(c
, size
, lod
);
561 case GLSL_SAMPLER_DIM_RECT
:
562 /* There's no LOD field for rects */
566 unreachable("Bad sampler type");
569 ntq_store_dest(c
, &instr
->dest
, i
, size
);
574 ntq_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
)
576 unsigned unit
= instr
->texture_index
;
578 /* Since each texture sampling op requires uploading uniforms to
579 * reference the texture, there's no HW support for texture size and
580 * you just upload uniforms containing the size.
583 case nir_texop_query_levels
:
584 ntq_store_dest(c
, &instr
->dest
, 0,
585 vir_uniform(c
, QUNIFORM_TEXTURE_LEVELS
, unit
));
588 ntq_emit_txs(c
, instr
);
594 if (c
->devinfo
->ver
>= 40)
595 v3d40_vir_emit_tex(c
, instr
);
597 v3d33_vir_emit_tex(c
, instr
);
601 ntq_fsincos(struct v3d_compile
*c
, struct qreg src
, bool is_cos
)
603 struct qreg input
= vir_FMUL(c
, src
, vir_uniform_f(c
, 1.0f
/ M_PI
));
605 input
= vir_FADD(c
, input
, vir_uniform_f(c
, 0.5));
607 struct qreg periods
= vir_FROUND(c
, input
);
608 struct qreg sin_output
= vir_SIN(c
, vir_FSUB(c
, input
, periods
));
609 return vir_XOR(c
, sin_output
, vir_SHL(c
,
610 vir_FTOIN(c
, periods
),
611 vir_uniform_ui(c
, -1)));
615 ntq_fsign(struct v3d_compile
*c
, struct qreg src
)
617 struct qreg t
= vir_get_temp(c
);
619 vir_MOV_dest(c
, t
, vir_uniform_f(c
, 0.0));
620 vir_set_pf(vir_FMOV_dest(c
, vir_nop_reg(), src
), V3D_QPU_PF_PUSHZ
);
621 vir_MOV_cond(c
, V3D_QPU_COND_IFNA
, t
, vir_uniform_f(c
, 1.0));
622 vir_set_pf(vir_FMOV_dest(c
, vir_nop_reg(), src
), V3D_QPU_PF_PUSHN
);
623 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, t
, vir_uniform_f(c
, -1.0));
624 return vir_MOV(c
, t
);
628 emit_fragcoord_input(struct v3d_compile
*c
, int attr
)
630 c
->inputs
[attr
* 4 + 0] = vir_FXCD(c
);
631 c
->inputs
[attr
* 4 + 1] = vir_FYCD(c
);
632 c
->inputs
[attr
* 4 + 2] = c
->payload_z
;
633 c
->inputs
[attr
* 4 + 3] = vir_RECIP(c
, c
->payload_w
);
637 emit_fragment_varying(struct v3d_compile
*c
, nir_variable
*var
,
638 uint8_t swizzle
, int array_index
)
640 struct qreg r3
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R3
);
641 struct qreg r5
= vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_R5
);
644 if (c
->devinfo
->ver
>= 41) {
645 struct qinst
*ldvary
= vir_add_inst(V3D_QPU_A_NOP
, c
->undef
,
647 ldvary
->qpu
.sig
.ldvary
= true;
648 vary
= vir_emit_def(c
, ldvary
);
650 vir_NOP(c
)->qpu
.sig
.ldvary
= true;
654 /* For gl_PointCoord input or distance along a line, we'll be called
655 * with no nir_variable, and we don't count toward VPM size so we
656 * don't track an input slot.
659 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
662 int i
= c
->num_inputs
++;
664 v3d_slot_from_slot_and_component(var
->data
.location
+
665 array_index
, swizzle
);
667 switch (var
->data
.interpolation
) {
668 case INTERP_MODE_NONE
:
669 /* If a gl_FrontColor or gl_BackColor input has no interp
670 * qualifier, then if we're using glShadeModel(GL_FLAT) it
671 * needs to be flat shaded.
673 switch (var
->data
.location
+ array_index
) {
674 case VARYING_SLOT_COL0
:
675 case VARYING_SLOT_COL1
:
676 case VARYING_SLOT_BFC0
:
677 case VARYING_SLOT_BFC1
:
678 if (c
->fs_key
->shade_model_flat
) {
679 BITSET_SET(c
->flat_shade_flags
, i
);
680 vir_MOV_dest(c
, c
->undef
, vary
);
681 return vir_MOV(c
, r5
);
683 return vir_FADD(c
, vir_FMUL(c
, vary
,
690 case INTERP_MODE_SMOOTH
:
691 if (var
->data
.centroid
) {
692 BITSET_SET(c
->centroid_flags
, i
);
693 return vir_FADD(c
, vir_FMUL(c
, vary
,
694 c
->payload_w_centroid
), r5
);
696 return vir_FADD(c
, vir_FMUL(c
, vary
, c
->payload_w
), r5
);
698 case INTERP_MODE_NOPERSPECTIVE
:
699 BITSET_SET(c
->noperspective_flags
, i
);
700 return vir_FADD(c
, vir_MOV(c
, vary
), r5
);
701 case INTERP_MODE_FLAT
:
702 BITSET_SET(c
->flat_shade_flags
, i
);
703 vir_MOV_dest(c
, c
->undef
, vary
);
704 return vir_MOV(c
, r5
);
706 unreachable("Bad interp mode");
711 emit_fragment_input(struct v3d_compile
*c
, int attr
, nir_variable
*var
,
714 for (int i
= 0; i
< glsl_get_vector_elements(var
->type
); i
++) {
715 int chan
= var
->data
.location_frac
+ i
;
716 c
->inputs
[attr
* 4 + chan
] =
717 emit_fragment_varying(c
, var
, chan
, array_index
);
722 add_output(struct v3d_compile
*c
,
723 uint32_t decl_offset
,
727 uint32_t old_array_size
= c
->outputs_array_size
;
728 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
731 if (old_array_size
!= c
->outputs_array_size
) {
732 c
->output_slots
= reralloc(c
,
734 struct v3d_varying_slot
,
735 c
->outputs_array_size
);
738 c
->output_slots
[decl_offset
] =
739 v3d_slot_from_slot_and_component(slot
, swizzle
);
743 * If compare_instr is a valid comparison instruction, emits the
744 * compare_instr's comparison and returns the sel_instr's return value based
745 * on the compare_instr's result.
748 ntq_emit_comparison(struct v3d_compile
*c
,
749 nir_alu_instr
*compare_instr
,
750 enum v3d_qpu_cond
*out_cond
)
752 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
754 if (nir_op_infos
[compare_instr
->op
].num_inputs
> 1)
755 src1
= ntq_get_alu_src(c
, compare_instr
, 1);
756 bool cond_invert
= false;
757 struct qreg nop
= vir_nop_reg();
759 switch (compare_instr
->op
) {
762 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
765 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
770 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
774 vir_set_pf(vir_XOR_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHZ
);
780 vir_set_pf(vir_FCMP_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
783 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
787 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
793 vir_set_pf(vir_FCMP_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHN
);
796 vir_set_pf(vir_MIN_dest(c
, nop
, src1
, src0
), V3D_QPU_PF_PUSHC
);
799 vir_set_pf(vir_SUB_dest(c
, nop
, src0
, src1
), V3D_QPU_PF_PUSHC
);
803 vir_set_pf(vir_MOV_dest(c
, nop
, src0
), V3D_QPU_PF_PUSHZ
);
808 vir_set_pf(vir_FMOV_dest(c
, nop
, src0
), V3D_QPU_PF_PUSHZ
);
816 *out_cond
= cond_invert
? V3D_QPU_COND_IFNA
: V3D_QPU_COND_IFA
;
821 /* Finds an ALU instruction that generates our src value that could
822 * (potentially) be greedily emitted in the consuming instruction.
824 static struct nir_alu_instr
*
825 ntq_get_alu_parent(nir_src src
)
827 if (!src
.is_ssa
|| src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
829 nir_alu_instr
*instr
= nir_instr_as_alu(src
.ssa
->parent_instr
);
833 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
834 * moving emission of the ALU instr down past another write of the
837 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
838 if (!instr
->src
[i
].src
.is_ssa
)
845 /* Turns a NIR bool into a condition code to predicate on. */
846 static enum v3d_qpu_cond
847 ntq_emit_bool_to_cond(struct v3d_compile
*c
, nir_src src
)
849 nir_alu_instr
*compare
= ntq_get_alu_parent(src
);
853 enum v3d_qpu_cond cond
;
854 if (ntq_emit_comparison(c
, compare
, &cond
))
858 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), ntq_get_src(c
, src
, 0)),
860 return V3D_QPU_COND_IFNA
;
864 ntq_emit_alu(struct v3d_compile
*c
, nir_alu_instr
*instr
)
866 /* This should always be lowered to ALU operations for V3D. */
867 assert(!instr
->dest
.saturate
);
869 /* Vectors are special in that they have non-scalarized writemasks,
870 * and just take the first swizzle channel for each argument in order
871 * into each writemask channel.
873 if (instr
->op
== nir_op_vec2
||
874 instr
->op
== nir_op_vec3
||
875 instr
->op
== nir_op_vec4
) {
877 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
878 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
879 instr
->src
[i
].swizzle
[0]);
880 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
881 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
882 vir_MOV(c
, srcs
[i
]));
886 /* General case: We can just grab the one used channel per src. */
887 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
888 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
889 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
896 result
= vir_MOV(c
, src
[0]);
900 result
= vir_XOR(c
, src
[0], vir_uniform_ui(c
, 1 << 31));
903 result
= vir_NEG(c
, src
[0]);
907 result
= vir_FMUL(c
, src
[0], src
[1]);
910 result
= vir_FADD(c
, src
[0], src
[1]);
913 result
= vir_FSUB(c
, src
[0], src
[1]);
916 result
= vir_FMIN(c
, src
[0], src
[1]);
919 result
= vir_FMAX(c
, src
[0], src
[1]);
923 nir_alu_instr
*src0_alu
= ntq_get_alu_parent(instr
->src
[0].src
);
924 if (src0_alu
&& src0_alu
->op
== nir_op_fround_even
) {
925 result
= vir_FTOIN(c
, ntq_get_alu_src(c
, src0_alu
, 0));
927 result
= vir_FTOIZ(c
, src
[0]);
933 result
= vir_FTOUZ(c
, src
[0]);
936 result
= vir_ITOF(c
, src
[0]);
939 result
= vir_UTOF(c
, src
[0]);
942 result
= vir_AND(c
, src
[0], vir_uniform_f(c
, 1.0));
945 result
= vir_AND(c
, src
[0], vir_uniform_ui(c
, 1));
949 result
= vir_ADD(c
, src
[0], src
[1]);
952 result
= vir_SHR(c
, src
[0], src
[1]);
955 result
= vir_SUB(c
, src
[0], src
[1]);
958 result
= vir_ASR(c
, src
[0], src
[1]);
961 result
= vir_SHL(c
, src
[0], src
[1]);
964 result
= vir_MIN(c
, src
[0], src
[1]);
967 result
= vir_UMIN(c
, src
[0], src
[1]);
970 result
= vir_MAX(c
, src
[0], src
[1]);
973 result
= vir_UMAX(c
, src
[0], src
[1]);
976 result
= vir_AND(c
, src
[0], src
[1]);
979 result
= vir_OR(c
, src
[0], src
[1]);
982 result
= vir_XOR(c
, src
[0], src
[1]);
985 result
= vir_NOT(c
, src
[0]);
988 case nir_op_ufind_msb
:
989 result
= vir_SUB(c
, vir_uniform_ui(c
, 31), vir_CLZ(c
, src
[0]));
993 result
= vir_UMUL(c
, src
[0], src
[1]);
1000 enum v3d_qpu_cond cond
;
1001 ASSERTED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
1003 result
= vir_MOV(c
, vir_SEL(c
, cond
,
1004 vir_uniform_f(c
, 1.0),
1005 vir_uniform_f(c
, 0.0)));
1020 case nir_op_ult32
: {
1021 enum v3d_qpu_cond cond
;
1022 ASSERTED
bool ok
= ntq_emit_comparison(c
, instr
, &cond
);
1024 result
= vir_MOV(c
, vir_SEL(c
, cond
,
1025 vir_uniform_ui(c
, ~0),
1026 vir_uniform_ui(c
, 0)));
1030 case nir_op_b32csel
:
1033 ntq_emit_bool_to_cond(c
, instr
->src
[0].src
),
1038 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), src
[0]),
1040 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFNA
,
1045 result
= vir_RECIP(c
, src
[0]);
1048 result
= vir_RSQRT(c
, src
[0]);
1051 result
= vir_EXP(c
, src
[0]);
1054 result
= vir_LOG(c
, src
[0]);
1058 result
= vir_FCEIL(c
, src
[0]);
1061 result
= vir_FFLOOR(c
, src
[0]);
1063 case nir_op_fround_even
:
1064 result
= vir_FROUND(c
, src
[0]);
1067 result
= vir_FTRUNC(c
, src
[0]);
1071 result
= ntq_fsincos(c
, src
[0], false);
1074 result
= ntq_fsincos(c
, src
[0], true);
1078 result
= ntq_fsign(c
, src
[0]);
1082 result
= vir_FMOV(c
, src
[0]);
1083 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_ABS
);
1088 result
= vir_MAX(c
, src
[0], vir_NEG(c
, src
[0]));
1092 case nir_op_fddx_coarse
:
1093 case nir_op_fddx_fine
:
1094 result
= vir_FDX(c
, src
[0]);
1098 case nir_op_fddy_coarse
:
1099 case nir_op_fddy_fine
:
1100 result
= vir_FDY(c
, src
[0]);
1103 case nir_op_uadd_carry
:
1104 vir_set_pf(vir_ADD_dest(c
, vir_nop_reg(), src
[0], src
[1]),
1106 result
= vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
1107 vir_uniform_ui(c
, ~0),
1108 vir_uniform_ui(c
, 0)));
1111 case nir_op_pack_half_2x16_split
:
1112 result
= vir_VFPACK(c
, src
[0], src
[1]);
1115 case nir_op_unpack_half_2x16_split_x
:
1116 result
= vir_FMOV(c
, src
[0]);
1117 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_L
);
1120 case nir_op_unpack_half_2x16_split_y
:
1121 result
= vir_FMOV(c
, src
[0]);
1122 vir_set_unpack(c
->defs
[result
.index
], 0, V3D_QPU_UNPACK_H
);
1126 fprintf(stderr
, "unknown NIR ALU inst: ");
1127 nir_print_instr(&instr
->instr
, stderr
);
1128 fprintf(stderr
, "\n");
1132 /* We have a scalar result, so the instruction should only have a
1133 * single channel written to.
1135 assert(util_is_power_of_two_or_zero(instr
->dest
.write_mask
));
1136 ntq_store_dest(c
, &instr
->dest
.dest
,
1137 ffs(instr
->dest
.write_mask
) - 1, result
);
1140 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1141 * specifier. They come from a register that's preloaded with 0xffffffff
1142 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1143 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1145 #define TLB_TYPE_F16_COLOR (3 << 6)
1146 #define TLB_TYPE_I32_COLOR (1 << 6)
1147 #define TLB_TYPE_F32_COLOR (0 << 6)
1148 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1149 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1150 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1151 #define TLB_F16_SWAP_HI_LO (1 << 1)
1152 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1153 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1154 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1156 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1159 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1160 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1161 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1162 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1163 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1165 /* Stencil is a single 32-bit write. */
1166 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1169 vir_emit_tlb_color_write(struct v3d_compile
*c
, unsigned rt
)
1171 if (!(c
->fs_key
->cbufs
& (1 << rt
)) || !c
->output_color_var
[rt
])
1174 struct qreg tlb_reg
= vir_magic_reg(V3D_QPU_WADDR_TLB
);
1175 struct qreg tlbu_reg
= vir_magic_reg(V3D_QPU_WADDR_TLBU
);
1177 nir_variable
*var
= c
->output_color_var
[rt
];
1178 int num_components
= glsl_get_vector_elements(var
->type
);
1179 uint32_t conf
= 0xffffff00;
1182 conf
|= c
->msaa_per_sample_output
? TLB_SAMPLE_MODE_PER_SAMPLE
:
1183 TLB_SAMPLE_MODE_PER_PIXEL
;
1184 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
1186 if (c
->fs_key
->swap_color_rb
& (1 << rt
))
1187 num_components
= MAX2(num_components
, 3);
1188 assert(num_components
!= 0);
1190 enum glsl_base_type type
= glsl_get_base_type(var
->type
);
1191 bool is_int_format
= type
== GLSL_TYPE_INT
|| type
== GLSL_TYPE_UINT
;
1192 bool is_32b_tlb_format
= is_int_format
||
1193 (c
->fs_key
->f32_color_rb
& (1 << rt
));
1195 if (is_int_format
) {
1196 /* The F32 vs I32 distinction was dropped in 4.2. */
1197 if (c
->devinfo
->ver
< 42)
1198 conf
|= TLB_TYPE_I32_COLOR
;
1200 conf
|= TLB_TYPE_F32_COLOR
;
1201 conf
|= ((num_components
- 1) << TLB_VEC_SIZE_MINUS_1_SHIFT
);
1203 if (c
->fs_key
->f32_color_rb
& (1 << rt
)) {
1204 conf
|= TLB_TYPE_F32_COLOR
;
1205 conf
|= ((num_components
- 1) <<
1206 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1208 conf
|= TLB_TYPE_F16_COLOR
;
1209 conf
|= TLB_F16_SWAP_HI_LO
;
1210 if (num_components
>= 3)
1211 conf
|= TLB_VEC_SIZE_4_F16
;
1213 conf
|= TLB_VEC_SIZE_2_F16
;
1217 int num_samples
= c
->msaa_per_sample_output
? V3D_MAX_SAMPLES
: 1;
1218 for (int i
= 0; i
< num_samples
; i
++) {
1219 struct qreg
*color
= c
->msaa_per_sample_output
?
1220 &c
->sample_colors
[(rt
* V3D_MAX_SAMPLES
+ i
) * 4] :
1221 &c
->outputs
[var
->data
.driver_location
* 4];
1223 struct qreg r
= color
[0];
1224 struct qreg g
= color
[1];
1225 struct qreg b
= color
[2];
1226 struct qreg a
= color
[3];
1228 if (c
->fs_key
->swap_color_rb
& (1 << rt
)) {
1233 if (c
->fs_key
->sample_alpha_to_one
)
1234 a
= vir_uniform_f(c
, 1.0);
1236 if (is_32b_tlb_format
) {
1238 inst
= vir_MOV_dest(c
, tlbu_reg
, r
);
1240 vir_get_uniform_index(c
,
1244 inst
= vir_MOV_dest(c
, tlb_reg
, r
);
1247 if (num_components
>= 2)
1248 vir_MOV_dest(c
, tlb_reg
, g
);
1249 if (num_components
>= 3)
1250 vir_MOV_dest(c
, tlb_reg
, b
);
1251 if (num_components
>= 4)
1252 vir_MOV_dest(c
, tlb_reg
, a
);
1254 inst
= vir_VFPACK_dest(c
, tlb_reg
, r
, g
);
1255 if (conf
!= ~0 && i
== 0) {
1256 inst
->dst
= tlbu_reg
;
1258 vir_get_uniform_index(c
,
1263 if (num_components
>= 3)
1264 inst
= vir_VFPACK_dest(c
, tlb_reg
, b
, a
);
1270 emit_frag_end(struct v3d_compile
*c
)
1273 if (c->output_sample_mask_index != -1) {
1274 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1278 bool has_any_tlb_color_write
= false;
1279 for (int rt
= 0; rt
< V3D_MAX_DRAW_BUFFERS
; rt
++) {
1280 if (c
->fs_key
->cbufs
& (1 << rt
) && c
->output_color_var
[rt
])
1281 has_any_tlb_color_write
= true;
1284 if (c
->fs_key
->sample_alpha_to_coverage
&& c
->output_color_var
[0]) {
1285 struct nir_variable
*var
= c
->output_color_var
[0];
1286 struct qreg
*color
= &c
->outputs
[var
->data
.driver_location
* 4];
1288 vir_SETMSF_dest(c
, vir_nop_reg(),
1291 vir_FTOC(c
, color
[3])));
1294 struct qreg tlbu_reg
= vir_magic_reg(V3D_QPU_WADDR_TLBU
);
1295 if (c
->output_position_index
!= -1) {
1296 struct qinst
*inst
= vir_MOV_dest(c
, tlbu_reg
,
1297 c
->outputs
[c
->output_position_index
]);
1298 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1300 if (c
->devinfo
->ver
>= 42) {
1301 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_PER_PIXEL
|
1302 TLB_SAMPLE_MODE_PER_PIXEL
);
1304 tlb_specifier
|= TLB_DEPTH_TYPE_PER_PIXEL
;
1306 inst
->uniform
= vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
1310 } else if (c
->s
->info
.fs
.uses_discard
||
1311 !c
->s
->info
.fs
.early_fragment_tests
||
1312 c
->fs_key
->sample_alpha_to_coverage
||
1313 !has_any_tlb_color_write
) {
1314 /* Emit passthrough Z if it needed to be delayed until shader
1315 * end due to potential discards.
1317 * Since (single-threaded) fragment shaders always need a TLB
1318 * write, emit passthrouh Z if we didn't have any color
1319 * buffers and flag us as potentially discarding, so that we
1320 * can use Z as the TLB write.
1322 c
->s
->info
.fs
.uses_discard
= true;
1324 struct qinst
*inst
= vir_MOV_dest(c
, tlbu_reg
,
1326 uint8_t tlb_specifier
= TLB_TYPE_DEPTH
;
1328 if (c
->devinfo
->ver
>= 42) {
1329 /* The spec says the PER_PIXEL flag is ignored for
1330 * invariant writes, but the simulator demands it.
1332 tlb_specifier
|= (TLB_V42_DEPTH_TYPE_INVARIANT
|
1333 TLB_SAMPLE_MODE_PER_PIXEL
);
1335 tlb_specifier
|= TLB_DEPTH_TYPE_INVARIANT
;
1338 inst
->uniform
= vir_get_uniform_index(c
,
1345 /* XXX: Performance improvement: Merge Z write and color writes TLB
1348 for (int rt
= 0; rt
< V3D_MAX_DRAW_BUFFERS
; rt
++)
1349 vir_emit_tlb_color_write(c
, rt
);
1353 vir_VPM_WRITE(struct v3d_compile
*c
, struct qreg val
, uint32_t vpm_index
)
1355 if (c
->devinfo
->ver
>= 40) {
1356 vir_STVPMV(c
, vir_uniform_ui(c
, vpm_index
), val
);
1358 /* XXX: v3d33_vir_vpm_write_setup(c); */
1359 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, V3D_QPU_WADDR_VPM
), val
);
1364 emit_vert_end(struct v3d_compile
*c
)
1366 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1368 if (c
->devinfo
->ver
>= 40 && c
->devinfo
->ver
<= 42)
1373 v3d_optimize_nir(struct nir_shader
*s
)
1376 unsigned lower_flrp
=
1377 (s
->options
->lower_flrp16
? 16 : 0) |
1378 (s
->options
->lower_flrp32
? 32 : 0) |
1379 (s
->options
->lower_flrp64
? 64 : 0);
1384 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1385 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
, NULL
, NULL
);
1386 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1387 NIR_PASS(progress
, s
, nir_copy_prop
);
1388 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1389 NIR_PASS(progress
, s
, nir_opt_dce
);
1390 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1391 NIR_PASS(progress
, s
, nir_opt_cse
);
1392 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8, true, true);
1393 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1394 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1396 if (lower_flrp
!= 0) {
1397 bool lower_flrp_progress
= false;
1399 NIR_PASS(lower_flrp_progress
, s
, nir_lower_flrp
,
1401 false /* always_precise */,
1402 s
->options
->lower_ffma
);
1403 if (lower_flrp_progress
) {
1404 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1408 /* Nothing should rematerialize any flrps, so we only
1409 * need to do this lowering once.
1414 NIR_PASS(progress
, s
, nir_opt_undef
);
1417 NIR_PASS(progress
, s
, nir_opt_move
, nir_move_load_ubo
);
1421 driver_location_compare(const void *in_a
, const void *in_b
)
1423 const nir_variable
*const *a
= in_a
;
1424 const nir_variable
*const *b
= in_b
;
1426 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1430 ntq_emit_vpm_read(struct v3d_compile
*c
,
1431 uint32_t *num_components_queued
,
1432 uint32_t *remaining
,
1435 struct qreg vpm
= vir_reg(QFILE_VPM
, vpm_index
);
1437 if (c
->devinfo
->ver
>= 40 ) {
1438 return vir_LDVPMV_IN(c
,
1440 (*num_components_queued
)++));
1443 if (*num_components_queued
!= 0) {
1444 (*num_components_queued
)--;
1445 return vir_MOV(c
, vpm
);
1448 uint32_t num_components
= MIN2(*remaining
, 32);
1450 v3d33_vir_vpm_read_setup(c
, num_components
);
1452 *num_components_queued
= num_components
- 1;
1453 *remaining
-= num_components
;
1455 return vir_MOV(c
, vpm
);
1459 ntq_setup_vpm_inputs(struct v3d_compile
*c
)
1461 /* Figure out how many components of each vertex attribute the shader
1462 * uses. Each variable should have been split to individual
1463 * components and unused ones DCEed. The vertex fetcher will load
1464 * from the start of the attribute to the number of components we
1465 * declare we need in c->vattr_sizes[].
1467 nir_foreach_variable(var
, &c
->s
->inputs
) {
1468 /* No VS attribute array support. */
1469 assert(MAX2(glsl_get_length(var
->type
), 1) == 1);
1471 unsigned loc
= var
->data
.driver_location
;
1472 int start_component
= var
->data
.location_frac
;
1473 int num_components
= glsl_get_components(var
->type
);
1475 c
->vattr_sizes
[loc
] = MAX2(c
->vattr_sizes
[loc
],
1476 start_component
+ num_components
);
1479 unsigned num_components
= 0;
1480 uint32_t vpm_components_queued
= 0;
1481 bool uses_iid
= c
->s
->info
.system_values_read
&
1482 (1ull << SYSTEM_VALUE_INSTANCE_ID
);
1483 bool uses_vid
= c
->s
->info
.system_values_read
&
1484 (1ull << SYSTEM_VALUE_VERTEX_ID
);
1485 num_components
+= uses_iid
;
1486 num_components
+= uses_vid
;
1488 for (int i
= 0; i
< ARRAY_SIZE(c
->vattr_sizes
); i
++)
1489 num_components
+= c
->vattr_sizes
[i
];
1492 c
->iid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1493 &num_components
, ~0);
1497 c
->vid
= ntq_emit_vpm_read(c
, &vpm_components_queued
,
1498 &num_components
, ~0);
1501 /* The actual loads will happen directly in nir_intrinsic_load_input
1502 * on newer versions.
1504 if (c
->devinfo
->ver
>= 40)
1507 for (int loc
= 0; loc
< ARRAY_SIZE(c
->vattr_sizes
); loc
++) {
1508 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1511 for (int i
= 0; i
< c
->vattr_sizes
[loc
]; i
++) {
1512 c
->inputs
[loc
* 4 + i
] =
1513 ntq_emit_vpm_read(c
,
1514 &vpm_components_queued
,
1521 if (c
->devinfo
->ver
>= 40) {
1522 assert(vpm_components_queued
== num_components
);
1524 assert(vpm_components_queued
== 0);
1525 assert(num_components
== 0);
1530 var_needs_point_coord(struct v3d_compile
*c
, nir_variable
*var
)
1532 return (var
->data
.location
== VARYING_SLOT_PNTC
||
1533 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1534 (c
->fs_key
->point_sprite_mask
&
1535 (1 << (var
->data
.location
- VARYING_SLOT_VAR0
)))));
1539 program_reads_point_coord(struct v3d_compile
*c
)
1541 nir_foreach_variable(var
, &c
->s
->inputs
) {
1542 if (var_needs_point_coord(c
, var
))
1550 ntq_setup_fs_inputs(struct v3d_compile
*c
)
1552 unsigned num_entries
= 0;
1553 unsigned num_components
= 0;
1554 nir_foreach_variable(var
, &c
->s
->inputs
) {
1556 num_components
+= glsl_get_components(var
->type
);
1559 nir_variable
*vars
[num_entries
];
1562 nir_foreach_variable(var
, &c
->s
->inputs
)
1565 /* Sort the variables so that we emit the input setup in
1566 * driver_location order. This is required for VPM reads, whose data
1567 * is fetched into the VPM in driver_location (TGSI register index)
1570 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1572 for (unsigned i
= 0; i
< num_entries
; i
++) {
1573 nir_variable
*var
= vars
[i
];
1574 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1575 unsigned loc
= var
->data
.driver_location
;
1577 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1578 (loc
+ array_len
) * 4);
1580 if (var
->data
.location
== VARYING_SLOT_POS
) {
1581 emit_fragcoord_input(c
, loc
);
1582 } else if (var_needs_point_coord(c
, var
)) {
1583 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1584 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1586 for (int j
= 0; j
< array_len
; j
++)
1587 emit_fragment_input(c
, loc
+ j
, var
, j
);
1593 ntq_setup_outputs(struct v3d_compile
*c
)
1595 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
1598 nir_foreach_variable(var
, &c
->s
->outputs
) {
1599 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1600 unsigned loc
= var
->data
.driver_location
* 4;
1602 assert(array_len
== 1);
1605 for (int i
= 0; i
< 4 - var
->data
.location_frac
; i
++) {
1606 add_output(c
, loc
+ var
->data
.location_frac
+ i
,
1608 var
->data
.location_frac
+ i
);
1611 switch (var
->data
.location
) {
1612 case FRAG_RESULT_COLOR
:
1613 c
->output_color_var
[0] = var
;
1614 c
->output_color_var
[1] = var
;
1615 c
->output_color_var
[2] = var
;
1616 c
->output_color_var
[3] = var
;
1618 case FRAG_RESULT_DATA0
:
1619 case FRAG_RESULT_DATA1
:
1620 case FRAG_RESULT_DATA2
:
1621 case FRAG_RESULT_DATA3
:
1622 c
->output_color_var
[var
->data
.location
-
1623 FRAG_RESULT_DATA0
] = var
;
1625 case FRAG_RESULT_DEPTH
:
1626 c
->output_position_index
= loc
;
1628 case FRAG_RESULT_SAMPLE_MASK
:
1629 c
->output_sample_mask_index
= loc
;
1636 * Sets up the mapping from nir_register to struct qreg *.
1638 * Each nir_register gets a struct qreg per 32-bit component being stored.
1641 ntq_setup_registers(struct v3d_compile
*c
, struct exec_list
*list
)
1643 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1644 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1645 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1647 nir_reg
->num_components
);
1649 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1651 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1652 qregs
[i
] = vir_get_temp(c
);
1657 ntq_emit_load_const(struct v3d_compile
*c
, nir_load_const_instr
*instr
)
1659 /* XXX perf: Experiment with using immediate loads to avoid having
1660 * these end up in the uniform stream. Watch out for breaking the
1661 * small immediates optimization in the process!
1663 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1664 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1665 qregs
[i
] = vir_uniform_ui(c
, instr
->value
[i
].u32
);
1667 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1671 ntq_emit_ssa_undef(struct v3d_compile
*c
, nir_ssa_undef_instr
*instr
)
1673 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1675 /* VIR needs there to be *some* value, so pick 0 (same as for
1676 * ntq_setup_registers().
1678 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1679 qregs
[i
] = vir_uniform_ui(c
, 0);
1683 ntq_emit_image_size(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1685 assert(instr
->intrinsic
== nir_intrinsic_image_deref_size
);
1686 nir_variable
*var
= nir_intrinsic_get_var(instr
, 0);
1687 unsigned image_index
= var
->data
.driver_location
;
1688 const struct glsl_type
*sampler_type
= glsl_without_array(var
->type
);
1689 bool is_array
= glsl_sampler_type_is_array(sampler_type
);
1691 ntq_store_dest(c
, &instr
->dest
, 0,
1692 vir_uniform(c
, QUNIFORM_IMAGE_WIDTH
, image_index
));
1693 if (instr
->num_components
> 1) {
1694 ntq_store_dest(c
, &instr
->dest
, 1,
1695 vir_uniform(c
, QUNIFORM_IMAGE_HEIGHT
,
1698 if (instr
->num_components
> 2) {
1699 ntq_store_dest(c
, &instr
->dest
, 2,
1702 QUNIFORM_IMAGE_ARRAY_SIZE
:
1703 QUNIFORM_IMAGE_DEPTH
,
1709 vir_emit_tlb_color_read(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1711 assert(c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
);
1713 int rt
= nir_src_as_uint(instr
->src
[0]);
1714 assert(rt
< V3D_MAX_DRAW_BUFFERS
);
1716 int sample_index
= nir_intrinsic_base(instr
) ;
1717 assert(sample_index
< V3D_MAX_SAMPLES
);
1719 int component
= nir_intrinsic_component(instr
);
1720 assert(component
< 4);
1722 /* We need to emit our TLB reads after we have acquired the scoreboard
1723 * lock, or the GPU will hang. Usually, we do our scoreboard locking on
1724 * the last thread switch to improve parallelism, however, that is only
1725 * guaranteed to happen before the tlb color writes.
1727 * To fix that, we make sure we always emit a thread switch before the
1728 * first tlb color read. If that happens to be the last thread switch
1729 * we emit, then everything is fine, but otherwsie, if any code after
1730 * this point needs to emit additional thread switches, then we will
1731 * switch the strategy to locking the scoreboard on the first thread
1732 * switch instead -- see vir_emit_thrsw().
1734 if (!c
->emitted_tlb_load
) {
1735 if (!c
->last_thrsw_at_top_level
) {
1736 assert(c
->devinfo
->ver
>= 41);
1740 c
->emitted_tlb_load
= true;
1743 struct qreg
*color_reads_for_sample
=
1744 &c
->color_reads
[(rt
* V3D_MAX_SAMPLES
+ sample_index
) * 4];
1746 if (color_reads_for_sample
[component
].file
== QFILE_NULL
) {
1747 enum pipe_format rt_format
= c
->fs_key
->color_fmt
[rt
].format
;
1748 int num_components
=
1749 util_format_get_nr_components(rt_format
);
1751 const bool swap_rb
= c
->fs_key
->swap_color_rb
& (1 << rt
);
1753 num_components
= MAX2(num_components
, 3);
1755 nir_variable
*var
= c
->output_color_var
[rt
];
1756 enum glsl_base_type type
= glsl_get_base_type(var
->type
);
1758 bool is_int_format
= type
== GLSL_TYPE_INT
||
1759 type
== GLSL_TYPE_UINT
;
1761 bool is_32b_tlb_format
= is_int_format
||
1762 (c
->fs_key
->f32_color_rb
& (1 << rt
));
1764 int num_samples
= c
->fs_key
->msaa
? V3D_MAX_SAMPLES
: 1;
1766 uint32_t conf
= 0xffffff00;
1767 conf
|= c
->fs_key
->msaa
? TLB_SAMPLE_MODE_PER_SAMPLE
:
1768 TLB_SAMPLE_MODE_PER_PIXEL
;
1769 conf
|= (7 - rt
) << TLB_RENDER_TARGET_SHIFT
;
1771 if (is_32b_tlb_format
) {
1772 /* The F32 vs I32 distinction was dropped in 4.2. */
1773 conf
|= (c
->devinfo
->ver
< 42 && is_int_format
) ?
1774 TLB_TYPE_I32_COLOR
: TLB_TYPE_F32_COLOR
;
1776 conf
|= ((num_components
- 1) <<
1777 TLB_VEC_SIZE_MINUS_1_SHIFT
);
1779 conf
|= TLB_TYPE_F16_COLOR
;
1780 conf
|= TLB_F16_SWAP_HI_LO
;
1782 if (num_components
>= 3)
1783 conf
|= TLB_VEC_SIZE_4_F16
;
1785 conf
|= TLB_VEC_SIZE_2_F16
;
1789 for (int i
= 0; i
< num_samples
; i
++) {
1790 struct qreg r
, g
, b
, a
;
1791 if (is_32b_tlb_format
) {
1792 r
= conf
!= 0xffffffff && i
== 0?
1793 vir_TLBU_COLOR_READ(c
, conf
) :
1794 vir_TLB_COLOR_READ(c
);
1795 if (num_components
>= 2)
1796 g
= vir_TLB_COLOR_READ(c
);
1797 if (num_components
>= 3)
1798 b
= vir_TLB_COLOR_READ(c
);
1799 if (num_components
>= 4)
1800 a
= vir_TLB_COLOR_READ(c
);
1802 struct qreg rg
= conf
!= 0xffffffff && i
== 0 ?
1803 vir_TLBU_COLOR_READ(c
, conf
) :
1804 vir_TLB_COLOR_READ(c
);
1805 r
= vir_FMOV(c
, rg
);
1806 vir_set_unpack(c
->defs
[r
.index
], 0,
1808 g
= vir_FMOV(c
, rg
);
1809 vir_set_unpack(c
->defs
[g
.index
], 0,
1812 if (num_components
> 2) {
1813 struct qreg ba
= vir_TLB_COLOR_READ(c
);
1814 b
= vir_FMOV(c
, ba
);
1815 vir_set_unpack(c
->defs
[b
.index
], 0,
1817 a
= vir_FMOV(c
, ba
);
1818 vir_set_unpack(c
->defs
[a
.index
], 0,
1823 struct qreg
*color_reads
=
1824 &c
->color_reads
[(rt
* V3D_MAX_SAMPLES
+ i
) * 4];
1826 color_reads
[0] = swap_rb
? b
: r
;
1827 if (num_components
>= 2)
1829 if (num_components
>= 3)
1830 color_reads
[2] = swap_rb
? r
: b
;
1831 if (num_components
>= 4)
1836 assert(color_reads_for_sample
[component
].file
!= QFILE_NULL
);
1837 ntq_store_dest(c
, &instr
->dest
, 0,
1838 vir_MOV(c
, color_reads_for_sample
[component
]));
1842 ntq_emit_load_uniform(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1844 if (nir_src_is_const(instr
->src
[0])) {
1845 int offset
= (nir_intrinsic_base(instr
) +
1846 nir_src_as_uint(instr
->src
[0]));
1847 assert(offset
% 4 == 0);
1848 /* We need dwords */
1849 offset
= offset
/ 4;
1850 for (int i
= 0; i
< instr
->num_components
; i
++) {
1851 ntq_store_dest(c
, &instr
->dest
, i
,
1852 vir_uniform(c
, QUNIFORM_UNIFORM
,
1856 ntq_emit_tmu_general(c
, instr
, false);
1861 ntq_emit_load_input(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1863 /* XXX: Use ldvpmv (uniform offset) or ldvpmd (non-uniform offset)
1864 * and enable PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR.
1867 nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[0]);
1869 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
&& c
->devinfo
->ver
>= 40) {
1870 /* Emit the LDVPM directly now, rather than at the top
1871 * of the shader like we did for V3D 3.x (which needs
1872 * vpmsetup when not just taking the next offset).
1874 * Note that delaying like this may introduce stalls,
1875 * as LDVPMV takes a minimum of 1 instruction but may
1876 * be slower if the VPM unit is busy with another QPU.
1879 if (c
->s
->info
.system_values_read
&
1880 (1ull << SYSTEM_VALUE_INSTANCE_ID
)) {
1883 if (c
->s
->info
.system_values_read
&
1884 (1ull << SYSTEM_VALUE_VERTEX_ID
)) {
1887 for (int i
= 0; i
< offset
; i
++)
1888 index
+= c
->vattr_sizes
[i
];
1889 index
+= nir_intrinsic_component(instr
);
1890 for (int i
= 0; i
< instr
->num_components
; i
++) {
1891 struct qreg vpm_offset
= vir_uniform_ui(c
, index
++);
1892 ntq_store_dest(c
, &instr
->dest
, i
,
1893 vir_LDVPMV_IN(c
, vpm_offset
));
1896 for (int i
= 0; i
< instr
->num_components
; i
++) {
1897 int comp
= nir_intrinsic_component(instr
) + i
;
1898 ntq_store_dest(c
, &instr
->dest
, i
,
1899 vir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1905 ntq_emit_per_sample_color_write(struct v3d_compile
*c
,
1906 nir_intrinsic_instr
*instr
)
1908 assert(instr
->intrinsic
== nir_intrinsic_store_tlb_sample_color_v3d
);
1910 unsigned rt
= nir_src_as_uint(instr
->src
[1]);
1911 assert(rt
< V3D_MAX_DRAW_BUFFERS
);
1913 unsigned sample_idx
= nir_intrinsic_base(instr
);
1914 assert(sample_idx
< V3D_MAX_SAMPLES
);
1916 unsigned offset
= (rt
* V3D_MAX_SAMPLES
+ sample_idx
) * 4;
1917 for (int i
= 0; i
< instr
->num_components
; i
++) {
1918 c
->sample_colors
[offset
+ i
] =
1919 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
1924 ntq_emit_color_write(struct v3d_compile
*c
,
1925 nir_intrinsic_instr
*instr
)
1927 unsigned offset
= (nir_intrinsic_base(instr
) +
1928 nir_src_as_uint(instr
->src
[1])) * 4 +
1929 nir_intrinsic_component(instr
);
1930 for (int i
= 0; i
< instr
->num_components
; i
++) {
1931 c
->outputs
[offset
+ i
] =
1932 vir_MOV(c
, ntq_get_src(c
, instr
->src
[0], i
));
1937 ntq_emit_intrinsic(struct v3d_compile
*c
, nir_intrinsic_instr
*instr
)
1939 switch (instr
->intrinsic
) {
1940 case nir_intrinsic_load_uniform
:
1941 ntq_emit_load_uniform(c
, instr
);
1944 case nir_intrinsic_load_ubo
:
1945 ntq_emit_tmu_general(c
, instr
, false);
1948 case nir_intrinsic_ssbo_atomic_add
:
1949 case nir_intrinsic_ssbo_atomic_imin
:
1950 case nir_intrinsic_ssbo_atomic_umin
:
1951 case nir_intrinsic_ssbo_atomic_imax
:
1952 case nir_intrinsic_ssbo_atomic_umax
:
1953 case nir_intrinsic_ssbo_atomic_and
:
1954 case nir_intrinsic_ssbo_atomic_or
:
1955 case nir_intrinsic_ssbo_atomic_xor
:
1956 case nir_intrinsic_ssbo_atomic_exchange
:
1957 case nir_intrinsic_ssbo_atomic_comp_swap
:
1958 case nir_intrinsic_load_ssbo
:
1959 case nir_intrinsic_store_ssbo
:
1960 ntq_emit_tmu_general(c
, instr
, false);
1963 case nir_intrinsic_shared_atomic_add
:
1964 case nir_intrinsic_shared_atomic_imin
:
1965 case nir_intrinsic_shared_atomic_umin
:
1966 case nir_intrinsic_shared_atomic_imax
:
1967 case nir_intrinsic_shared_atomic_umax
:
1968 case nir_intrinsic_shared_atomic_and
:
1969 case nir_intrinsic_shared_atomic_or
:
1970 case nir_intrinsic_shared_atomic_xor
:
1971 case nir_intrinsic_shared_atomic_exchange
:
1972 case nir_intrinsic_shared_atomic_comp_swap
:
1973 case nir_intrinsic_load_shared
:
1974 case nir_intrinsic_store_shared
:
1975 case nir_intrinsic_load_scratch
:
1976 case nir_intrinsic_store_scratch
:
1977 ntq_emit_tmu_general(c
, instr
, true);
1980 case nir_intrinsic_image_deref_load
:
1981 case nir_intrinsic_image_deref_store
:
1982 case nir_intrinsic_image_deref_atomic_add
:
1983 case nir_intrinsic_image_deref_atomic_imin
:
1984 case nir_intrinsic_image_deref_atomic_umin
:
1985 case nir_intrinsic_image_deref_atomic_imax
:
1986 case nir_intrinsic_image_deref_atomic_umax
:
1987 case nir_intrinsic_image_deref_atomic_and
:
1988 case nir_intrinsic_image_deref_atomic_or
:
1989 case nir_intrinsic_image_deref_atomic_xor
:
1990 case nir_intrinsic_image_deref_atomic_exchange
:
1991 case nir_intrinsic_image_deref_atomic_comp_swap
:
1992 v3d40_vir_emit_image_load_store(c
, instr
);
1995 case nir_intrinsic_get_buffer_size
:
1996 ntq_store_dest(c
, &instr
->dest
, 0,
1997 vir_uniform(c
, QUNIFORM_GET_BUFFER_SIZE
,
1998 nir_src_as_uint(instr
->src
[0])));
2001 case nir_intrinsic_load_user_clip_plane
:
2002 for (int i
= 0; i
< instr
->num_components
; i
++) {
2003 ntq_store_dest(c
, &instr
->dest
, i
,
2004 vir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
2005 nir_intrinsic_ucp_id(instr
) *
2010 case nir_intrinsic_load_viewport_x_scale
:
2011 ntq_store_dest(c
, &instr
->dest
, 0,
2012 vir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
, 0));
2015 case nir_intrinsic_load_viewport_y_scale
:
2016 ntq_store_dest(c
, &instr
->dest
, 0,
2017 vir_uniform(c
, QUNIFORM_VIEWPORT_Y_SCALE
, 0));
2020 case nir_intrinsic_load_viewport_z_scale
:
2021 ntq_store_dest(c
, &instr
->dest
, 0,
2022 vir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0));
2025 case nir_intrinsic_load_viewport_z_offset
:
2026 ntq_store_dest(c
, &instr
->dest
, 0,
2027 vir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0));
2030 case nir_intrinsic_load_alpha_ref_float
:
2031 ntq_store_dest(c
, &instr
->dest
, 0,
2032 vir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
2035 case nir_intrinsic_load_sample_mask_in
:
2036 ntq_store_dest(c
, &instr
->dest
, 0, vir_MSF(c
));
2039 case nir_intrinsic_load_helper_invocation
:
2040 vir_set_pf(vir_MSF_dest(c
, vir_nop_reg()), V3D_QPU_PF_PUSHZ
);
2041 ntq_store_dest(c
, &instr
->dest
, 0,
2042 vir_MOV(c
, vir_SEL(c
, V3D_QPU_COND_IFA
,
2043 vir_uniform_ui(c
, ~0),
2044 vir_uniform_ui(c
, 0))));
2047 case nir_intrinsic_load_front_face
:
2048 /* The register contains 0 (front) or 1 (back), and we need to
2049 * turn it into a NIR bool where true means front.
2051 ntq_store_dest(c
, &instr
->dest
, 0,
2053 vir_uniform_ui(c
, -1),
2057 case nir_intrinsic_load_instance_id
:
2058 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->iid
));
2061 case nir_intrinsic_load_vertex_id
:
2062 ntq_store_dest(c
, &instr
->dest
, 0, vir_MOV(c
, c
->vid
));
2065 case nir_intrinsic_load_tlb_color_v3d
:
2066 vir_emit_tlb_color_read(c
, instr
);
2069 case nir_intrinsic_load_input
:
2070 ntq_emit_load_input(c
, instr
);
2073 case nir_intrinsic_store_tlb_sample_color_v3d
:
2074 ntq_emit_per_sample_color_write(c
, instr
);
2077 case nir_intrinsic_store_output
:
2078 /* XXX perf: Use stvpmv with uniform non-constant offsets and
2079 * stvpmd with non-uniform offsets and enable
2080 * PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR.
2082 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2083 ntq_emit_color_write(c
, instr
);
2085 assert(instr
->num_components
== 1);
2088 ntq_get_src(c
, instr
->src
[0], 0),
2089 nir_intrinsic_base(instr
));
2093 case nir_intrinsic_image_deref_size
:
2094 ntq_emit_image_size(c
, instr
);
2097 case nir_intrinsic_discard
:
2098 if (vir_in_nonuniform_control_flow(c
)) {
2099 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2101 vir_set_cond(vir_SETMSF_dest(c
, vir_nop_reg(),
2102 vir_uniform_ui(c
, 0)),
2105 vir_SETMSF_dest(c
, vir_nop_reg(),
2106 vir_uniform_ui(c
, 0));
2110 case nir_intrinsic_discard_if
: {
2111 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, instr
->src
[0]);
2113 if (vir_in_nonuniform_control_flow(c
)) {
2114 struct qinst
*exec_flag
= vir_MOV_dest(c
, vir_nop_reg(),
2116 if (cond
== V3D_QPU_COND_IFA
) {
2117 vir_set_uf(exec_flag
, V3D_QPU_UF_ANDZ
);
2119 vir_set_uf(exec_flag
, V3D_QPU_UF_NORNZ
);
2120 cond
= V3D_QPU_COND_IFA
;
2124 vir_set_cond(vir_SETMSF_dest(c
, vir_nop_reg(),
2125 vir_uniform_ui(c
, 0)), cond
);
2130 case nir_intrinsic_memory_barrier
:
2131 case nir_intrinsic_memory_barrier_atomic_counter
:
2132 case nir_intrinsic_memory_barrier_buffer
:
2133 case nir_intrinsic_memory_barrier_image
:
2134 case nir_intrinsic_memory_barrier_shared
:
2135 case nir_intrinsic_group_memory_barrier
:
2136 /* We don't do any instruction scheduling of these NIR
2137 * instructions between each other, so we just need to make
2138 * sure that the TMU operations before the barrier are flushed
2139 * before the ones after the barrier. That is currently
2140 * handled by having a THRSW in each of them and a LDTMU
2141 * series or a TMUWT after.
2145 case nir_intrinsic_barrier
:
2146 /* Emit a TSY op to get all invocations in the workgroup
2147 * (actually supergroup) to block until the last invocation
2148 * reaches the TSY op.
2150 if (c
->devinfo
->ver
>= 42) {
2151 vir_BARRIERID_dest(c
, vir_reg(QFILE_MAGIC
,
2152 V3D_QPU_WADDR_SYNCB
));
2154 struct qinst
*sync
=
2155 vir_BARRIERID_dest(c
,
2156 vir_reg(QFILE_MAGIC
,
2157 V3D_QPU_WADDR_SYNCU
));
2159 vir_get_uniform_index(c
, QUNIFORM_CONSTANT
,
2161 V3D_TSY_WAIT_INC_CHECK
);
2165 /* The blocking of a TSY op only happens at the next thread
2166 * switch. No texturing may be outstanding at the time of a
2167 * TSY blocking operation.
2172 case nir_intrinsic_load_num_work_groups
:
2173 for (int i
= 0; i
< 3; i
++) {
2174 ntq_store_dest(c
, &instr
->dest
, i
,
2175 vir_uniform(c
, QUNIFORM_NUM_WORK_GROUPS
,
2180 case nir_intrinsic_load_local_invocation_index
:
2181 ntq_store_dest(c
, &instr
->dest
, 0,
2182 vir_SHR(c
, c
->cs_payload
[1],
2183 vir_uniform_ui(c
, 32 - c
->local_invocation_index_bits
)));
2186 case nir_intrinsic_load_work_group_id
:
2187 ntq_store_dest(c
, &instr
->dest
, 0,
2188 vir_AND(c
, c
->cs_payload
[0],
2189 vir_uniform_ui(c
, 0xffff)));
2190 ntq_store_dest(c
, &instr
->dest
, 1,
2191 vir_SHR(c
, c
->cs_payload
[0],
2192 vir_uniform_ui(c
, 16)));
2193 ntq_store_dest(c
, &instr
->dest
, 2,
2194 vir_AND(c
, c
->cs_payload
[1],
2195 vir_uniform_ui(c
, 0xffff)));
2198 case nir_intrinsic_load_subgroup_id
:
2199 ntq_store_dest(c
, &instr
->dest
, 0, vir_EIDX(c
));
2203 fprintf(stderr
, "Unknown intrinsic: ");
2204 nir_print_instr(&instr
->instr
, stderr
);
2205 fprintf(stderr
, "\n");
2210 /* Clears (activates) the execute flags for any channels whose jump target
2211 * matches this block.
2213 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2216 * XXX perf: For uniform control flow, we should be able to skip c->execute
2217 * handling entirely.
2220 ntq_activate_execute_for_block(struct v3d_compile
*c
)
2222 vir_set_pf(vir_XOR_dest(c
, vir_nop_reg(),
2223 c
->execute
, vir_uniform_ui(c
, c
->cur_block
->index
)),
2226 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
2230 ntq_emit_uniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
2232 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
2233 bool empty_else_block
=
2234 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
2235 exec_list_is_empty(&nir_else_block
->instr_list
));
2237 struct qblock
*then_block
= vir_new_block(c
);
2238 struct qblock
*after_block
= vir_new_block(c
);
2239 struct qblock
*else_block
;
2240 if (empty_else_block
)
2241 else_block
= after_block
;
2243 else_block
= vir_new_block(c
);
2245 /* Set up the flags for the IF condition (taking the THEN branch). */
2246 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, if_stmt
->condition
);
2249 vir_BRANCH(c
, cond
== V3D_QPU_COND_IFA
?
2250 V3D_QPU_BRANCH_COND_ALLNA
:
2251 V3D_QPU_BRANCH_COND_ALLA
);
2252 vir_link_blocks(c
->cur_block
, else_block
);
2253 vir_link_blocks(c
->cur_block
, then_block
);
2255 /* Process the THEN block. */
2256 vir_set_emit_block(c
, then_block
);
2257 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
2259 if (!empty_else_block
) {
2260 /* At the end of the THEN block, jump to ENDIF */
2261 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALWAYS
);
2262 vir_link_blocks(c
->cur_block
, after_block
);
2264 /* Emit the else block. */
2265 vir_set_emit_block(c
, else_block
);
2266 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
2269 vir_link_blocks(c
->cur_block
, after_block
);
2271 vir_set_emit_block(c
, after_block
);
2275 ntq_emit_nonuniform_if(struct v3d_compile
*c
, nir_if
*if_stmt
)
2277 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
2278 bool empty_else_block
=
2279 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
2280 exec_list_is_empty(&nir_else_block
->instr_list
));
2282 struct qblock
*then_block
= vir_new_block(c
);
2283 struct qblock
*after_block
= vir_new_block(c
);
2284 struct qblock
*else_block
;
2285 if (empty_else_block
)
2286 else_block
= after_block
;
2288 else_block
= vir_new_block(c
);
2290 bool was_uniform_control_flow
= false;
2291 if (!vir_in_nonuniform_control_flow(c
)) {
2292 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
2293 was_uniform_control_flow
= true;
2296 /* Set up the flags for the IF condition (taking the THEN branch). */
2297 enum v3d_qpu_cond cond
= ntq_emit_bool_to_cond(c
, if_stmt
->condition
);
2299 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2300 * was previously active (execute Z) for updating the exec flags.
2302 if (was_uniform_control_flow
) {
2303 cond
= v3d_qpu_cond_invert(cond
);
2305 struct qinst
*inst
= vir_MOV_dest(c
, vir_nop_reg(), c
->execute
);
2306 if (cond
== V3D_QPU_COND_IFA
) {
2307 vir_set_uf(inst
, V3D_QPU_UF_NORNZ
);
2309 vir_set_uf(inst
, V3D_QPU_UF_ANDZ
);
2310 cond
= V3D_QPU_COND_IFA
;
2314 vir_MOV_cond(c
, cond
,
2316 vir_uniform_ui(c
, else_block
->index
));
2318 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2321 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
), V3D_QPU_PF_PUSHZ
);
2322 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLNA
);
2323 vir_link_blocks(c
->cur_block
, else_block
);
2324 vir_link_blocks(c
->cur_block
, then_block
);
2326 /* Process the THEN block. */
2327 vir_set_emit_block(c
, then_block
);
2328 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
2330 if (!empty_else_block
) {
2331 /* Handle the end of the THEN block. First, all currently
2332 * active channels update their execute flags to point to
2335 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2337 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2338 vir_uniform_ui(c
, after_block
->index
));
2340 /* If everything points at ENDIF, then jump there immediately. */
2341 vir_set_pf(vir_XOR_dest(c
, vir_nop_reg(),
2343 vir_uniform_ui(c
, after_block
->index
)),
2345 vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ALLA
);
2346 vir_link_blocks(c
->cur_block
, after_block
);
2347 vir_link_blocks(c
->cur_block
, else_block
);
2349 vir_set_emit_block(c
, else_block
);
2350 ntq_activate_execute_for_block(c
);
2351 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
2354 vir_link_blocks(c
->cur_block
, after_block
);
2356 vir_set_emit_block(c
, after_block
);
2357 if (was_uniform_control_flow
)
2358 c
->execute
= c
->undef
;
2360 ntq_activate_execute_for_block(c
);
2364 ntq_emit_if(struct v3d_compile
*c
, nir_if
*nif
)
2366 bool was_in_control_flow
= c
->in_control_flow
;
2367 c
->in_control_flow
= true;
2368 if (!vir_in_nonuniform_control_flow(c
) &&
2369 nir_src_is_dynamically_uniform(nif
->condition
)) {
2370 ntq_emit_uniform_if(c
, nif
);
2372 ntq_emit_nonuniform_if(c
, nif
);
2374 c
->in_control_flow
= was_in_control_flow
;
2378 ntq_emit_jump(struct v3d_compile
*c
, nir_jump_instr
*jump
)
2380 switch (jump
->type
) {
2381 case nir_jump_break
:
2382 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2384 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2385 vir_uniform_ui(c
, c
->loop_break_block
->index
));
2388 case nir_jump_continue
:
2389 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
),
2391 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
,
2392 vir_uniform_ui(c
, c
->loop_cont_block
->index
));
2395 case nir_jump_return
:
2396 unreachable("All returns shouold be lowered\n");
2401 ntq_emit_instr(struct v3d_compile
*c
, nir_instr
*instr
)
2403 switch (instr
->type
) {
2404 case nir_instr_type_deref
:
2405 /* ignored, will be walked by the intrinsic using it. */
2408 case nir_instr_type_alu
:
2409 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
2412 case nir_instr_type_intrinsic
:
2413 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
2416 case nir_instr_type_load_const
:
2417 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
2420 case nir_instr_type_ssa_undef
:
2421 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
2424 case nir_instr_type_tex
:
2425 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
2428 case nir_instr_type_jump
:
2429 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
2433 fprintf(stderr
, "Unknown NIR instr type: ");
2434 nir_print_instr(instr
, stderr
);
2435 fprintf(stderr
, "\n");
2441 ntq_emit_block(struct v3d_compile
*c
, nir_block
*block
)
2443 nir_foreach_instr(instr
, block
) {
2444 ntq_emit_instr(c
, instr
);
2448 static void ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
);
2451 ntq_emit_loop(struct v3d_compile
*c
, nir_loop
*loop
)
2453 bool was_in_control_flow
= c
->in_control_flow
;
2454 c
->in_control_flow
= true;
2456 bool was_uniform_control_flow
= false;
2457 if (!vir_in_nonuniform_control_flow(c
)) {
2458 c
->execute
= vir_MOV(c
, vir_uniform_ui(c
, 0));
2459 was_uniform_control_flow
= true;
2462 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
2463 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
2465 c
->loop_cont_block
= vir_new_block(c
);
2466 c
->loop_break_block
= vir_new_block(c
);
2468 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2469 vir_set_emit_block(c
, c
->loop_cont_block
);
2470 ntq_activate_execute_for_block(c
);
2472 ntq_emit_cf_list(c
, &loop
->body
);
2474 /* Re-enable any previous continues now, so our ANYA check below
2477 * XXX: Use the .ORZ flags update, instead.
2479 vir_set_pf(vir_XOR_dest(c
,
2482 vir_uniform_ui(c
, c
->loop_cont_block
->index
)),
2484 vir_MOV_cond(c
, V3D_QPU_COND_IFA
, c
->execute
, vir_uniform_ui(c
, 0));
2486 vir_set_pf(vir_MOV_dest(c
, vir_nop_reg(), c
->execute
), V3D_QPU_PF_PUSHZ
);
2488 struct qinst
*branch
= vir_BRANCH(c
, V3D_QPU_BRANCH_COND_ANYA
);
2489 /* Pixels that were not dispatched or have been discarded should not
2490 * contribute to looping again.
2492 branch
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_P
;
2493 vir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2494 vir_link_blocks(c
->cur_block
, c
->loop_break_block
);
2496 vir_set_emit_block(c
, c
->loop_break_block
);
2497 if (was_uniform_control_flow
)
2498 c
->execute
= c
->undef
;
2500 ntq_activate_execute_for_block(c
);
2502 c
->loop_break_block
= save_loop_break_block
;
2503 c
->loop_cont_block
= save_loop_cont_block
;
2507 c
->in_control_flow
= was_in_control_flow
;
2511 ntq_emit_function(struct v3d_compile
*c
, nir_function_impl
*func
)
2513 fprintf(stderr
, "FUNCTIONS not handled.\n");
2518 ntq_emit_cf_list(struct v3d_compile
*c
, struct exec_list
*list
)
2520 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2521 switch (node
->type
) {
2522 case nir_cf_node_block
:
2523 ntq_emit_block(c
, nir_cf_node_as_block(node
));
2526 case nir_cf_node_if
:
2527 ntq_emit_if(c
, nir_cf_node_as_if(node
));
2530 case nir_cf_node_loop
:
2531 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
2534 case nir_cf_node_function
:
2535 ntq_emit_function(c
, nir_cf_node_as_function(node
));
2539 fprintf(stderr
, "Unknown NIR node type\n");
2546 ntq_emit_impl(struct v3d_compile
*c
, nir_function_impl
*impl
)
2548 ntq_setup_registers(c
, &impl
->registers
);
2549 ntq_emit_cf_list(c
, &impl
->body
);
2553 nir_to_vir(struct v3d_compile
*c
)
2555 switch (c
->s
->info
.stage
) {
2556 case MESA_SHADER_FRAGMENT
:
2557 c
->payload_w
= vir_MOV(c
, vir_reg(QFILE_REG
, 0));
2558 c
->payload_w_centroid
= vir_MOV(c
, vir_reg(QFILE_REG
, 1));
2559 c
->payload_z
= vir_MOV(c
, vir_reg(QFILE_REG
, 2));
2561 /* V3D 4.x can disable implicit point coordinate varyings if
2562 * they are not used.
2564 if (c
->fs_key
->is_points
&&
2565 (c
->devinfo
->ver
< 40 || program_reads_point_coord(c
))) {
2566 c
->point_x
= emit_fragment_varying(c
, NULL
, 0, 0);
2567 c
->point_y
= emit_fragment_varying(c
, NULL
, 0, 0);
2568 c
->uses_implicit_point_line_varyings
= true;
2569 } else if (c
->fs_key
->is_lines
&& c
->devinfo
->ver
< 40) {
2570 c
->line_x
= emit_fragment_varying(c
, NULL
, 0, 0);
2571 c
->uses_implicit_point_line_varyings
= true;
2574 case MESA_SHADER_COMPUTE
:
2575 /* Set up the TSO for barriers, assuming we do some. */
2576 if (c
->devinfo
->ver
< 42) {
2577 vir_BARRIERID_dest(c
, vir_reg(QFILE_MAGIC
,
2578 V3D_QPU_WADDR_SYNC
));
2581 c
->cs_payload
[0] = vir_MOV(c
, vir_reg(QFILE_REG
, 0));
2582 c
->cs_payload
[1] = vir_MOV(c
, vir_reg(QFILE_REG
, 2));
2584 /* Set up the division between gl_LocalInvocationIndex and
2585 * wg_in_mem in the payload reg.
2587 int wg_size
= (c
->s
->info
.cs
.local_size
[0] *
2588 c
->s
->info
.cs
.local_size
[1] *
2589 c
->s
->info
.cs
.local_size
[2]);
2590 c
->local_invocation_index_bits
=
2591 ffs(util_next_power_of_two(MAX2(wg_size
, 64))) - 1;
2592 assert(c
->local_invocation_index_bits
<= 8);
2594 if (c
->s
->info
.cs
.shared_size
) {
2595 struct qreg wg_in_mem
= vir_SHR(c
, c
->cs_payload
[1],
2596 vir_uniform_ui(c
, 16));
2597 if (c
->s
->info
.cs
.local_size
[0] != 1 ||
2598 c
->s
->info
.cs
.local_size
[1] != 1 ||
2599 c
->s
->info
.cs
.local_size
[2] != 1) {
2601 c
->local_invocation_index_bits
);
2602 int wg_mask
= (1 << wg_bits
) - 1;
2603 wg_in_mem
= vir_AND(c
, wg_in_mem
,
2604 vir_uniform_ui(c
, wg_mask
));
2606 struct qreg shared_per_wg
=
2607 vir_uniform_ui(c
, c
->s
->info
.cs
.shared_size
);
2609 c
->cs_shared_offset
=
2611 vir_uniform(c
, QUNIFORM_SHARED_OFFSET
,0),
2612 vir_UMUL(c
, wg_in_mem
, shared_per_wg
));
2619 if (c
->s
->scratch_size
) {
2620 v3d_setup_spill_base(c
);
2621 c
->spill_size
+= V3D_CHANNELS
* c
->s
->scratch_size
;
2624 if (c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
)
2625 ntq_setup_fs_inputs(c
);
2627 ntq_setup_vpm_inputs(c
);
2629 ntq_setup_outputs(c
);
2631 /* Find the main function and emit the body. */
2632 nir_foreach_function(function
, c
->s
) {
2633 assert(strcmp(function
->name
, "main") == 0);
2634 assert(function
->impl
);
2635 ntq_emit_impl(c
, function
->impl
);
2639 const nir_shader_compiler_options v3d_nir_options
= {
2640 .lower_all_io_to_temps
= true,
2641 .lower_extract_byte
= true,
2642 .lower_extract_word
= true,
2643 .lower_bitfield_insert_to_shifts
= true,
2644 .lower_bitfield_extract_to_shifts
= true,
2645 .lower_bitfield_reverse
= true,
2646 .lower_bit_count
= true,
2647 .lower_cs_local_id_from_index
= true,
2648 .lower_ffract
= true,
2650 .lower_pack_unorm_2x16
= true,
2651 .lower_pack_snorm_2x16
= true,
2652 .lower_pack_unorm_4x8
= true,
2653 .lower_pack_snorm_4x8
= true,
2654 .lower_unpack_unorm_4x8
= true,
2655 .lower_unpack_snorm_4x8
= true,
2656 .lower_pack_half_2x16
= true,
2657 .lower_unpack_half_2x16
= true,
2659 .lower_find_lsb
= true,
2661 .lower_flrp32
= true,
2664 .lower_fsqrt
= true,
2665 .lower_ifind_msb
= true,
2666 .lower_isign
= true,
2667 .lower_ldexp
= true,
2668 .lower_mul_high
= true,
2669 .lower_wpos_pntc
= true,
2670 .lower_rotate
= true,
2674 * When demoting a shader down to single-threaded, removes the THRSW
2675 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2679 vir_remove_thrsw(struct v3d_compile
*c
)
2681 vir_for_each_block(block
, c
) {
2682 vir_for_each_inst_safe(inst
, block
) {
2683 if (inst
->qpu
.sig
.thrsw
)
2684 vir_remove_instruction(c
, inst
);
2688 c
->last_thrsw
= NULL
;
2692 vir_emit_last_thrsw(struct v3d_compile
*c
)
2694 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2695 * switching, so disable threads if we didn't do any TMU ops (each of
2696 * which would have emitted a THRSW).
2698 if (!c
->last_thrsw_at_top_level
&& c
->devinfo
->ver
< 41) {
2701 vir_remove_thrsw(c
);
2705 /* If we're threaded and the last THRSW was in conditional code, then
2706 * we need to emit another one so that we can flag it as the last
2709 if (c
->last_thrsw
&& !c
->last_thrsw_at_top_level
) {
2710 assert(c
->devinfo
->ver
>= 41);
2714 /* If we're threaded, then we need to mark the last THRSW instruction
2715 * so we can emit a pair of them at QPU emit time.
2717 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2718 * post-last-THRSW state, so we can skip this.
2720 if (!c
->last_thrsw
&& c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2721 assert(c
->devinfo
->ver
>= 41);
2726 c
->last_thrsw
->is_last_thrsw
= true;
2729 /* There's a flag in the shader for "center W is needed for reasons other than
2730 * non-centroid varyings", so we just walk the program after VIR optimization
2731 * to see if it's used. It should be harmless to set even if we only use
2732 * center W for varyings.
2735 vir_check_payload_w(struct v3d_compile
*c
)
2737 if (c
->s
->info
.stage
!= MESA_SHADER_FRAGMENT
)
2740 vir_for_each_inst_inorder(inst
, c
) {
2741 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
2742 if (inst
->src
[i
].file
== QFILE_REG
&&
2743 inst
->src
[i
].index
== 0) {
2744 c
->uses_center_w
= true;
2753 v3d_nir_to_vir(struct v3d_compile
*c
)
2755 if (V3D_DEBUG
& (V3D_DEBUG_NIR
|
2756 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2757 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2758 vir_get_stage_name(c
),
2759 c
->program_id
, c
->variant_id
);
2760 nir_print_shader(c
->s
, stderr
);
2765 /* Emit the last THRSW before STVPM and TLB writes. */
2766 vir_emit_last_thrsw(c
);
2768 switch (c
->s
->info
.stage
) {
2769 case MESA_SHADER_FRAGMENT
:
2772 case MESA_SHADER_VERTEX
:
2775 case MESA_SHADER_COMPUTE
:
2778 unreachable("bad stage");
2781 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2782 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2783 fprintf(stderr
, "%s prog %d/%d pre-opt VIR:\n",
2784 vir_get_stage_name(c
),
2785 c
->program_id
, c
->variant_id
);
2787 fprintf(stderr
, "\n");
2792 vir_check_payload_w(c
);
2794 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2795 * We used that on that platform to pipeline TMU writes and reduce the
2796 * number of thread switches, as well as try (mostly successfully) to
2797 * reduce maximum register pressure to allow more threads. We should
2798 * do something of that sort for V3D -- either instruction scheduling
2799 * here, or delay the the THRSW and LDTMUs from our texture
2800 * instructions until the results are needed.
2803 if (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2804 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
))) {
2805 fprintf(stderr
, "%s prog %d/%d VIR:\n",
2806 vir_get_stage_name(c
),
2807 c
->program_id
, c
->variant_id
);
2809 fprintf(stderr
, "\n");
2812 /* Attempt to allocate registers for the temporaries. If we fail,
2813 * reduce thread count and try again.
2815 int min_threads
= (c
->devinfo
->ver
>= 41) ? 2 : 1;
2816 struct qpu_reg
*temp_registers
;
2819 temp_registers
= v3d_register_allocate(c
, &spilled
);
2826 if (c
->threads
== min_threads
) {
2827 fprintf(stderr
, "Failed to register allocate at %d threads:\n",
2836 if (c
->threads
== 1)
2837 vir_remove_thrsw(c
);
2841 (V3D_DEBUG
& (V3D_DEBUG_VIR
|
2842 v3d_debug_flag_for_shader_stage(c
->s
->info
.stage
)))) {
2843 fprintf(stderr
, "%s prog %d/%d spilled VIR:\n",
2844 vir_get_stage_name(c
),
2845 c
->program_id
, c
->variant_id
);
2847 fprintf(stderr
, "\n");
2850 v3d_vir_to_qpu(c
, temp_registers
);