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v3d: Fix vir_is_raw_mov() for input unpacks.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "common/v3d_device_info.h"
33 #include "v3d_compiler.h"
34
35 #define GENERAL_TMU_LOOKUP_PER_QUAD (0 << 7)
36 #define GENERAL_TMU_LOOKUP_PER_PIXEL (1 << 7)
37 #define GENERAL_TMU_READ_OP_PREFETCH (0 << 3)
38 #define GENERAL_TMU_READ_OP_CACHE_CLEAR (1 << 3)
39 #define GENERAL_TMU_READ_OP_CACHE_FLUSH (3 << 3)
40 #define GENERAL_TMU_READ_OP_CACHE_CLEAN (3 << 3)
41 #define GENERAL_TMU_READ_OP_CACHE_L1T_CLEAR (4 << 3)
42 #define GENERAL_TMU_READ_OP_CACHE_L1T_FLUSH_AGGREGATION (5 << 3)
43 #define GENERAL_TMU_READ_OP_ATOMIC_INC (8 << 3)
44 #define GENERAL_TMU_READ_OP_ATOMIC_DEC (9 << 3)
45 #define GENERAL_TMU_READ_OP_ATOMIC_NOT (10 << 3)
46 #define GENERAL_TMU_READ_OP_READ (15 << 3)
47 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_I (0 << 0)
48 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_I (1 << 0)
49 #define GENERAL_TMU_LOOKUP_TYPE_VEC2 (2 << 0)
50 #define GENERAL_TMU_LOOKUP_TYPE_VEC3 (3 << 0)
51 #define GENERAL_TMU_LOOKUP_TYPE_VEC4 (4 << 0)
52 #define GENERAL_TMU_LOOKUP_TYPE_8BIT_UI (5 << 0)
53 #define GENERAL_TMU_LOOKUP_TYPE_16BIT_UI (6 << 0)
54 #define GENERAL_TMU_LOOKUP_TYPE_32BIT_UI (7 << 0)
55
56 #define GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP (0 << 3)
57 #define GENERAL_TMU_WRITE_OP_ATOMIC_SUB_WRAP (1 << 3)
58 #define GENERAL_TMU_WRITE_OP_ATOMIC_XCHG (2 << 3)
59 #define GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG (3 << 3)
60 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMIN (4 << 3)
61 #define GENERAL_TMU_WRITE_OP_ATOMIC_UMAX (5 << 3)
62 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMIN (6 << 3)
63 #define GENERAL_TMU_WRITE_OP_ATOMIC_SMAX (7 << 3)
64 #define GENERAL_TMU_WRITE_OP_ATOMIC_AND (8 << 3)
65 #define GENERAL_TMU_WRITE_OP_ATOMIC_OR (9 << 3)
66 #define GENERAL_TMU_WRITE_OP_ATOMIC_XOR (10 << 3)
67 #define GENERAL_TMU_WRITE_OP_WRITE (15 << 3)
68
69 #define V3D_TSY_SET_QUORUM 0
70 #define V3D_TSY_INC_WAITERS 1
71 #define V3D_TSY_DEC_WAITERS 2
72 #define V3D_TSY_INC_QUORUM 3
73 #define V3D_TSY_DEC_QUORUM 4
74 #define V3D_TSY_FREE_ALL 5
75 #define V3D_TSY_RELEASE 6
76 #define V3D_TSY_ACQUIRE 7
77 #define V3D_TSY_WAIT 8
78 #define V3D_TSY_WAIT_INC 9
79 #define V3D_TSY_WAIT_CHECK 10
80 #define V3D_TSY_WAIT_INC_CHECK 11
81 #define V3D_TSY_WAIT_CV 12
82 #define V3D_TSY_INC_SEMAPHORE 13
83 #define V3D_TSY_DEC_SEMAPHORE 14
84 #define V3D_TSY_SET_QUORUM_FREE_ALL 15
85
86 static void
87 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
88
89 static void
90 resize_qreg_array(struct v3d_compile *c,
91 struct qreg **regs,
92 uint32_t *size,
93 uint32_t decl_size)
94 {
95 if (*size >= decl_size)
96 return;
97
98 uint32_t old_size = *size;
99 *size = MAX2(*size * 2, decl_size);
100 *regs = reralloc(c, *regs, struct qreg, *size);
101 if (!*regs) {
102 fprintf(stderr, "Malloc failure\n");
103 abort();
104 }
105
106 for (uint32_t i = old_size; i < *size; i++)
107 (*regs)[i] = c->undef;
108 }
109
110 void
111 vir_emit_thrsw(struct v3d_compile *c)
112 {
113 if (c->threads == 1)
114 return;
115
116 /* Always thread switch after each texture operation for now.
117 *
118 * We could do better by batching a bunch of texture fetches up and
119 * then doing one thread switch and collecting all their results
120 * afterward.
121 */
122 c->last_thrsw = vir_NOP(c);
123 c->last_thrsw->qpu.sig.thrsw = true;
124 c->last_thrsw_at_top_level = !c->in_control_flow;
125 }
126
127 static uint32_t
128 v3d_general_tmu_op(nir_intrinsic_instr *instr)
129 {
130 switch (instr->intrinsic) {
131 case nir_intrinsic_load_ssbo:
132 case nir_intrinsic_load_ubo:
133 case nir_intrinsic_load_uniform:
134 case nir_intrinsic_load_shared:
135 return GENERAL_TMU_READ_OP_READ;
136 case nir_intrinsic_store_ssbo:
137 case nir_intrinsic_store_shared:
138 return GENERAL_TMU_WRITE_OP_WRITE;
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_shared_atomic_add:
141 return GENERAL_TMU_WRITE_OP_ATOMIC_ADD_WRAP;
142 case nir_intrinsic_ssbo_atomic_imin:
143 case nir_intrinsic_shared_atomic_imin:
144 return GENERAL_TMU_WRITE_OP_ATOMIC_SMIN;
145 case nir_intrinsic_ssbo_atomic_umin:
146 case nir_intrinsic_shared_atomic_umin:
147 return GENERAL_TMU_WRITE_OP_ATOMIC_UMIN;
148 case nir_intrinsic_ssbo_atomic_imax:
149 case nir_intrinsic_shared_atomic_imax:
150 return GENERAL_TMU_WRITE_OP_ATOMIC_SMAX;
151 case nir_intrinsic_ssbo_atomic_umax:
152 case nir_intrinsic_shared_atomic_umax:
153 return GENERAL_TMU_WRITE_OP_ATOMIC_UMAX;
154 case nir_intrinsic_ssbo_atomic_and:
155 case nir_intrinsic_shared_atomic_and:
156 return GENERAL_TMU_WRITE_OP_ATOMIC_AND;
157 case nir_intrinsic_ssbo_atomic_or:
158 case nir_intrinsic_shared_atomic_or:
159 return GENERAL_TMU_WRITE_OP_ATOMIC_OR;
160 case nir_intrinsic_ssbo_atomic_xor:
161 case nir_intrinsic_shared_atomic_xor:
162 return GENERAL_TMU_WRITE_OP_ATOMIC_XOR;
163 case nir_intrinsic_ssbo_atomic_exchange:
164 case nir_intrinsic_shared_atomic_exchange:
165 return GENERAL_TMU_WRITE_OP_ATOMIC_XCHG;
166 case nir_intrinsic_ssbo_atomic_comp_swap:
167 case nir_intrinsic_shared_atomic_comp_swap:
168 return GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG;
169 default:
170 unreachable("unknown intrinsic op");
171 }
172 }
173
174 /**
175 * Implements indirect uniform loads and SSBO accesses through the TMU general
176 * memory access interface.
177 */
178 static void
179 ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
180 bool is_shared)
181 {
182 /* XXX perf: We should turn add/sub of 1 to inc/dec. Perhaps NIR
183 * wants to have support for inc/dec?
184 */
185
186 uint32_t tmu_op = v3d_general_tmu_op(instr);
187 bool is_store = (instr->intrinsic == nir_intrinsic_store_ssbo ||
188 instr->intrinsic == nir_intrinsic_store_shared);
189 bool has_index = !is_shared;
190
191 int offset_src;
192 int tmu_writes = 1; /* address */
193 if (instr->intrinsic == nir_intrinsic_load_uniform) {
194 offset_src = 0;
195 } else if (instr->intrinsic == nir_intrinsic_load_ssbo ||
196 instr->intrinsic == nir_intrinsic_load_ubo ||
197 instr->intrinsic == nir_intrinsic_load_shared) {
198 offset_src = 0 + has_index;
199 } else if (is_store) {
200 offset_src = 1 + has_index;
201 for (int i = 0; i < instr->num_components; i++) {
202 vir_MOV_dest(c,
203 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
204 ntq_get_src(c, instr->src[0], i));
205 tmu_writes++;
206 }
207 } else {
208 offset_src = 0 + has_index;
209 vir_MOV_dest(c,
210 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
211 ntq_get_src(c, instr->src[1 + has_index], 0));
212 tmu_writes++;
213 if (tmu_op == GENERAL_TMU_WRITE_OP_ATOMIC_CMPXCHG) {
214 vir_MOV_dest(c,
215 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUD),
216 ntq_get_src(c, instr->src[2 + has_index],
217 0));
218 tmu_writes++;
219 }
220 }
221
222 /* Make sure we won't exceed the 16-entry TMU fifo if each thread is
223 * storing at the same time.
224 */
225 while (tmu_writes > 16 / c->threads)
226 c->threads /= 2;
227
228 struct qreg offset;
229 if (instr->intrinsic == nir_intrinsic_load_uniform) {
230 offset = vir_uniform(c, QUNIFORM_UBO_ADDR, 0);
231
232 /* Find what variable in the default uniform block this
233 * uniform load is coming from.
234 */
235 uint32_t base = nir_intrinsic_base(instr);
236 int i;
237 struct v3d_ubo_range *range = NULL;
238 for (i = 0; i < c->num_ubo_ranges; i++) {
239 range = &c->ubo_ranges[i];
240 if (base >= range->src_offset &&
241 base < range->src_offset + range->size) {
242 break;
243 }
244 }
245 /* The driver-location-based offset always has to be within a
246 * declared uniform range.
247 */
248 assert(i != c->num_ubo_ranges);
249 if (!c->ubo_range_used[i]) {
250 c->ubo_range_used[i] = true;
251 range->dst_offset = c->next_ubo_dst_offset;
252 c->next_ubo_dst_offset += range->size;
253 }
254
255 base = base - range->src_offset + range->dst_offset;
256
257 if (base != 0)
258 offset = vir_ADD(c, offset, vir_uniform_ui(c, base));
259 } else if (instr->intrinsic == nir_intrinsic_load_ubo) {
260 /* Note that QUNIFORM_UBO_ADDR takes a UBO index shifted up by
261 * 1 (0 is gallium's constant buffer 0).
262 */
263 offset = vir_uniform(c, QUNIFORM_UBO_ADDR,
264 nir_src_as_uint(instr->src[0]) + 1);
265 } else if (is_shared) {
266 /* Shared variables have no buffer index, and all start from a
267 * common base that we set up at the start of dispatch
268 */
269 offset = c->cs_shared_offset;
270 } else {
271 offset = vir_uniform(c, QUNIFORM_SSBO_OFFSET,
272 nir_src_as_uint(instr->src[is_store ?
273 1 : 0]));
274 }
275
276 uint32_t config = (0xffffff00 |
277 tmu_op |
278 GENERAL_TMU_LOOKUP_PER_PIXEL);
279 if (instr->num_components == 1) {
280 config |= GENERAL_TMU_LOOKUP_TYPE_32BIT_UI;
281 } else {
282 config |= (GENERAL_TMU_LOOKUP_TYPE_VEC2 +
283 instr->num_components - 2);
284 }
285
286 if (vir_in_nonuniform_control_flow(c)) {
287 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
288 V3D_QPU_PF_PUSHZ);
289 }
290
291 struct qreg dest;
292 if (config == ~0)
293 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA);
294 else
295 dest = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUAU);
296
297 struct qinst *tmu;
298 if (nir_src_is_const(instr->src[offset_src]) &&
299 nir_src_as_uint(instr->src[offset_src]) == 0) {
300 tmu = vir_MOV_dest(c, dest, offset);
301 } else {
302 tmu = vir_ADD_dest(c, dest,
303 offset,
304 ntq_get_src(c, instr->src[offset_src], 0));
305 }
306
307 if (config != ~0) {
308 tmu->src[vir_get_implicit_uniform_src(tmu)] =
309 vir_uniform_ui(c, config);
310 }
311
312 if (vir_in_nonuniform_control_flow(c))
313 vir_set_cond(tmu, V3D_QPU_COND_IFA);
314
315 vir_emit_thrsw(c);
316
317 /* Read the result, or wait for the TMU op to complete. */
318 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++)
319 ntq_store_dest(c, &instr->dest, i, vir_MOV(c, vir_LDTMU(c)));
320
321 if (nir_intrinsic_dest_components(instr) == 0)
322 vir_TMUWT(c);
323 }
324
325 static struct qreg *
326 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
327 {
328 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
329 def->num_components);
330 _mesa_hash_table_insert(c->def_ht, def, qregs);
331 return qregs;
332 }
333
334 /**
335 * This function is responsible for getting VIR results into the associated
336 * storage for a NIR instruction.
337 *
338 * If it's a NIR SSA def, then we just set the associated hash table entry to
339 * the new result.
340 *
341 * If it's a NIR reg, then we need to update the existing qreg assigned to the
342 * NIR destination with the incoming value. To do that without introducing
343 * new MOVs, we require that the incoming qreg either be a uniform, or be
344 * SSA-defined by the previous VIR instruction in the block and rewritable by
345 * this function. That lets us sneak ahead and insert the SF flag beforehand
346 * (knowing that the previous instruction doesn't depend on flags) and rewrite
347 * its destination to be the NIR reg's destination
348 */
349 void
350 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
351 struct qreg result)
352 {
353 struct qinst *last_inst = NULL;
354 if (!list_empty(&c->cur_block->instructions))
355 last_inst = (struct qinst *)c->cur_block->instructions.prev;
356
357 assert(result.file == QFILE_UNIF ||
358 (result.file == QFILE_TEMP &&
359 last_inst && last_inst == c->defs[result.index]));
360
361 if (dest->is_ssa) {
362 assert(chan < dest->ssa.num_components);
363
364 struct qreg *qregs;
365 struct hash_entry *entry =
366 _mesa_hash_table_search(c->def_ht, &dest->ssa);
367
368 if (entry)
369 qregs = entry->data;
370 else
371 qregs = ntq_init_ssa_def(c, &dest->ssa);
372
373 qregs[chan] = result;
374 } else {
375 nir_register *reg = dest->reg.reg;
376 assert(dest->reg.base_offset == 0);
377 assert(reg->num_array_elems == 0);
378 struct hash_entry *entry =
379 _mesa_hash_table_search(c->def_ht, reg);
380 struct qreg *qregs = entry->data;
381
382 /* Insert a MOV if the source wasn't an SSA def in the
383 * previous instruction.
384 */
385 if (result.file == QFILE_UNIF) {
386 result = vir_MOV(c, result);
387 last_inst = c->defs[result.index];
388 }
389
390 /* We know they're both temps, so just rewrite index. */
391 c->defs[last_inst->dst.index] = NULL;
392 last_inst->dst.index = qregs[chan].index;
393
394 /* If we're in control flow, then make this update of the reg
395 * conditional on the execution mask.
396 */
397 if (vir_in_nonuniform_control_flow(c)) {
398 last_inst->dst.index = qregs[chan].index;
399
400 /* Set the flags to the current exec mask.
401 */
402 c->cursor = vir_before_inst(last_inst);
403 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
404 V3D_QPU_PF_PUSHZ);
405 c->cursor = vir_after_inst(last_inst);
406
407 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
408 last_inst->cond_is_exec_mask = true;
409 }
410 }
411 }
412
413 struct qreg
414 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
415 {
416 struct hash_entry *entry;
417 if (src.is_ssa) {
418 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
419 assert(i < src.ssa->num_components);
420 } else {
421 nir_register *reg = src.reg.reg;
422 entry = _mesa_hash_table_search(c->def_ht, reg);
423 assert(reg->num_array_elems == 0);
424 assert(src.reg.base_offset == 0);
425 assert(i < reg->num_components);
426 }
427
428 struct qreg *qregs = entry->data;
429 return qregs[i];
430 }
431
432 static struct qreg
433 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
434 unsigned src)
435 {
436 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
437 unsigned chan = ffs(instr->dest.write_mask) - 1;
438 struct qreg r = ntq_get_src(c, instr->src[src].src,
439 instr->src[src].swizzle[chan]);
440
441 assert(!instr->src[src].abs);
442 assert(!instr->src[src].negate);
443
444 return r;
445 };
446
447 static struct qreg
448 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
449 {
450 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
451 }
452
453 static void
454 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
455 {
456 unsigned unit = instr->texture_index;
457 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
458 int dest_size = nir_tex_instr_dest_size(instr);
459
460 struct qreg lod = c->undef;
461 if (lod_index != -1)
462 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
463
464 for (int i = 0; i < dest_size; i++) {
465 assert(i < 3);
466 enum quniform_contents contents;
467
468 if (instr->is_array && i == dest_size - 1)
469 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
470 else
471 contents = QUNIFORM_TEXTURE_WIDTH + i;
472
473 struct qreg size = vir_uniform(c, contents, unit);
474
475 switch (instr->sampler_dim) {
476 case GLSL_SAMPLER_DIM_1D:
477 case GLSL_SAMPLER_DIM_2D:
478 case GLSL_SAMPLER_DIM_MS:
479 case GLSL_SAMPLER_DIM_3D:
480 case GLSL_SAMPLER_DIM_CUBE:
481 /* Don't minify the array size. */
482 if (!(instr->is_array && i == dest_size - 1)) {
483 size = ntq_minify(c, size, lod);
484 }
485 break;
486
487 case GLSL_SAMPLER_DIM_RECT:
488 /* There's no LOD field for rects */
489 break;
490
491 default:
492 unreachable("Bad sampler type");
493 }
494
495 ntq_store_dest(c, &instr->dest, i, size);
496 }
497 }
498
499 static void
500 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
501 {
502 unsigned unit = instr->texture_index;
503
504 /* Since each texture sampling op requires uploading uniforms to
505 * reference the texture, there's no HW support for texture size and
506 * you just upload uniforms containing the size.
507 */
508 switch (instr->op) {
509 case nir_texop_query_levels:
510 ntq_store_dest(c, &instr->dest, 0,
511 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
512 return;
513 case nir_texop_txs:
514 ntq_emit_txs(c, instr);
515 return;
516 default:
517 break;
518 }
519
520 if (c->devinfo->ver >= 40)
521 v3d40_vir_emit_tex(c, instr);
522 else
523 v3d33_vir_emit_tex(c, instr);
524 }
525
526 static struct qreg
527 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
528 {
529 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
530 if (is_cos)
531 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
532
533 struct qreg periods = vir_FROUND(c, input);
534 struct qreg sin_output = vir_SIN(c, vir_FSUB(c, input, periods));
535 return vir_XOR(c, sin_output, vir_SHL(c,
536 vir_FTOIN(c, periods),
537 vir_uniform_ui(c, -1)));
538 }
539
540 static struct qreg
541 ntq_fsign(struct v3d_compile *c, struct qreg src)
542 {
543 struct qreg t = vir_get_temp(c);
544
545 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
546 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHZ);
547 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
548 vir_set_pf(vir_FMOV_dest(c, vir_nop_reg(), src), V3D_QPU_PF_PUSHN);
549 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
550 return vir_MOV(c, t);
551 }
552
553 static void
554 emit_fragcoord_input(struct v3d_compile *c, int attr)
555 {
556 c->inputs[attr * 4 + 0] = vir_FXCD(c);
557 c->inputs[attr * 4 + 1] = vir_FYCD(c);
558 c->inputs[attr * 4 + 2] = c->payload_z;
559 c->inputs[attr * 4 + 3] = vir_RECIP(c, c->payload_w);
560 }
561
562 static struct qreg
563 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
564 uint8_t swizzle, int array_index)
565 {
566 struct qreg r3 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R3);
567 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
568
569 struct qreg vary;
570 if (c->devinfo->ver >= 41) {
571 struct qinst *ldvary = vir_add_inst(V3D_QPU_A_NOP, c->undef,
572 c->undef, c->undef);
573 ldvary->qpu.sig.ldvary = true;
574 vary = vir_emit_def(c, ldvary);
575 } else {
576 vir_NOP(c)->qpu.sig.ldvary = true;
577 vary = r3;
578 }
579
580 /* For gl_PointCoord input or distance along a line, we'll be called
581 * with no nir_variable, and we don't count toward VPM size so we
582 * don't track an input slot.
583 */
584 if (!var) {
585 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
586 }
587
588 int i = c->num_inputs++;
589 c->input_slots[i] =
590 v3d_slot_from_slot_and_component(var->data.location +
591 array_index, swizzle);
592
593 switch (var->data.interpolation) {
594 case INTERP_MODE_NONE:
595 /* If a gl_FrontColor or gl_BackColor input has no interp
596 * qualifier, then if we're using glShadeModel(GL_FLAT) it
597 * needs to be flat shaded.
598 */
599 switch (var->data.location + array_index) {
600 case VARYING_SLOT_COL0:
601 case VARYING_SLOT_COL1:
602 case VARYING_SLOT_BFC0:
603 case VARYING_SLOT_BFC1:
604 if (c->fs_key->shade_model_flat) {
605 BITSET_SET(c->flat_shade_flags, i);
606 vir_MOV_dest(c, c->undef, vary);
607 return vir_MOV(c, r5);
608 } else {
609 return vir_FADD(c, vir_FMUL(c, vary,
610 c->payload_w), r5);
611 }
612 default:
613 break;
614 }
615 /* FALLTHROUGH */
616 case INTERP_MODE_SMOOTH:
617 if (var->data.centroid) {
618 BITSET_SET(c->centroid_flags, i);
619 return vir_FADD(c, vir_FMUL(c, vary,
620 c->payload_w_centroid), r5);
621 } else {
622 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
623 }
624 case INTERP_MODE_NOPERSPECTIVE:
625 BITSET_SET(c->noperspective_flags, i);
626 return vir_FADD(c, vir_MOV(c, vary), r5);
627 case INTERP_MODE_FLAT:
628 BITSET_SET(c->flat_shade_flags, i);
629 vir_MOV_dest(c, c->undef, vary);
630 return vir_MOV(c, r5);
631 default:
632 unreachable("Bad interp mode");
633 }
634 }
635
636 static void
637 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var,
638 int array_index)
639 {
640 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
641 int chan = var->data.location_frac + i;
642 c->inputs[attr * 4 + chan] =
643 emit_fragment_varying(c, var, chan, array_index);
644 }
645 }
646
647 static void
648 add_output(struct v3d_compile *c,
649 uint32_t decl_offset,
650 uint8_t slot,
651 uint8_t swizzle)
652 {
653 uint32_t old_array_size = c->outputs_array_size;
654 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
655 decl_offset + 1);
656
657 if (old_array_size != c->outputs_array_size) {
658 c->output_slots = reralloc(c,
659 c->output_slots,
660 struct v3d_varying_slot,
661 c->outputs_array_size);
662 }
663
664 c->output_slots[decl_offset] =
665 v3d_slot_from_slot_and_component(slot, swizzle);
666 }
667
668 static void
669 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
670 {
671 unsigned array_id = c->num_ubo_ranges++;
672 if (array_id >= c->ubo_ranges_array_size) {
673 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
674 array_id + 1);
675 c->ubo_ranges = reralloc(c, c->ubo_ranges,
676 struct v3d_ubo_range,
677 c->ubo_ranges_array_size);
678 c->ubo_range_used = reralloc(c, c->ubo_range_used,
679 bool,
680 c->ubo_ranges_array_size);
681 }
682
683 c->ubo_ranges[array_id].dst_offset = 0;
684 c->ubo_ranges[array_id].src_offset = start;
685 c->ubo_ranges[array_id].size = size;
686 c->ubo_range_used[array_id] = false;
687 }
688
689 /**
690 * If compare_instr is a valid comparison instruction, emits the
691 * compare_instr's comparison and returns the sel_instr's return value based
692 * on the compare_instr's result.
693 */
694 static bool
695 ntq_emit_comparison(struct v3d_compile *c,
696 nir_alu_instr *compare_instr,
697 enum v3d_qpu_cond *out_cond)
698 {
699 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
700 struct qreg src1;
701 if (nir_op_infos[compare_instr->op].num_inputs > 1)
702 src1 = ntq_get_alu_src(c, compare_instr, 1);
703 bool cond_invert = false;
704 struct qreg nop = vir_nop_reg();
705
706 switch (compare_instr->op) {
707 case nir_op_feq32:
708 case nir_op_seq:
709 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
710 break;
711 case nir_op_ieq32:
712 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
713 break;
714
715 case nir_op_fne32:
716 case nir_op_sne:
717 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
718 cond_invert = true;
719 break;
720 case nir_op_ine32:
721 vir_set_pf(vir_XOR_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHZ);
722 cond_invert = true;
723 break;
724
725 case nir_op_fge32:
726 case nir_op_sge:
727 vir_set_pf(vir_FCMP_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
728 break;
729 case nir_op_ige32:
730 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
731 cond_invert = true;
732 break;
733 case nir_op_uge32:
734 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
735 cond_invert = true;
736 break;
737
738 case nir_op_slt:
739 case nir_op_flt32:
740 vir_set_pf(vir_FCMP_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHN);
741 break;
742 case nir_op_ilt32:
743 vir_set_pf(vir_MIN_dest(c, nop, src1, src0), V3D_QPU_PF_PUSHC);
744 break;
745 case nir_op_ult32:
746 vir_set_pf(vir_SUB_dest(c, nop, src0, src1), V3D_QPU_PF_PUSHC);
747 break;
748
749 case nir_op_i2b32:
750 vir_set_pf(vir_MOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
751 cond_invert = true;
752 break;
753
754 case nir_op_f2b32:
755 vir_set_pf(vir_FMOV_dest(c, nop, src0), V3D_QPU_PF_PUSHZ);
756 cond_invert = true;
757 break;
758
759 default:
760 return false;
761 }
762
763 *out_cond = cond_invert ? V3D_QPU_COND_IFNA : V3D_QPU_COND_IFA;
764
765 return true;
766 }
767
768 /* Finds an ALU instruction that generates our src value that could
769 * (potentially) be greedily emitted in the consuming instruction.
770 */
771 static struct nir_alu_instr *
772 ntq_get_alu_parent(nir_src src)
773 {
774 if (!src.is_ssa || src.ssa->parent_instr->type != nir_instr_type_alu)
775 return NULL;
776 nir_alu_instr *instr = nir_instr_as_alu(src.ssa->parent_instr);
777 if (!instr)
778 return NULL;
779
780 /* If the ALU instr's srcs are non-SSA, then we would have to avoid
781 * moving emission of the ALU instr down past another write of the
782 * src.
783 */
784 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
785 if (!instr->src[i].src.is_ssa)
786 return NULL;
787 }
788
789 return instr;
790 }
791
792 /* Turns a NIR bool into a condition code to predicate on. */
793 static enum v3d_qpu_cond
794 ntq_emit_bool_to_cond(struct v3d_compile *c, nir_src src)
795 {
796 nir_alu_instr *compare = ntq_get_alu_parent(src);
797 if (!compare)
798 goto out;
799
800 enum v3d_qpu_cond cond;
801 if (ntq_emit_comparison(c, compare, &cond))
802 return cond;
803
804 out:
805 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), ntq_get_src(c, src, 0)),
806 V3D_QPU_PF_PUSHZ);
807 return V3D_QPU_COND_IFNA;
808 }
809
810 static void
811 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
812 {
813 /* This should always be lowered to ALU operations for V3D. */
814 assert(!instr->dest.saturate);
815
816 /* Vectors are special in that they have non-scalarized writemasks,
817 * and just take the first swizzle channel for each argument in order
818 * into each writemask channel.
819 */
820 if (instr->op == nir_op_vec2 ||
821 instr->op == nir_op_vec3 ||
822 instr->op == nir_op_vec4) {
823 struct qreg srcs[4];
824 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
825 srcs[i] = ntq_get_src(c, instr->src[i].src,
826 instr->src[i].swizzle[0]);
827 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
828 ntq_store_dest(c, &instr->dest.dest, i,
829 vir_MOV(c, srcs[i]));
830 return;
831 }
832
833 /* General case: We can just grab the one used channel per src. */
834 struct qreg src[nir_op_infos[instr->op].num_inputs];
835 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
836 src[i] = ntq_get_alu_src(c, instr, i);
837 }
838
839 struct qreg result;
840
841 switch (instr->op) {
842 case nir_op_fmov:
843 case nir_op_imov:
844 result = vir_MOV(c, src[0]);
845 break;
846
847 case nir_op_fneg:
848 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
849 break;
850 case nir_op_ineg:
851 result = vir_NEG(c, src[0]);
852 break;
853
854 case nir_op_fmul:
855 result = vir_FMUL(c, src[0], src[1]);
856 break;
857 case nir_op_fadd:
858 result = vir_FADD(c, src[0], src[1]);
859 break;
860 case nir_op_fsub:
861 result = vir_FSUB(c, src[0], src[1]);
862 break;
863 case nir_op_fmin:
864 result = vir_FMIN(c, src[0], src[1]);
865 break;
866 case nir_op_fmax:
867 result = vir_FMAX(c, src[0], src[1]);
868 break;
869
870 case nir_op_f2i32:
871 result = vir_FTOIZ(c, src[0]);
872 break;
873 case nir_op_f2u32:
874 result = vir_FTOUZ(c, src[0]);
875 break;
876 case nir_op_i2f32:
877 result = vir_ITOF(c, src[0]);
878 break;
879 case nir_op_u2f32:
880 result = vir_UTOF(c, src[0]);
881 break;
882 case nir_op_b2f32:
883 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
884 break;
885 case nir_op_b2i32:
886 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
887 break;
888
889 case nir_op_iadd:
890 result = vir_ADD(c, src[0], src[1]);
891 break;
892 case nir_op_ushr:
893 result = vir_SHR(c, src[0], src[1]);
894 break;
895 case nir_op_isub:
896 result = vir_SUB(c, src[0], src[1]);
897 break;
898 case nir_op_ishr:
899 result = vir_ASR(c, src[0], src[1]);
900 break;
901 case nir_op_ishl:
902 result = vir_SHL(c, src[0], src[1]);
903 break;
904 case nir_op_imin:
905 result = vir_MIN(c, src[0], src[1]);
906 break;
907 case nir_op_umin:
908 result = vir_UMIN(c, src[0], src[1]);
909 break;
910 case nir_op_imax:
911 result = vir_MAX(c, src[0], src[1]);
912 break;
913 case nir_op_umax:
914 result = vir_UMAX(c, src[0], src[1]);
915 break;
916 case nir_op_iand:
917 result = vir_AND(c, src[0], src[1]);
918 break;
919 case nir_op_ior:
920 result = vir_OR(c, src[0], src[1]);
921 break;
922 case nir_op_ixor:
923 result = vir_XOR(c, src[0], src[1]);
924 break;
925 case nir_op_inot:
926 result = vir_NOT(c, src[0]);
927 break;
928
929 case nir_op_ufind_msb:
930 result = vir_SUB(c, vir_uniform_ui(c, 31), vir_CLZ(c, src[0]));
931 break;
932
933 case nir_op_imul:
934 result = vir_UMUL(c, src[0], src[1]);
935 break;
936
937 case nir_op_seq:
938 case nir_op_sne:
939 case nir_op_sge:
940 case nir_op_slt: {
941 enum v3d_qpu_cond cond;
942 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
943 assert(ok);
944 result = vir_MOV(c, vir_SEL(c, cond,
945 vir_uniform_f(c, 1.0),
946 vir_uniform_f(c, 0.0)));
947 break;
948 }
949
950 case nir_op_i2b32:
951 case nir_op_f2b32:
952 case nir_op_feq32:
953 case nir_op_fne32:
954 case nir_op_fge32:
955 case nir_op_flt32:
956 case nir_op_ieq32:
957 case nir_op_ine32:
958 case nir_op_ige32:
959 case nir_op_uge32:
960 case nir_op_ilt32:
961 case nir_op_ult32: {
962 enum v3d_qpu_cond cond;
963 MAYBE_UNUSED bool ok = ntq_emit_comparison(c, instr, &cond);
964 assert(ok);
965 result = vir_MOV(c, vir_SEL(c, cond,
966 vir_uniform_ui(c, ~0),
967 vir_uniform_ui(c, 0)));
968 break;
969 }
970
971 case nir_op_b32csel:
972 result = vir_MOV(c,
973 vir_SEL(c,
974 ntq_emit_bool_to_cond(c, instr->src[0].src),
975 src[1], src[2]));
976 break;
977
978 case nir_op_fcsel:
979 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), src[0]),
980 V3D_QPU_PF_PUSHZ);
981 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
982 src[1], src[2]));
983 break;
984
985 case nir_op_frcp:
986 result = vir_RECIP(c, src[0]);
987 break;
988 case nir_op_frsq:
989 result = vir_RSQRT(c, src[0]);
990 break;
991 case nir_op_fexp2:
992 result = vir_EXP(c, src[0]);
993 break;
994 case nir_op_flog2:
995 result = vir_LOG(c, src[0]);
996 break;
997
998 case nir_op_fceil:
999 result = vir_FCEIL(c, src[0]);
1000 break;
1001 case nir_op_ffloor:
1002 result = vir_FFLOOR(c, src[0]);
1003 break;
1004 case nir_op_fround_even:
1005 result = vir_FROUND(c, src[0]);
1006 break;
1007 case nir_op_ftrunc:
1008 result = vir_FTRUNC(c, src[0]);
1009 break;
1010
1011 case nir_op_fsin:
1012 result = ntq_fsincos(c, src[0], false);
1013 break;
1014 case nir_op_fcos:
1015 result = ntq_fsincos(c, src[0], true);
1016 break;
1017
1018 case nir_op_fsign:
1019 result = ntq_fsign(c, src[0]);
1020 break;
1021
1022 case nir_op_fabs: {
1023 result = vir_FMOV(c, src[0]);
1024 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
1025 break;
1026 }
1027
1028 case nir_op_iabs:
1029 result = vir_MAX(c, src[0], vir_NEG(c, src[0]));
1030 break;
1031
1032 case nir_op_fddx:
1033 case nir_op_fddx_coarse:
1034 case nir_op_fddx_fine:
1035 result = vir_FDX(c, src[0]);
1036 break;
1037
1038 case nir_op_fddy:
1039 case nir_op_fddy_coarse:
1040 case nir_op_fddy_fine:
1041 result = vir_FDY(c, src[0]);
1042 break;
1043
1044 case nir_op_uadd_carry:
1045 vir_set_pf(vir_ADD_dest(c, vir_nop_reg(), src[0], src[1]),
1046 V3D_QPU_PF_PUSHC);
1047 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1048 vir_uniform_ui(c, ~0),
1049 vir_uniform_ui(c, 0)));
1050 break;
1051
1052 case nir_op_pack_half_2x16_split:
1053 result = vir_VFPACK(c, src[0], src[1]);
1054 break;
1055
1056 case nir_op_unpack_half_2x16_split_x:
1057 result = vir_FMOV(c, src[0]);
1058 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_L);
1059 break;
1060
1061 case nir_op_unpack_half_2x16_split_y:
1062 result = vir_FMOV(c, src[0]);
1063 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_H);
1064 break;
1065
1066 default:
1067 fprintf(stderr, "unknown NIR ALU inst: ");
1068 nir_print_instr(&instr->instr, stderr);
1069 fprintf(stderr, "\n");
1070 abort();
1071 }
1072
1073 /* We have a scalar result, so the instruction should only have a
1074 * single channel written to.
1075 */
1076 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1077 ntq_store_dest(c, &instr->dest.dest,
1078 ffs(instr->dest.write_mask) - 1, result);
1079 }
1080
1081 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1082 * specifier. They come from a register that's preloaded with 0xffffffff
1083 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1084 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1085 */
1086 #define TLB_TYPE_F16_COLOR (3 << 6)
1087 #define TLB_TYPE_I32_COLOR (1 << 6)
1088 #define TLB_TYPE_F32_COLOR (0 << 6)
1089 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1090 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1091 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1092 #define TLB_F16_SWAP_HI_LO (1 << 1)
1093 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1094 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1095 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1096
1097 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1098 * flag is set.
1099 */
1100 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1101 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1102 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1103 #define TLB_V42_DEPTH_TYPE_INVARIANT (0 << 3) /* Unmodified sideband input used */
1104 #define TLB_V42_DEPTH_TYPE_PER_PIXEL (1 << 3) /* QPU result used */
1105
1106 /* Stencil is a single 32-bit write. */
1107 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1108
1109 static void
1110 emit_frag_end(struct v3d_compile *c)
1111 {
1112 /* XXX
1113 if (c->output_sample_mask_index != -1) {
1114 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1115 }
1116 */
1117
1118 bool has_any_tlb_color_write = false;
1119 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1120 if (c->fs_key->cbufs & (1 << rt) && c->output_color_var[rt])
1121 has_any_tlb_color_write = true;
1122 }
1123
1124 if (c->fs_key->sample_alpha_to_coverage && c->output_color_var[0]) {
1125 struct nir_variable *var = c->output_color_var[0];
1126 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1127
1128 vir_SETMSF_dest(c, vir_nop_reg(),
1129 vir_AND(c,
1130 vir_MSF(c),
1131 vir_FTOC(c, color[3])));
1132 }
1133
1134 if (c->output_position_index != -1) {
1135 struct qinst *inst = vir_MOV_dest(c,
1136 vir_reg(QFILE_TLBU, 0),
1137 c->outputs[c->output_position_index]);
1138 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1139
1140 if (c->devinfo->ver >= 42) {
1141 tlb_specifier |= (TLB_V42_DEPTH_TYPE_PER_PIXEL |
1142 TLB_SAMPLE_MODE_PER_PIXEL);
1143 } else
1144 tlb_specifier |= TLB_DEPTH_TYPE_PER_PIXEL;
1145
1146 inst->src[vir_get_implicit_uniform_src(inst)] =
1147 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1148 c->writes_z = true;
1149 } else if (c->s->info.fs.uses_discard ||
1150 !c->s->info.fs.early_fragment_tests ||
1151 c->fs_key->sample_alpha_to_coverage ||
1152 !has_any_tlb_color_write) {
1153 /* Emit passthrough Z if it needed to be delayed until shader
1154 * end due to potential discards.
1155 *
1156 * Since (single-threaded) fragment shaders always need a TLB
1157 * write, emit passthrouh Z if we didn't have any color
1158 * buffers and flag us as potentially discarding, so that we
1159 * can use Z as the TLB write.
1160 */
1161 c->s->info.fs.uses_discard = true;
1162
1163 struct qinst *inst = vir_MOV_dest(c,
1164 vir_reg(QFILE_TLBU, 0),
1165 vir_nop_reg());
1166 uint8_t tlb_specifier = TLB_TYPE_DEPTH;
1167
1168 if (c->devinfo->ver >= 42) {
1169 /* The spec says the PER_PIXEL flag is ignored for
1170 * invariant writes, but the simulator demands it.
1171 */
1172 tlb_specifier |= (TLB_V42_DEPTH_TYPE_INVARIANT |
1173 TLB_SAMPLE_MODE_PER_PIXEL);
1174 } else {
1175 tlb_specifier |= TLB_DEPTH_TYPE_INVARIANT;
1176 }
1177
1178 inst->src[vir_get_implicit_uniform_src(inst)] =
1179 vir_uniform_ui(c, tlb_specifier | 0xffffff00);
1180 c->writes_z = true;
1181 }
1182
1183 /* XXX: Performance improvement: Merge Z write and color writes TLB
1184 * uniform setup
1185 */
1186
1187 for (int rt = 0; rt < V3D_MAX_DRAW_BUFFERS; rt++) {
1188 if (!(c->fs_key->cbufs & (1 << rt)) || !c->output_color_var[rt])
1189 continue;
1190
1191 nir_variable *var = c->output_color_var[rt];
1192 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1193 int num_components = glsl_get_vector_elements(var->type);
1194 uint32_t conf = 0xffffff00;
1195 struct qinst *inst;
1196
1197 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1198 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1199
1200 if (c->fs_key->swap_color_rb & (1 << rt))
1201 num_components = MAX2(num_components, 3);
1202
1203 assert(num_components != 0);
1204 switch (glsl_get_base_type(var->type)) {
1205 case GLSL_TYPE_UINT:
1206 case GLSL_TYPE_INT:
1207 /* The F32 vs I32 distinction was dropped in 4.2. */
1208 if (c->devinfo->ver < 42)
1209 conf |= TLB_TYPE_I32_COLOR;
1210 else
1211 conf |= TLB_TYPE_F32_COLOR;
1212 conf |= ((num_components - 1) <<
1213 TLB_VEC_SIZE_MINUS_1_SHIFT);
1214
1215 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1216 inst->src[vir_get_implicit_uniform_src(inst)] =
1217 vir_uniform_ui(c, conf);
1218
1219 for (int i = 1; i < num_components; i++) {
1220 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1221 color[i]);
1222 }
1223 break;
1224
1225 default: {
1226 struct qreg r = color[0];
1227 struct qreg g = color[1];
1228 struct qreg b = color[2];
1229 struct qreg a = color[3];
1230
1231 if (c->fs_key->f32_color_rb & (1 << rt)) {
1232 conf |= TLB_TYPE_F32_COLOR;
1233 conf |= ((num_components - 1) <<
1234 TLB_VEC_SIZE_MINUS_1_SHIFT);
1235 } else {
1236 conf |= TLB_TYPE_F16_COLOR;
1237 conf |= TLB_F16_SWAP_HI_LO;
1238 if (num_components >= 3)
1239 conf |= TLB_VEC_SIZE_4_F16;
1240 else
1241 conf |= TLB_VEC_SIZE_2_F16;
1242 }
1243
1244 if (c->fs_key->swap_color_rb & (1 << rt)) {
1245 r = color[2];
1246 b = color[0];
1247 }
1248
1249 if (c->fs_key->sample_alpha_to_one)
1250 a = vir_uniform_f(c, 1.0);
1251
1252 if (c->fs_key->f32_color_rb & (1 << rt)) {
1253 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), r);
1254 inst->src[vir_get_implicit_uniform_src(inst)] =
1255 vir_uniform_ui(c, conf);
1256
1257 if (num_components >= 2)
1258 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), g);
1259 if (num_components >= 3)
1260 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), b);
1261 if (num_components >= 4)
1262 vir_MOV_dest(c, vir_reg(QFILE_TLB, 0), a);
1263 } else {
1264 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1265 if (conf != ~0) {
1266 inst->dst.file = QFILE_TLBU;
1267 inst->src[vir_get_implicit_uniform_src(inst)] =
1268 vir_uniform_ui(c, conf);
1269 }
1270
1271 if (num_components >= 3)
1272 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1273 }
1274 break;
1275 }
1276 }
1277 }
1278 }
1279
1280 static void
1281 vir_VPM_WRITE(struct v3d_compile *c, struct qreg val, uint32_t *vpm_index)
1282 {
1283 if (c->devinfo->ver >= 40) {
1284 vir_STVPMV(c, vir_uniform_ui(c, *vpm_index), val);
1285 *vpm_index = *vpm_index + 1;
1286 } else {
1287 vir_MOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM), val);
1288 }
1289
1290 c->num_vpm_writes++;
1291 }
1292
1293 static void
1294 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w,
1295 uint32_t *vpm_index)
1296 {
1297 for (int i = 0; i < 2; i++) {
1298 struct qreg coord = c->outputs[c->output_position_index + i];
1299 coord = vir_FMUL(c, coord,
1300 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1301 0));
1302 coord = vir_FMUL(c, coord, rcp_w);
1303 vir_VPM_WRITE(c, vir_FTOIN(c, coord), vpm_index);
1304 }
1305
1306 }
1307
1308 static void
1309 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1310 {
1311 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1312 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1313
1314 struct qreg z = c->outputs[c->output_position_index + 2];
1315 z = vir_FMUL(c, z, zscale);
1316 z = vir_FMUL(c, z, rcp_w);
1317 z = vir_FADD(c, z, zoffset);
1318 vir_VPM_WRITE(c, z, vpm_index);
1319 }
1320
1321 static void
1322 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w, uint32_t *vpm_index)
1323 {
1324 vir_VPM_WRITE(c, rcp_w, vpm_index);
1325 }
1326
1327 static void
1328 emit_point_size_write(struct v3d_compile *c, uint32_t *vpm_index)
1329 {
1330 struct qreg point_size;
1331
1332 if (c->output_point_size_index != -1)
1333 point_size = c->outputs[c->output_point_size_index];
1334 else
1335 point_size = vir_uniform_f(c, 1.0);
1336
1337 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1338 * BCM21553).
1339 */
1340 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1341
1342 vir_VPM_WRITE(c, point_size, vpm_index);
1343 }
1344
1345 static void
1346 emit_vpm_write_setup(struct v3d_compile *c)
1347 {
1348 if (c->devinfo->ver >= 40)
1349 return;
1350
1351 v3d33_vir_vpm_write_setup(c);
1352 }
1353
1354 /**
1355 * Sets up c->outputs[c->output_position_index] for the vertex shader
1356 * epilogue, if an output vertex position wasn't specified in the user's
1357 * shader. This may be the case for transform feedback with rasterizer
1358 * discard enabled.
1359 */
1360 static void
1361 setup_default_position(struct v3d_compile *c)
1362 {
1363 if (c->output_position_index != -1)
1364 return;
1365
1366 c->output_position_index = c->outputs_array_size;
1367 for (int i = 0; i < 4; i++) {
1368 add_output(c,
1369 c->output_position_index + i,
1370 VARYING_SLOT_POS, i);
1371 }
1372 }
1373
1374 static void
1375 emit_vert_end(struct v3d_compile *c)
1376 {
1377 setup_default_position(c);
1378
1379 uint32_t vpm_index = 0;
1380 struct qreg rcp_w = vir_RECIP(c,
1381 c->outputs[c->output_position_index + 3]);
1382
1383 emit_vpm_write_setup(c);
1384
1385 if (c->vs_key->is_coord) {
1386 for (int i = 0; i < 4; i++)
1387 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i],
1388 &vpm_index);
1389 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1390 if (c->vs_key->per_vertex_point_size) {
1391 emit_point_size_write(c, &vpm_index);
1392 /* emit_rcp_wc_write(c, rcp_w); */
1393 }
1394 /* XXX: Z-only rendering */
1395 if (0)
1396 emit_zs_write(c, rcp_w, &vpm_index);
1397 } else {
1398 emit_scaled_viewport_write(c, rcp_w, &vpm_index);
1399 emit_zs_write(c, rcp_w, &vpm_index);
1400 emit_rcp_wc_write(c, rcp_w, &vpm_index);
1401 if (c->vs_key->per_vertex_point_size)
1402 emit_point_size_write(c, &vpm_index);
1403 }
1404
1405 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1406 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1407 int j;
1408
1409 for (j = 0; j < c->num_outputs; j++) {
1410 struct v3d_varying_slot output = c->output_slots[j];
1411
1412 if (!memcmp(&input, &output, sizeof(input))) {
1413 vir_VPM_WRITE(c, c->outputs[j],
1414 &vpm_index);
1415 break;
1416 }
1417 }
1418 /* Emit padding if we didn't find a declared VS output for
1419 * this FS input.
1420 */
1421 if (j == c->num_outputs)
1422 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0),
1423 &vpm_index);
1424 }
1425
1426 /* GFXH-1684: VPM writes need to be complete by the end of the shader.
1427 */
1428 if (c->devinfo->ver >= 40 && c->devinfo->ver <= 42)
1429 vir_VPMWT(c);
1430 }
1431
1432 void
1433 v3d_optimize_nir(struct nir_shader *s)
1434 {
1435 bool progress;
1436
1437 do {
1438 progress = false;
1439
1440 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1441 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1442 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1443 NIR_PASS(progress, s, nir_copy_prop);
1444 NIR_PASS(progress, s, nir_opt_remove_phis);
1445 NIR_PASS(progress, s, nir_opt_dce);
1446 NIR_PASS(progress, s, nir_opt_dead_cf);
1447 NIR_PASS(progress, s, nir_opt_cse);
1448 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1449 NIR_PASS(progress, s, nir_opt_algebraic);
1450 NIR_PASS(progress, s, nir_opt_constant_folding);
1451 NIR_PASS(progress, s, nir_opt_undef);
1452 } while (progress);
1453
1454 NIR_PASS(progress, s, nir_opt_move_load_ubo);
1455 }
1456
1457 static int
1458 driver_location_compare(const void *in_a, const void *in_b)
1459 {
1460 const nir_variable *const *a = in_a;
1461 const nir_variable *const *b = in_b;
1462
1463 return (*a)->data.driver_location - (*b)->data.driver_location;
1464 }
1465
1466 static struct qreg
1467 ntq_emit_vpm_read(struct v3d_compile *c,
1468 uint32_t *num_components_queued,
1469 uint32_t *remaining,
1470 uint32_t vpm_index)
1471 {
1472 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1473
1474 if (c->devinfo->ver >= 40 ) {
1475 return vir_LDVPMV_IN(c,
1476 vir_uniform_ui(c,
1477 (*num_components_queued)++));
1478 }
1479
1480 if (*num_components_queued != 0) {
1481 (*num_components_queued)--;
1482 return vir_MOV(c, vpm);
1483 }
1484
1485 uint32_t num_components = MIN2(*remaining, 32);
1486
1487 v3d33_vir_vpm_read_setup(c, num_components);
1488
1489 *num_components_queued = num_components - 1;
1490 *remaining -= num_components;
1491
1492 return vir_MOV(c, vpm);
1493 }
1494
1495 static void
1496 ntq_setup_vpm_inputs(struct v3d_compile *c)
1497 {
1498 /* Figure out how many components of each vertex attribute the shader
1499 * uses. Each variable should have been split to individual
1500 * components and unused ones DCEed. The vertex fetcher will load
1501 * from the start of the attribute to the number of components we
1502 * declare we need in c->vattr_sizes[].
1503 */
1504 nir_foreach_variable(var, &c->s->inputs) {
1505 /* No VS attribute array support. */
1506 assert(MAX2(glsl_get_length(var->type), 1) == 1);
1507
1508 unsigned loc = var->data.driver_location;
1509 int start_component = var->data.location_frac;
1510 int num_components = glsl_get_components(var->type);
1511
1512 c->vattr_sizes[loc] = MAX2(c->vattr_sizes[loc],
1513 start_component + num_components);
1514 }
1515
1516 unsigned num_components = 0;
1517 uint32_t vpm_components_queued = 0;
1518 bool uses_iid = c->s->info.system_values_read &
1519 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1520 bool uses_vid = c->s->info.system_values_read &
1521 (1ull << SYSTEM_VALUE_VERTEX_ID);
1522 num_components += uses_iid;
1523 num_components += uses_vid;
1524
1525 for (int i = 0; i < ARRAY_SIZE(c->vattr_sizes); i++)
1526 num_components += c->vattr_sizes[i];
1527
1528 if (uses_iid) {
1529 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1530 &num_components, ~0);
1531 }
1532
1533 if (uses_vid) {
1534 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1535 &num_components, ~0);
1536 }
1537
1538 /* The actual loads will happen directly in nir_intrinsic_load_input
1539 * on newer versions.
1540 */
1541 if (c->devinfo->ver >= 40)
1542 return;
1543
1544 for (int loc = 0; loc < ARRAY_SIZE(c->vattr_sizes); loc++) {
1545 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1546 (loc + 1) * 4);
1547
1548 for (int i = 0; i < c->vattr_sizes[loc]; i++) {
1549 c->inputs[loc * 4 + i] =
1550 ntq_emit_vpm_read(c,
1551 &vpm_components_queued,
1552 &num_components,
1553 loc * 4 + i);
1554
1555 }
1556 }
1557
1558 if (c->devinfo->ver >= 40) {
1559 assert(vpm_components_queued == num_components);
1560 } else {
1561 assert(vpm_components_queued == 0);
1562 assert(num_components == 0);
1563 }
1564 }
1565
1566 static void
1567 ntq_setup_fs_inputs(struct v3d_compile *c)
1568 {
1569 unsigned num_entries = 0;
1570 unsigned num_components = 0;
1571 nir_foreach_variable(var, &c->s->inputs) {
1572 num_entries++;
1573 num_components += glsl_get_components(var->type);
1574 }
1575
1576 nir_variable *vars[num_entries];
1577
1578 unsigned i = 0;
1579 nir_foreach_variable(var, &c->s->inputs)
1580 vars[i++] = var;
1581
1582 /* Sort the variables so that we emit the input setup in
1583 * driver_location order. This is required for VPM reads, whose data
1584 * is fetched into the VPM in driver_location (TGSI register index)
1585 * order.
1586 */
1587 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1588
1589 for (unsigned i = 0; i < num_entries; i++) {
1590 nir_variable *var = vars[i];
1591 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1592 unsigned loc = var->data.driver_location;
1593
1594 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1595 (loc + array_len) * 4);
1596
1597 if (var->data.location == VARYING_SLOT_POS) {
1598 emit_fragcoord_input(c, loc);
1599 } else if (var->data.location == VARYING_SLOT_PNTC ||
1600 (var->data.location >= VARYING_SLOT_VAR0 &&
1601 (c->fs_key->point_sprite_mask &
1602 (1 << (var->data.location -
1603 VARYING_SLOT_VAR0))))) {
1604 c->inputs[loc * 4 + 0] = c->point_x;
1605 c->inputs[loc * 4 + 1] = c->point_y;
1606 } else {
1607 for (int j = 0; j < array_len; j++)
1608 emit_fragment_input(c, loc + j, var, j);
1609 }
1610 }
1611 }
1612
1613 static void
1614 ntq_setup_outputs(struct v3d_compile *c)
1615 {
1616 nir_foreach_variable(var, &c->s->outputs) {
1617 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1618 unsigned loc = var->data.driver_location * 4;
1619
1620 assert(array_len == 1);
1621 (void)array_len;
1622
1623 for (int i = 0; i < 4 - var->data.location_frac; i++) {
1624 add_output(c, loc + var->data.location_frac + i,
1625 var->data.location,
1626 var->data.location_frac + i);
1627 }
1628
1629 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1630 switch (var->data.location) {
1631 case FRAG_RESULT_COLOR:
1632 c->output_color_var[0] = var;
1633 c->output_color_var[1] = var;
1634 c->output_color_var[2] = var;
1635 c->output_color_var[3] = var;
1636 break;
1637 case FRAG_RESULT_DATA0:
1638 case FRAG_RESULT_DATA1:
1639 case FRAG_RESULT_DATA2:
1640 case FRAG_RESULT_DATA3:
1641 c->output_color_var[var->data.location -
1642 FRAG_RESULT_DATA0] = var;
1643 break;
1644 case FRAG_RESULT_DEPTH:
1645 c->output_position_index = loc;
1646 break;
1647 case FRAG_RESULT_SAMPLE_MASK:
1648 c->output_sample_mask_index = loc;
1649 break;
1650 }
1651 } else {
1652 switch (var->data.location) {
1653 case VARYING_SLOT_POS:
1654 c->output_position_index = loc;
1655 break;
1656 case VARYING_SLOT_PSIZ:
1657 c->output_point_size_index = loc;
1658 break;
1659 }
1660 }
1661 }
1662 }
1663
1664 static void
1665 ntq_setup_uniforms(struct v3d_compile *c)
1666 {
1667 nir_foreach_variable(var, &c->s->uniforms) {
1668 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1669 false);
1670 unsigned vec4_size = 4 * sizeof(float);
1671
1672 if (var->data.mode != nir_var_uniform)
1673 continue;
1674
1675 declare_uniform_range(c, var->data.driver_location * vec4_size,
1676 vec4_count * vec4_size);
1677
1678 }
1679 }
1680
1681 /**
1682 * Sets up the mapping from nir_register to struct qreg *.
1683 *
1684 * Each nir_register gets a struct qreg per 32-bit component being stored.
1685 */
1686 static void
1687 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1688 {
1689 foreach_list_typed(nir_register, nir_reg, node, list) {
1690 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1691 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1692 array_len *
1693 nir_reg->num_components);
1694
1695 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1696
1697 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1698 qregs[i] = vir_get_temp(c);
1699 }
1700 }
1701
1702 static void
1703 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1704 {
1705 /* XXX perf: Experiment with using immediate loads to avoid having
1706 * these end up in the uniform stream. Watch out for breaking the
1707 * small immediates optimization in the process!
1708 */
1709 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1710 for (int i = 0; i < instr->def.num_components; i++)
1711 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1712
1713 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1714 }
1715
1716 static void
1717 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1718 {
1719 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1720
1721 /* VIR needs there to be *some* value, so pick 0 (same as for
1722 * ntq_setup_registers().
1723 */
1724 for (int i = 0; i < instr->def.num_components; i++)
1725 qregs[i] = vir_uniform_ui(c, 0);
1726 }
1727
1728 static void
1729 ntq_emit_image_size(struct v3d_compile *c, nir_intrinsic_instr *instr)
1730 {
1731 assert(instr->intrinsic == nir_intrinsic_image_deref_size);
1732 nir_variable *var = nir_intrinsic_get_var(instr, 0);
1733 unsigned image_index = var->data.driver_location;
1734 const struct glsl_type *sampler_type = glsl_without_array(var->type);
1735 bool is_array = glsl_sampler_type_is_array(sampler_type);
1736
1737 ntq_store_dest(c, &instr->dest, 0,
1738 vir_uniform(c, QUNIFORM_IMAGE_WIDTH, image_index));
1739 if (instr->num_components > 1) {
1740 ntq_store_dest(c, &instr->dest, 1,
1741 vir_uniform(c, QUNIFORM_IMAGE_HEIGHT,
1742 image_index));
1743 }
1744 if (instr->num_components > 2) {
1745 ntq_store_dest(c, &instr->dest, 2,
1746 vir_uniform(c,
1747 is_array ?
1748 QUNIFORM_IMAGE_ARRAY_SIZE :
1749 QUNIFORM_IMAGE_DEPTH,
1750 image_index));
1751 }
1752 }
1753
1754 static void
1755 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1756 {
1757 unsigned offset;
1758
1759 switch (instr->intrinsic) {
1760 case nir_intrinsic_load_uniform:
1761 if (nir_src_is_const(instr->src[0])) {
1762 int offset = (nir_intrinsic_base(instr) +
1763 nir_src_as_uint(instr->src[0]));
1764 assert(offset % 4 == 0);
1765 /* We need dwords */
1766 offset = offset / 4;
1767 for (int i = 0; i < instr->num_components; i++) {
1768 ntq_store_dest(c, &instr->dest, i,
1769 vir_uniform(c, QUNIFORM_UNIFORM,
1770 offset + i));
1771 }
1772 } else {
1773 ntq_emit_tmu_general(c, instr, false);
1774 }
1775 break;
1776
1777 case nir_intrinsic_load_ubo:
1778 ntq_emit_tmu_general(c, instr, false);
1779 break;
1780
1781 case nir_intrinsic_ssbo_atomic_add:
1782 case nir_intrinsic_ssbo_atomic_imin:
1783 case nir_intrinsic_ssbo_atomic_umin:
1784 case nir_intrinsic_ssbo_atomic_imax:
1785 case nir_intrinsic_ssbo_atomic_umax:
1786 case nir_intrinsic_ssbo_atomic_and:
1787 case nir_intrinsic_ssbo_atomic_or:
1788 case nir_intrinsic_ssbo_atomic_xor:
1789 case nir_intrinsic_ssbo_atomic_exchange:
1790 case nir_intrinsic_ssbo_atomic_comp_swap:
1791 case nir_intrinsic_load_ssbo:
1792 case nir_intrinsic_store_ssbo:
1793 ntq_emit_tmu_general(c, instr, false);
1794 break;
1795
1796 case nir_intrinsic_shared_atomic_add:
1797 case nir_intrinsic_shared_atomic_imin:
1798 case nir_intrinsic_shared_atomic_umin:
1799 case nir_intrinsic_shared_atomic_imax:
1800 case nir_intrinsic_shared_atomic_umax:
1801 case nir_intrinsic_shared_atomic_and:
1802 case nir_intrinsic_shared_atomic_or:
1803 case nir_intrinsic_shared_atomic_xor:
1804 case nir_intrinsic_shared_atomic_exchange:
1805 case nir_intrinsic_shared_atomic_comp_swap:
1806 case nir_intrinsic_load_shared:
1807 case nir_intrinsic_store_shared:
1808 ntq_emit_tmu_general(c, instr, true);
1809 break;
1810
1811 case nir_intrinsic_image_deref_load:
1812 case nir_intrinsic_image_deref_store:
1813 case nir_intrinsic_image_deref_atomic_add:
1814 case nir_intrinsic_image_deref_atomic_min:
1815 case nir_intrinsic_image_deref_atomic_max:
1816 case nir_intrinsic_image_deref_atomic_and:
1817 case nir_intrinsic_image_deref_atomic_or:
1818 case nir_intrinsic_image_deref_atomic_xor:
1819 case nir_intrinsic_image_deref_atomic_exchange:
1820 case nir_intrinsic_image_deref_atomic_comp_swap:
1821 v3d40_vir_emit_image_load_store(c, instr);
1822 break;
1823
1824 case nir_intrinsic_get_buffer_size:
1825 ntq_store_dest(c, &instr->dest, 0,
1826 vir_uniform(c, QUNIFORM_GET_BUFFER_SIZE,
1827 nir_src_as_uint(instr->src[0])));
1828 break;
1829
1830 case nir_intrinsic_load_user_clip_plane:
1831 for (int i = 0; i < instr->num_components; i++) {
1832 ntq_store_dest(c, &instr->dest, i,
1833 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1834 nir_intrinsic_ucp_id(instr) *
1835 4 + i));
1836 }
1837 break;
1838
1839 case nir_intrinsic_load_alpha_ref_float:
1840 ntq_store_dest(c, &instr->dest, 0,
1841 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1842 break;
1843
1844 case nir_intrinsic_load_sample_mask_in:
1845 ntq_store_dest(c, &instr->dest, 0, vir_MSF(c));
1846 break;
1847
1848 case nir_intrinsic_load_helper_invocation:
1849 vir_set_pf(vir_MSF_dest(c, vir_nop_reg()), V3D_QPU_PF_PUSHZ);
1850 ntq_store_dest(c, &instr->dest, 0,
1851 vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFA,
1852 vir_uniform_ui(c, ~0),
1853 vir_uniform_ui(c, 0))));
1854 break;
1855
1856 case nir_intrinsic_load_front_face:
1857 /* The register contains 0 (front) or 1 (back), and we need to
1858 * turn it into a NIR bool where true means front.
1859 */
1860 ntq_store_dest(c, &instr->dest, 0,
1861 vir_ADD(c,
1862 vir_uniform_ui(c, -1),
1863 vir_REVF(c)));
1864 break;
1865
1866 case nir_intrinsic_load_instance_id:
1867 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1868 break;
1869
1870 case nir_intrinsic_load_vertex_id:
1871 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1872 break;
1873
1874 case nir_intrinsic_load_input:
1875 offset = (nir_intrinsic_base(instr) +
1876 nir_src_as_uint(instr->src[0]));
1877 if (c->s->info.stage != MESA_SHADER_FRAGMENT &&
1878 c->devinfo->ver >= 40) {
1879 /* Emit the LDVPM directly now, rather than at the top
1880 * of the shader like we did for V3D 3.x (which needs
1881 * vpmsetup when not just taking the next offset).
1882 *
1883 * Note that delaying like this may introduce stalls,
1884 * as LDVPMV takes a minimum of 1 instruction but may
1885 * be slower if the VPM unit is busy with another QPU.
1886 */
1887 int index = 0;
1888 if (c->s->info.system_values_read &
1889 (1ull << SYSTEM_VALUE_INSTANCE_ID)) {
1890 index++;
1891 }
1892 if (c->s->info.system_values_read &
1893 (1ull << SYSTEM_VALUE_VERTEX_ID)) {
1894 index++;
1895 }
1896 for (int i = 0; i < offset; i++)
1897 index += c->vattr_sizes[i];
1898 index += nir_intrinsic_component(instr);
1899 for (int i = 0; i < instr->num_components; i++) {
1900 struct qreg vpm_offset =
1901 vir_uniform_ui(c, index++);
1902 ntq_store_dest(c, &instr->dest, i,
1903 vir_LDVPMV_IN(c, vpm_offset));
1904 }
1905 } else {
1906 for (int i = 0; i < instr->num_components; i++) {
1907 int comp = nir_intrinsic_component(instr) + i;
1908 ntq_store_dest(c, &instr->dest, i,
1909 vir_MOV(c, c->inputs[offset * 4 +
1910 comp]));
1911 }
1912 }
1913 break;
1914
1915 case nir_intrinsic_store_output:
1916 offset = ((nir_intrinsic_base(instr) +
1917 nir_src_as_uint(instr->src[1])) * 4 +
1918 nir_intrinsic_component(instr));
1919
1920 for (int i = 0; i < instr->num_components; i++) {
1921 c->outputs[offset + i] =
1922 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1923 }
1924 c->num_outputs = MAX2(c->num_outputs,
1925 offset + instr->num_components);
1926 break;
1927
1928 case nir_intrinsic_image_deref_size:
1929 ntq_emit_image_size(c, instr);
1930 break;
1931
1932 case nir_intrinsic_discard:
1933 if (vir_in_nonuniform_control_flow(c)) {
1934 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
1935 V3D_QPU_PF_PUSHZ);
1936 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1937 vir_uniform_ui(c, 0)),
1938 V3D_QPU_COND_IFA);
1939 } else {
1940 vir_SETMSF_dest(c, vir_nop_reg(),
1941 vir_uniform_ui(c, 0));
1942 }
1943 break;
1944
1945 case nir_intrinsic_discard_if: {
1946 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, instr->src[0]);
1947
1948 if (vir_in_nonuniform_control_flow(c)) {
1949 struct qinst *exec_flag = vir_MOV_dest(c, vir_nop_reg(),
1950 c->execute);
1951 if (cond == V3D_QPU_COND_IFA) {
1952 vir_set_uf(exec_flag, V3D_QPU_UF_ANDZ);
1953 } else {
1954 vir_set_uf(exec_flag, V3D_QPU_UF_NORNZ);
1955 cond = V3D_QPU_COND_IFA;
1956 }
1957 }
1958
1959 vir_set_cond(vir_SETMSF_dest(c, vir_nop_reg(),
1960 vir_uniform_ui(c, 0)), cond);
1961
1962 break;
1963 }
1964
1965 case nir_intrinsic_memory_barrier:
1966 case nir_intrinsic_memory_barrier_atomic_counter:
1967 case nir_intrinsic_memory_barrier_buffer:
1968 case nir_intrinsic_memory_barrier_image:
1969 case nir_intrinsic_memory_barrier_shared:
1970 /* We don't do any instruction scheduling of these NIR
1971 * instructions between each other, so we just need to make
1972 * sure that the TMU operations before the barrier are flushed
1973 * before the ones after the barrier. That is currently
1974 * handled by having a THRSW in each of them and a LDTMU
1975 * series or a TMUWT after.
1976 */
1977 break;
1978
1979 case nir_intrinsic_barrier:
1980 /* Emit a TSY op to get all invocations in the workgroup
1981 * (actually supergroup) to block until the last invocation
1982 * reaches the TSY op.
1983 */
1984 if (c->devinfo->ver >= 42) {
1985 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
1986 V3D_QPU_WADDR_SYNCB));
1987 } else {
1988 struct qinst *sync =
1989 vir_BARRIERID_dest(c,
1990 vir_reg(QFILE_MAGIC,
1991 V3D_QPU_WADDR_SYNCU));
1992 sync->src[vir_get_implicit_uniform_src(sync)] =
1993 vir_uniform_ui(c,
1994 0xffffff00 |
1995 V3D_TSY_WAIT_INC_CHECK);
1996
1997 }
1998
1999 /* The blocking of a TSY op only happens at the next thread
2000 * switch. No texturing may be outstanding at the time of a
2001 * TSY blocking operation.
2002 */
2003 vir_emit_thrsw(c);
2004 break;
2005
2006 case nir_intrinsic_load_num_work_groups:
2007 for (int i = 0; i < 3; i++) {
2008 ntq_store_dest(c, &instr->dest, i,
2009 vir_uniform(c, QUNIFORM_NUM_WORK_GROUPS,
2010 i));
2011 }
2012 break;
2013
2014 case nir_intrinsic_load_local_invocation_index:
2015 ntq_store_dest(c, &instr->dest, 0,
2016 vir_SHR(c, c->cs_payload[1],
2017 vir_uniform_ui(c, 32 - c->local_invocation_index_bits)));
2018 break;
2019
2020 case nir_intrinsic_load_work_group_id:
2021 ntq_store_dest(c, &instr->dest, 0,
2022 vir_AND(c, c->cs_payload[0],
2023 vir_uniform_ui(c, 0xffff)));
2024 ntq_store_dest(c, &instr->dest, 1,
2025 vir_SHR(c, c->cs_payload[0],
2026 vir_uniform_ui(c, 16)));
2027 ntq_store_dest(c, &instr->dest, 2,
2028 vir_AND(c, c->cs_payload[1],
2029 vir_uniform_ui(c, 0xffff)));
2030 break;
2031
2032 default:
2033 fprintf(stderr, "Unknown intrinsic: ");
2034 nir_print_instr(&instr->instr, stderr);
2035 fprintf(stderr, "\n");
2036 break;
2037 }
2038 }
2039
2040 /* Clears (activates) the execute flags for any channels whose jump target
2041 * matches this block.
2042 *
2043 * XXX perf: Could we be using flpush/flpop somehow for our execution channel
2044 * enabling?
2045 *
2046 * XXX perf: For uniform control flow, we should be able to skip c->execute
2047 * handling entirely.
2048 */
2049 static void
2050 ntq_activate_execute_for_block(struct v3d_compile *c)
2051 {
2052 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2053 c->execute, vir_uniform_ui(c, c->cur_block->index)),
2054 V3D_QPU_PF_PUSHZ);
2055
2056 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2057 }
2058
2059 static void
2060 ntq_emit_uniform_if(struct v3d_compile *c, nir_if *if_stmt)
2061 {
2062 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2063 bool empty_else_block =
2064 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2065 exec_list_is_empty(&nir_else_block->instr_list));
2066
2067 struct qblock *then_block = vir_new_block(c);
2068 struct qblock *after_block = vir_new_block(c);
2069 struct qblock *else_block;
2070 if (empty_else_block)
2071 else_block = after_block;
2072 else
2073 else_block = vir_new_block(c);
2074
2075 /* Set up the flags for the IF condition (taking the THEN branch). */
2076 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2077
2078 /* Jump to ELSE. */
2079 vir_BRANCH(c, cond == V3D_QPU_COND_IFA ?
2080 V3D_QPU_BRANCH_COND_ALLNA :
2081 V3D_QPU_BRANCH_COND_ALLA);
2082 vir_link_blocks(c->cur_block, else_block);
2083 vir_link_blocks(c->cur_block, then_block);
2084
2085 /* Process the THEN block. */
2086 vir_set_emit_block(c, then_block);
2087 ntq_emit_cf_list(c, &if_stmt->then_list);
2088
2089 if (!empty_else_block) {
2090 /* At the end of the THEN block, jump to ENDIF */
2091 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALWAYS);
2092 vir_link_blocks(c->cur_block, after_block);
2093
2094 /* Emit the else block. */
2095 vir_set_emit_block(c, else_block);
2096 ntq_activate_execute_for_block(c);
2097 ntq_emit_cf_list(c, &if_stmt->else_list);
2098 }
2099
2100 vir_link_blocks(c->cur_block, after_block);
2101
2102 vir_set_emit_block(c, after_block);
2103 }
2104
2105 static void
2106 ntq_emit_nonuniform_if(struct v3d_compile *c, nir_if *if_stmt)
2107 {
2108 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
2109 bool empty_else_block =
2110 (nir_else_block == nir_if_last_else_block(if_stmt) &&
2111 exec_list_is_empty(&nir_else_block->instr_list));
2112
2113 struct qblock *then_block = vir_new_block(c);
2114 struct qblock *after_block = vir_new_block(c);
2115 struct qblock *else_block;
2116 if (empty_else_block)
2117 else_block = after_block;
2118 else
2119 else_block = vir_new_block(c);
2120
2121 bool was_uniform_control_flow = false;
2122 if (!vir_in_nonuniform_control_flow(c)) {
2123 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2124 was_uniform_control_flow = true;
2125 }
2126
2127 /* Set up the flags for the IF condition (taking the THEN branch). */
2128 enum v3d_qpu_cond cond = ntq_emit_bool_to_cond(c, if_stmt->condition);
2129
2130 /* Update the flags+cond to mean "Taking the ELSE branch (!cond) and
2131 * was previously active (execute Z) for updating the exec flags.
2132 */
2133 if (was_uniform_control_flow) {
2134 cond = v3d_qpu_cond_invert(cond);
2135 } else {
2136 struct qinst *inst = vir_MOV_dest(c, vir_nop_reg(), c->execute);
2137 if (cond == V3D_QPU_COND_IFA) {
2138 vir_set_uf(inst, V3D_QPU_UF_NORNZ);
2139 } else {
2140 vir_set_uf(inst, V3D_QPU_UF_ANDZ);
2141 cond = V3D_QPU_COND_IFA;
2142 }
2143 }
2144
2145 vir_MOV_cond(c, cond,
2146 c->execute,
2147 vir_uniform_ui(c, else_block->index));
2148
2149 /* Jump to ELSE if nothing is active for THEN, otherwise fall
2150 * through.
2151 */
2152 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2153 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
2154 vir_link_blocks(c->cur_block, else_block);
2155 vir_link_blocks(c->cur_block, then_block);
2156
2157 /* Process the THEN block. */
2158 vir_set_emit_block(c, then_block);
2159 ntq_emit_cf_list(c, &if_stmt->then_list);
2160
2161 if (!empty_else_block) {
2162 /* Handle the end of the THEN block. First, all currently
2163 * active channels update their execute flags to point to
2164 * ENDIF
2165 */
2166 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2167 V3D_QPU_PF_PUSHZ);
2168 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2169 vir_uniform_ui(c, after_block->index));
2170
2171 /* If everything points at ENDIF, then jump there immediately. */
2172 vir_set_pf(vir_XOR_dest(c, vir_nop_reg(),
2173 c->execute,
2174 vir_uniform_ui(c, after_block->index)),
2175 V3D_QPU_PF_PUSHZ);
2176 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
2177 vir_link_blocks(c->cur_block, after_block);
2178 vir_link_blocks(c->cur_block, else_block);
2179
2180 vir_set_emit_block(c, else_block);
2181 ntq_activate_execute_for_block(c);
2182 ntq_emit_cf_list(c, &if_stmt->else_list);
2183 }
2184
2185 vir_link_blocks(c->cur_block, after_block);
2186
2187 vir_set_emit_block(c, after_block);
2188 if (was_uniform_control_flow)
2189 c->execute = c->undef;
2190 else
2191 ntq_activate_execute_for_block(c);
2192 }
2193
2194 static void
2195 ntq_emit_if(struct v3d_compile *c, nir_if *nif)
2196 {
2197 bool was_in_control_flow = c->in_control_flow;
2198 c->in_control_flow = true;
2199 if (!vir_in_nonuniform_control_flow(c) &&
2200 nir_src_is_dynamically_uniform(nif->condition)) {
2201 ntq_emit_uniform_if(c, nif);
2202 } else {
2203 ntq_emit_nonuniform_if(c, nif);
2204 }
2205 c->in_control_flow = was_in_control_flow;
2206 }
2207
2208 static void
2209 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
2210 {
2211 switch (jump->type) {
2212 case nir_jump_break:
2213 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2214 V3D_QPU_PF_PUSHZ);
2215 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2216 vir_uniform_ui(c, c->loop_break_block->index));
2217 break;
2218
2219 case nir_jump_continue:
2220 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
2221 V3D_QPU_PF_PUSHZ);
2222 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
2223 vir_uniform_ui(c, c->loop_cont_block->index));
2224 break;
2225
2226 case nir_jump_return:
2227 unreachable("All returns shouold be lowered\n");
2228 }
2229 }
2230
2231 static void
2232 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
2233 {
2234 switch (instr->type) {
2235 case nir_instr_type_deref:
2236 /* ignored, will be walked by the intrinsic using it. */
2237 break;
2238
2239 case nir_instr_type_alu:
2240 ntq_emit_alu(c, nir_instr_as_alu(instr));
2241 break;
2242
2243 case nir_instr_type_intrinsic:
2244 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2245 break;
2246
2247 case nir_instr_type_load_const:
2248 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2249 break;
2250
2251 case nir_instr_type_ssa_undef:
2252 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2253 break;
2254
2255 case nir_instr_type_tex:
2256 ntq_emit_tex(c, nir_instr_as_tex(instr));
2257 break;
2258
2259 case nir_instr_type_jump:
2260 ntq_emit_jump(c, nir_instr_as_jump(instr));
2261 break;
2262
2263 default:
2264 fprintf(stderr, "Unknown NIR instr type: ");
2265 nir_print_instr(instr, stderr);
2266 fprintf(stderr, "\n");
2267 abort();
2268 }
2269 }
2270
2271 static void
2272 ntq_emit_block(struct v3d_compile *c, nir_block *block)
2273 {
2274 nir_foreach_instr(instr, block) {
2275 ntq_emit_instr(c, instr);
2276 }
2277 }
2278
2279 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
2280
2281 static void
2282 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
2283 {
2284 bool was_in_control_flow = c->in_control_flow;
2285 c->in_control_flow = true;
2286
2287 bool was_uniform_control_flow = false;
2288 if (!vir_in_nonuniform_control_flow(c)) {
2289 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
2290 was_uniform_control_flow = true;
2291 }
2292
2293 struct qblock *save_loop_cont_block = c->loop_cont_block;
2294 struct qblock *save_loop_break_block = c->loop_break_block;
2295
2296 c->loop_cont_block = vir_new_block(c);
2297 c->loop_break_block = vir_new_block(c);
2298
2299 vir_link_blocks(c->cur_block, c->loop_cont_block);
2300 vir_set_emit_block(c, c->loop_cont_block);
2301 ntq_activate_execute_for_block(c);
2302
2303 ntq_emit_cf_list(c, &loop->body);
2304
2305 /* Re-enable any previous continues now, so our ANYA check below
2306 * works.
2307 *
2308 * XXX: Use the .ORZ flags update, instead.
2309 */
2310 vir_set_pf(vir_XOR_dest(c,
2311 vir_nop_reg(),
2312 c->execute,
2313 vir_uniform_ui(c, c->loop_cont_block->index)),
2314 V3D_QPU_PF_PUSHZ);
2315 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
2316
2317 vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute), V3D_QPU_PF_PUSHZ);
2318
2319 struct qinst *branch = vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
2320 /* Pixels that were not dispatched or have been discarded should not
2321 * contribute to looping again.
2322 */
2323 branch->qpu.branch.msfign = V3D_QPU_MSFIGN_P;
2324 vir_link_blocks(c->cur_block, c->loop_cont_block);
2325 vir_link_blocks(c->cur_block, c->loop_break_block);
2326
2327 vir_set_emit_block(c, c->loop_break_block);
2328 if (was_uniform_control_flow)
2329 c->execute = c->undef;
2330 else
2331 ntq_activate_execute_for_block(c);
2332
2333 c->loop_break_block = save_loop_break_block;
2334 c->loop_cont_block = save_loop_cont_block;
2335
2336 c->loops++;
2337
2338 c->in_control_flow = was_in_control_flow;
2339 }
2340
2341 static void
2342 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
2343 {
2344 fprintf(stderr, "FUNCTIONS not handled.\n");
2345 abort();
2346 }
2347
2348 static void
2349 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
2350 {
2351 foreach_list_typed(nir_cf_node, node, node, list) {
2352 switch (node->type) {
2353 case nir_cf_node_block:
2354 ntq_emit_block(c, nir_cf_node_as_block(node));
2355 break;
2356
2357 case nir_cf_node_if:
2358 ntq_emit_if(c, nir_cf_node_as_if(node));
2359 break;
2360
2361 case nir_cf_node_loop:
2362 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2363 break;
2364
2365 case nir_cf_node_function:
2366 ntq_emit_function(c, nir_cf_node_as_function(node));
2367 break;
2368
2369 default:
2370 fprintf(stderr, "Unknown NIR node type\n");
2371 abort();
2372 }
2373 }
2374 }
2375
2376 static void
2377 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
2378 {
2379 ntq_setup_registers(c, &impl->registers);
2380 ntq_emit_cf_list(c, &impl->body);
2381 }
2382
2383 static void
2384 nir_to_vir(struct v3d_compile *c)
2385 {
2386 switch (c->s->info.stage) {
2387 case MESA_SHADER_FRAGMENT:
2388 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
2389 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
2390 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
2391
2392 /* XXX perf: We could set the "disable implicit point/line
2393 * varyings" field in the shader record and not emit these, if
2394 * they're not going to be used.
2395 */
2396 if (c->fs_key->is_points) {
2397 c->point_x = emit_fragment_varying(c, NULL, 0, 0);
2398 c->point_y = emit_fragment_varying(c, NULL, 0, 0);
2399 } else if (c->fs_key->is_lines) {
2400 c->line_x = emit_fragment_varying(c, NULL, 0, 0);
2401 }
2402 break;
2403 case MESA_SHADER_COMPUTE:
2404 /* Set up the TSO for barriers, assuming we do some. */
2405 if (c->devinfo->ver < 42) {
2406 vir_BARRIERID_dest(c, vir_reg(QFILE_MAGIC,
2407 V3D_QPU_WADDR_SYNC));
2408 }
2409
2410 if (c->s->info.system_values_read &
2411 ((1ull << SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) |
2412 (1ull << SYSTEM_VALUE_WORK_GROUP_ID))) {
2413 c->cs_payload[0] = vir_MOV(c, vir_reg(QFILE_REG, 0));
2414 }
2415 if ((c->s->info.system_values_read &
2416 ((1ull << SYSTEM_VALUE_WORK_GROUP_ID))) ||
2417 c->s->info.cs.shared_size) {
2418 c->cs_payload[1] = vir_MOV(c, vir_reg(QFILE_REG, 2));
2419 }
2420
2421 /* Set up the division between gl_LocalInvocationIndex and
2422 * wg_in_mem in the payload reg.
2423 */
2424 int wg_size = (c->s->info.cs.local_size[0] *
2425 c->s->info.cs.local_size[1] *
2426 c->s->info.cs.local_size[2]);
2427 c->local_invocation_index_bits =
2428 ffs(util_next_power_of_two(MAX2(wg_size, 64))) - 1;
2429 assert(c->local_invocation_index_bits <= 8);
2430
2431 if (c->s->info.cs.shared_size) {
2432 struct qreg wg_in_mem = vir_SHR(c, c->cs_payload[1],
2433 vir_uniform_ui(c, 16));
2434 if (c->s->info.cs.local_size[0] != 1 ||
2435 c->s->info.cs.local_size[1] != 1 ||
2436 c->s->info.cs.local_size[2] != 1) {
2437 int wg_bits = (16 -
2438 c->local_invocation_index_bits);
2439 int wg_mask = (1 << wg_bits) - 1;
2440 wg_in_mem = vir_AND(c, wg_in_mem,
2441 vir_uniform_ui(c, wg_mask));
2442 }
2443 struct qreg shared_per_wg =
2444 vir_uniform_ui(c, c->s->info.cs.shared_size);
2445
2446 c->cs_shared_offset =
2447 vir_ADD(c,
2448 vir_uniform(c, QUNIFORM_SHARED_OFFSET,0),
2449 vir_UMUL(c, wg_in_mem, shared_per_wg));
2450 }
2451 break;
2452 default:
2453 break;
2454 }
2455
2456 if (c->s->info.stage == MESA_SHADER_FRAGMENT)
2457 ntq_setup_fs_inputs(c);
2458 else
2459 ntq_setup_vpm_inputs(c);
2460
2461 ntq_setup_outputs(c);
2462 ntq_setup_uniforms(c);
2463 ntq_setup_registers(c, &c->s->registers);
2464
2465 /* Find the main function and emit the body. */
2466 nir_foreach_function(function, c->s) {
2467 assert(strcmp(function->name, "main") == 0);
2468 assert(function->impl);
2469 ntq_emit_impl(c, function->impl);
2470 }
2471 }
2472
2473 const nir_shader_compiler_options v3d_nir_options = {
2474 .lower_all_io_to_temps = true,
2475 .lower_extract_byte = true,
2476 .lower_extract_word = true,
2477 .lower_bfm = true,
2478 .lower_bitfield_insert_to_shifts = true,
2479 .lower_bitfield_extract_to_shifts = true,
2480 .lower_bitfield_reverse = true,
2481 .lower_bit_count = true,
2482 .lower_cs_local_id_from_index = true,
2483 .lower_ffract = true,
2484 .lower_pack_unorm_2x16 = true,
2485 .lower_pack_snorm_2x16 = true,
2486 .lower_pack_unorm_4x8 = true,
2487 .lower_pack_snorm_4x8 = true,
2488 .lower_unpack_unorm_4x8 = true,
2489 .lower_unpack_snorm_4x8 = true,
2490 .lower_pack_half_2x16 = true,
2491 .lower_unpack_half_2x16 = true,
2492 .lower_fdiv = true,
2493 .lower_find_lsb = true,
2494 .lower_ffma = true,
2495 .lower_flrp32 = true,
2496 .lower_fpow = true,
2497 .lower_fsat = true,
2498 .lower_fsqrt = true,
2499 .lower_ifind_msb = true,
2500 .lower_isign = true,
2501 .lower_ldexp = true,
2502 .lower_mul_high = true,
2503 .lower_wpos_pntc = true,
2504 .native_integers = true,
2505 };
2506
2507 /**
2508 * When demoting a shader down to single-threaded, removes the THRSW
2509 * instructions (one will still be inserted at v3d_vir_to_qpu() for the
2510 * program end).
2511 */
2512 static void
2513 vir_remove_thrsw(struct v3d_compile *c)
2514 {
2515 vir_for_each_block(block, c) {
2516 vir_for_each_inst_safe(inst, block) {
2517 if (inst->qpu.sig.thrsw)
2518 vir_remove_instruction(c, inst);
2519 }
2520 }
2521
2522 c->last_thrsw = NULL;
2523 }
2524
2525 void
2526 vir_emit_last_thrsw(struct v3d_compile *c)
2527 {
2528 /* On V3D before 4.1, we need a TMU op to be outstanding when thread
2529 * switching, so disable threads if we didn't do any TMU ops (each of
2530 * which would have emitted a THRSW).
2531 */
2532 if (!c->last_thrsw_at_top_level && c->devinfo->ver < 41) {
2533 c->threads = 1;
2534 if (c->last_thrsw)
2535 vir_remove_thrsw(c);
2536 return;
2537 }
2538
2539 /* If we're threaded and the last THRSW was in conditional code, then
2540 * we need to emit another one so that we can flag it as the last
2541 * thrsw.
2542 */
2543 if (c->last_thrsw && !c->last_thrsw_at_top_level) {
2544 assert(c->devinfo->ver >= 41);
2545 vir_emit_thrsw(c);
2546 }
2547
2548 /* If we're threaded, then we need to mark the last THRSW instruction
2549 * so we can emit a pair of them at QPU emit time.
2550 *
2551 * For V3D 4.x, we can spawn the non-fragment shaders already in the
2552 * post-last-THRSW state, so we can skip this.
2553 */
2554 if (!c->last_thrsw && c->s->info.stage == MESA_SHADER_FRAGMENT) {
2555 assert(c->devinfo->ver >= 41);
2556 vir_emit_thrsw(c);
2557 }
2558
2559 if (c->last_thrsw)
2560 c->last_thrsw->is_last_thrsw = true;
2561 }
2562
2563 /* There's a flag in the shader for "center W is needed for reasons other than
2564 * non-centroid varyings", so we just walk the program after VIR optimization
2565 * to see if it's used. It should be harmless to set even if we only use
2566 * center W for varyings.
2567 */
2568 static void
2569 vir_check_payload_w(struct v3d_compile *c)
2570 {
2571 if (c->s->info.stage != MESA_SHADER_FRAGMENT)
2572 return;
2573
2574 vir_for_each_inst_inorder(inst, c) {
2575 for (int i = 0; i < vir_get_nsrc(inst); i++) {
2576 if (inst->src[i].file == QFILE_REG &&
2577 inst->src[i].index == 0) {
2578 c->uses_center_w = true;
2579 return;
2580 }
2581 }
2582 }
2583
2584 }
2585
2586 void
2587 v3d_nir_to_vir(struct v3d_compile *c)
2588 {
2589 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2590 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2591 fprintf(stderr, "%s prog %d/%d NIR:\n",
2592 vir_get_stage_name(c),
2593 c->program_id, c->variant_id);
2594 nir_print_shader(c->s, stderr);
2595 }
2596
2597 nir_to_vir(c);
2598
2599 /* Emit the last THRSW before STVPM and TLB writes. */
2600 vir_emit_last_thrsw(c);
2601
2602 switch (c->s->info.stage) {
2603 case MESA_SHADER_FRAGMENT:
2604 emit_frag_end(c);
2605 break;
2606 case MESA_SHADER_VERTEX:
2607 emit_vert_end(c);
2608 break;
2609 default:
2610 unreachable("bad stage");
2611 }
2612
2613 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2614 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2615 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2616 vir_get_stage_name(c),
2617 c->program_id, c->variant_id);
2618 vir_dump(c);
2619 fprintf(stderr, "\n");
2620 }
2621
2622 vir_optimize(c);
2623 vir_lower_uniforms(c);
2624
2625 vir_check_payload_w(c);
2626
2627 /* XXX perf: On VC4, we do a VIR-level instruction scheduling here.
2628 * We used that on that platform to pipeline TMU writes and reduce the
2629 * number of thread switches, as well as try (mostly successfully) to
2630 * reduce maximum register pressure to allow more threads. We should
2631 * do something of that sort for V3D -- either instruction scheduling
2632 * here, or delay the the THRSW and LDTMUs from our texture
2633 * instructions until the results are needed.
2634 */
2635
2636 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2637 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2638 fprintf(stderr, "%s prog %d/%d VIR:\n",
2639 vir_get_stage_name(c),
2640 c->program_id, c->variant_id);
2641 vir_dump(c);
2642 fprintf(stderr, "\n");
2643 }
2644
2645 /* Attempt to allocate registers for the temporaries. If we fail,
2646 * reduce thread count and try again.
2647 */
2648 int min_threads = (c->devinfo->ver >= 41) ? 2 : 1;
2649 struct qpu_reg *temp_registers;
2650 while (true) {
2651 bool spilled;
2652 temp_registers = v3d_register_allocate(c, &spilled);
2653 if (spilled)
2654 continue;
2655
2656 if (temp_registers)
2657 break;
2658
2659 if (c->threads == min_threads) {
2660 fprintf(stderr, "Failed to register allocate at %d threads:\n",
2661 c->threads);
2662 vir_dump(c);
2663 c->failed = true;
2664 return;
2665 }
2666
2667 c->threads /= 2;
2668
2669 if (c->threads == 1)
2670 vir_remove_thrsw(c);
2671 }
2672
2673 v3d_vir_to_qpu(c, temp_registers);
2674 }