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broadcom/vc5: Stop lowering negates to subs.
[mesa.git] / src / broadcom / compiler / nir_to_vir.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <inttypes.h>
25 #include "util/u_format.h"
26 #include "util/u_math.h"
27 #include "util/u_memory.h"
28 #include "util/ralloc.h"
29 #include "util/hash_table.h"
30 #include "compiler/nir/nir.h"
31 #include "compiler/nir/nir_builder.h"
32 #include "v3d_compiler.h"
33
34 /* We don't do any address packing. */
35 #define __gen_user_data void
36 #define __gen_address_type uint32_t
37 #define __gen_address_offset(reloc) (*reloc)
38 #define __gen_emit_reloc(cl, reloc)
39 #include "cle/v3d_packet_v33_pack.h"
40
41 static struct qreg
42 ntq_get_src(struct v3d_compile *c, nir_src src, int i);
43 static void
44 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
45
46 static void
47 resize_qreg_array(struct v3d_compile *c,
48 struct qreg **regs,
49 uint32_t *size,
50 uint32_t decl_size)
51 {
52 if (*size >= decl_size)
53 return;
54
55 uint32_t old_size = *size;
56 *size = MAX2(*size * 2, decl_size);
57 *regs = reralloc(c, *regs, struct qreg, *size);
58 if (!*regs) {
59 fprintf(stderr, "Malloc failure\n");
60 abort();
61 }
62
63 for (uint32_t i = old_size; i < *size; i++)
64 (*regs)[i] = c->undef;
65 }
66
67 static struct qreg
68 vir_SFU(struct v3d_compile *c, int waddr, struct qreg src)
69 {
70 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, waddr), src);
71 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
72 }
73
74 static struct qreg
75 vir_LDTMU(struct v3d_compile *c)
76 {
77 vir_NOP(c)->qpu.sig.ldtmu = true;
78 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
79 }
80
81 static struct qreg
82 indirect_uniform_load(struct v3d_compile *c, nir_intrinsic_instr *intr)
83 {
84 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
85 uint32_t offset = nir_intrinsic_base(intr);
86 struct v3d_ubo_range *range = NULL;
87 unsigned i;
88
89 for (i = 0; i < c->num_ubo_ranges; i++) {
90 range = &c->ubo_ranges[i];
91 if (offset >= range->src_offset &&
92 offset < range->src_offset + range->size) {
93 break;
94 }
95 }
96 /* The driver-location-based offset always has to be within a declared
97 * uniform range.
98 */
99 assert(i != c->num_ubo_ranges);
100 if (!c->ubo_range_used[i]) {
101 c->ubo_range_used[i] = true;
102 range->dst_offset = c->next_ubo_dst_offset;
103 c->next_ubo_dst_offset += range->size;
104 }
105
106 offset -= range->src_offset;
107
108 if (range->dst_offset + offset != 0) {
109 indirect_offset = vir_ADD(c, indirect_offset,
110 vir_uniform_ui(c, range->dst_offset +
111 offset));
112 }
113
114 /* Adjust for where we stored the TGSI register base. */
115 vir_ADD_dest(c,
116 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
117 vir_uniform(c, QUNIFORM_UBO_ADDR, 0),
118 indirect_offset);
119
120 return vir_LDTMU(c);
121 }
122
123 static struct qreg *
124 ntq_init_ssa_def(struct v3d_compile *c, nir_ssa_def *def)
125 {
126 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
127 def->num_components);
128 _mesa_hash_table_insert(c->def_ht, def, qregs);
129 return qregs;
130 }
131
132 /**
133 * This function is responsible for getting VIR results into the associated
134 * storage for a NIR instruction.
135 *
136 * If it's a NIR SSA def, then we just set the associated hash table entry to
137 * the new result.
138 *
139 * If it's a NIR reg, then we need to update the existing qreg assigned to the
140 * NIR destination with the incoming value. To do that without introducing
141 * new MOVs, we require that the incoming qreg either be a uniform, or be
142 * SSA-defined by the previous VIR instruction in the block and rewritable by
143 * this function. That lets us sneak ahead and insert the SF flag beforehand
144 * (knowing that the previous instruction doesn't depend on flags) and rewrite
145 * its destination to be the NIR reg's destination
146 */
147 static void
148 ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
149 struct qreg result)
150 {
151 struct qinst *last_inst = NULL;
152 if (!list_empty(&c->cur_block->instructions))
153 last_inst = (struct qinst *)c->cur_block->instructions.prev;
154
155 assert(result.file == QFILE_UNIF ||
156 (result.file == QFILE_TEMP &&
157 last_inst && last_inst == c->defs[result.index]));
158
159 if (dest->is_ssa) {
160 assert(chan < dest->ssa.num_components);
161
162 struct qreg *qregs;
163 struct hash_entry *entry =
164 _mesa_hash_table_search(c->def_ht, &dest->ssa);
165
166 if (entry)
167 qregs = entry->data;
168 else
169 qregs = ntq_init_ssa_def(c, &dest->ssa);
170
171 qregs[chan] = result;
172 } else {
173 nir_register *reg = dest->reg.reg;
174 assert(dest->reg.base_offset == 0);
175 assert(reg->num_array_elems == 0);
176 struct hash_entry *entry =
177 _mesa_hash_table_search(c->def_ht, reg);
178 struct qreg *qregs = entry->data;
179
180 /* Insert a MOV if the source wasn't an SSA def in the
181 * previous instruction.
182 */
183 if (result.file == QFILE_UNIF) {
184 result = vir_MOV(c, result);
185 last_inst = c->defs[result.index];
186 }
187
188 /* We know they're both temps, so just rewrite index. */
189 c->defs[last_inst->dst.index] = NULL;
190 last_inst->dst.index = qregs[chan].index;
191
192 /* If we're in control flow, then make this update of the reg
193 * conditional on the execution mask.
194 */
195 if (c->execute.file != QFILE_NULL) {
196 last_inst->dst.index = qregs[chan].index;
197
198 /* Set the flags to the current exec mask. To insert
199 * the flags push, we temporarily remove our SSA
200 * instruction.
201 */
202 list_del(&last_inst->link);
203 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
204 list_addtail(&last_inst->link,
205 &c->cur_block->instructions);
206
207 vir_set_cond(last_inst, V3D_QPU_COND_IFA);
208 last_inst->cond_is_exec_mask = true;
209 }
210 }
211 }
212
213 static struct qreg
214 ntq_get_src(struct v3d_compile *c, nir_src src, int i)
215 {
216 struct hash_entry *entry;
217 if (src.is_ssa) {
218 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
219 assert(i < src.ssa->num_components);
220 } else {
221 nir_register *reg = src.reg.reg;
222 entry = _mesa_hash_table_search(c->def_ht, reg);
223 assert(reg->num_array_elems == 0);
224 assert(src.reg.base_offset == 0);
225 assert(i < reg->num_components);
226 }
227
228 struct qreg *qregs = entry->data;
229 return qregs[i];
230 }
231
232 static struct qreg
233 ntq_get_alu_src(struct v3d_compile *c, nir_alu_instr *instr,
234 unsigned src)
235 {
236 assert(util_is_power_of_two(instr->dest.write_mask));
237 unsigned chan = ffs(instr->dest.write_mask) - 1;
238 struct qreg r = ntq_get_src(c, instr->src[src].src,
239 instr->src[src].swizzle[chan]);
240
241 assert(!instr->src[src].abs);
242 assert(!instr->src[src].negate);
243
244 return r;
245 };
246
247 static inline struct qreg
248 vir_SAT(struct v3d_compile *c, struct qreg val)
249 {
250 return vir_FMAX(c,
251 vir_FMIN(c, val, vir_uniform_f(c, 1.0)),
252 vir_uniform_f(c, 0.0));
253 }
254
255 static struct qreg
256 ntq_umul(struct v3d_compile *c, struct qreg src0, struct qreg src1)
257 {
258 vir_MULTOP(c, src0, src1);
259 return vir_UMUL24(c, src0, src1);
260 }
261
262 static struct qreg
263 ntq_minify(struct v3d_compile *c, struct qreg size, struct qreg level)
264 {
265 return vir_MAX(c, vir_SHR(c, size, level), vir_uniform_ui(c, 1));
266 }
267
268 static void
269 ntq_emit_txs(struct v3d_compile *c, nir_tex_instr *instr)
270 {
271 unsigned unit = instr->texture_index;
272 int lod_index = nir_tex_instr_src_index(instr, nir_tex_src_lod);
273 int dest_size = nir_tex_instr_dest_size(instr);
274
275 struct qreg lod = c->undef;
276 if (lod_index != -1)
277 lod = ntq_get_src(c, instr->src[lod_index].src, 0);
278
279 for (int i = 0; i < dest_size; i++) {
280 assert(i < 3);
281 enum quniform_contents contents;
282
283 if (instr->is_array && i == dest_size - 1)
284 contents = QUNIFORM_TEXTURE_ARRAY_SIZE;
285 else
286 contents = QUNIFORM_TEXTURE_WIDTH + i;
287
288 struct qreg size = vir_uniform(c, contents, unit);
289
290 switch (instr->sampler_dim) {
291 case GLSL_SAMPLER_DIM_1D:
292 case GLSL_SAMPLER_DIM_2D:
293 case GLSL_SAMPLER_DIM_3D:
294 case GLSL_SAMPLER_DIM_CUBE:
295 /* Don't minify the array size. */
296 if (!(instr->is_array && i == dest_size - 1)) {
297 size = ntq_minify(c, size, lod);
298 }
299 break;
300
301 case GLSL_SAMPLER_DIM_RECT:
302 /* There's no LOD field for rects */
303 break;
304
305 default:
306 unreachable("Bad sampler type");
307 }
308
309 ntq_store_dest(c, &instr->dest, i, size);
310 }
311 }
312
313 static void
314 ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
315 {
316 unsigned unit = instr->texture_index;
317
318 /* Since each texture sampling op requires uploading uniforms to
319 * reference the texture, there's no HW support for texture size and
320 * you just upload uniforms containing the size.
321 */
322 switch (instr->op) {
323 case nir_texop_query_levels:
324 ntq_store_dest(c, &instr->dest, 0,
325 vir_uniform(c, QUNIFORM_TEXTURE_LEVELS, unit));
326 return;
327 case nir_texop_txs:
328 ntq_emit_txs(c, instr);
329 return;
330 default:
331 break;
332 }
333
334 struct V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1 p0_unpacked = {
335 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_header,
336
337 .fetch_sample_mode = instr->op == nir_texop_txf,
338 };
339
340 switch (instr->sampler_dim) {
341 case GLSL_SAMPLER_DIM_1D:
342 if (instr->is_array)
343 p0_unpacked.lookup_type = TEXTURE_1D_ARRAY;
344 else
345 p0_unpacked.lookup_type = TEXTURE_1D;
346 break;
347 case GLSL_SAMPLER_DIM_2D:
348 case GLSL_SAMPLER_DIM_RECT:
349 if (instr->is_array)
350 p0_unpacked.lookup_type = TEXTURE_2D_ARRAY;
351 else
352 p0_unpacked.lookup_type = TEXTURE_2D;
353 break;
354 case GLSL_SAMPLER_DIM_3D:
355 p0_unpacked.lookup_type = TEXTURE_3D;
356 break;
357 case GLSL_SAMPLER_DIM_CUBE:
358 p0_unpacked.lookup_type = TEXTURE_CUBE_MAP;
359 break;
360 default:
361 unreachable("Bad sampler type");
362 }
363
364 struct qreg coords[5];
365 int next_coord = 0;
366 for (unsigned i = 0; i < instr->num_srcs; i++) {
367 switch (instr->src[i].src_type) {
368 case nir_tex_src_coord:
369 for (int j = 0; j < instr->coord_components; j++) {
370 coords[next_coord++] =
371 ntq_get_src(c, instr->src[i].src, j);
372 }
373 if (instr->coord_components < 2)
374 coords[next_coord++] = vir_uniform_f(c, 0.5);
375 break;
376 case nir_tex_src_bias:
377 coords[next_coord++] =
378 ntq_get_src(c, instr->src[i].src, 0);
379
380 p0_unpacked.bias_supplied = true;
381 break;
382 case nir_tex_src_lod:
383 /* XXX: Needs base level addition */
384 coords[next_coord++] =
385 ntq_get_src(c, instr->src[i].src, 0);
386
387 if (instr->op != nir_texop_txf &&
388 instr->op != nir_texop_tg4) {
389 p0_unpacked.disable_autolod_use_bias_only = true;
390 }
391 break;
392 case nir_tex_src_comparator:
393 coords[next_coord++] =
394 ntq_get_src(c, instr->src[i].src, 0);
395
396 p0_unpacked.shadow = true;
397 break;
398
399 case nir_tex_src_offset: {
400 nir_const_value *offset =
401 nir_src_as_const_value(instr->src[i].src);
402 p0_unpacked.texel_offset_for_s_coordinate =
403 offset->i32[0];
404
405 if (instr->coord_components >= 2)
406 p0_unpacked.texel_offset_for_t_coordinate =
407 offset->i32[1];
408
409 if (instr->coord_components >= 3)
410 p0_unpacked.texel_offset_for_r_coordinate =
411 offset->i32[2];
412 break;
413 }
414
415 default:
416 unreachable("unknown texture source");
417 }
418 }
419
420 uint32_t p0_packed;
421 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_pack(NULL,
422 (uint8_t *)&p0_packed,
423 &p0_unpacked);
424
425 /* There is no native support for GL texture rectangle coordinates, so
426 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
427 * 1]).
428 */
429 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
430 coords[0] = vir_FMUL(c, coords[0],
431 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_X,
432 unit));
433 coords[1] = vir_FMUL(c, coords[1],
434 vir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y,
435 unit));
436 }
437
438 struct qreg texture_u[] = {
439 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0_0 + unit, p0_packed),
440 vir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
441 };
442 uint32_t next_texture_u = 0;
443
444 for (int i = 0; i < next_coord; i++) {
445 struct qreg dst;
446
447 if (i == next_coord - 1)
448 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUL);
449 else
450 dst = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMU);
451
452 struct qinst *tmu = vir_MOV_dest(c, dst, coords[i]);
453
454 if (i < 2) {
455 tmu->has_implicit_uniform = true;
456 tmu->src[vir_get_implicit_uniform_src(tmu)] =
457 texture_u[next_texture_u++];
458 }
459 }
460
461 bool return_16 = (c->key->tex[unit].return_size == 16 ||
462 p0_unpacked.shadow);
463
464 struct qreg return_values[4];
465 for (int i = 0; i < c->key->tex[unit].return_channels; i++)
466 return_values[i] = vir_LDTMU(c);
467 /* Swizzling .zw of an RG texture should give undefined results, not
468 * crash the compiler.
469 */
470 for (int i = c->key->tex[unit].return_channels; i < 4; i++)
471 return_values[i] = c->undef;
472
473 for (int i = 0; i < nir_tex_instr_dest_size(instr); i++) {
474 struct qreg chan;
475
476 if (return_16) {
477 STATIC_ASSERT(PIPE_SWIZZLE_X == 0);
478 chan = return_values[i / 2];
479
480 enum v3d_qpu_input_unpack unpack;
481 if (i & 1)
482 unpack = V3D_QPU_UNPACK_H;
483 else
484 unpack = V3D_QPU_UNPACK_L;
485
486 chan = vir_FMOV(c, chan);
487 vir_set_unpack(c->defs[chan.index], 0, unpack);
488 } else {
489 chan = vir_MOV(c, return_values[i]);
490 }
491 ntq_store_dest(c, &instr->dest, i, chan);
492 }
493 }
494
495 static struct qreg
496 ntq_fsincos(struct v3d_compile *c, struct qreg src, bool is_cos)
497 {
498 struct qreg input = vir_FMUL(c, src, vir_uniform_f(c, 1.0f / M_PI));
499 if (is_cos)
500 input = vir_FADD(c, input, vir_uniform_f(c, 0.5));
501
502 struct qreg periods = vir_FROUND(c, input);
503 struct qreg sin_output = vir_SFU(c, V3D_QPU_WADDR_SIN,
504 vir_FSUB(c, input, periods));
505 return vir_XOR(c, sin_output, vir_SHL(c,
506 vir_FTOIN(c, periods),
507 vir_uniform_ui(c, -1)));
508 }
509
510 static struct qreg
511 ntq_fsign(struct v3d_compile *c, struct qreg src)
512 {
513 struct qreg t = vir_get_temp(c);
514
515 vir_MOV_dest(c, t, vir_uniform_f(c, 0.0));
516 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHZ);
517 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_f(c, 1.0));
518 vir_PF(c, vir_FMOV(c, src), V3D_QPU_PF_PUSHN);
519 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_f(c, -1.0));
520 return vir_MOV(c, t);
521 }
522
523 static struct qreg
524 ntq_isign(struct v3d_compile *c, struct qreg src)
525 {
526 struct qreg t = vir_get_temp(c);
527
528 vir_MOV_dest(c, t, vir_uniform_ui(c, 0));
529 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHZ);
530 vir_MOV_cond(c, V3D_QPU_COND_IFNA, t, vir_uniform_ui(c, 1));
531 vir_PF(c, vir_MOV(c, src), V3D_QPU_PF_PUSHN);
532 vir_MOV_cond(c, V3D_QPU_COND_IFA, t, vir_uniform_ui(c, -1));
533 return vir_MOV(c, t);
534 }
535
536 static void
537 emit_fragcoord_input(struct v3d_compile *c, int attr)
538 {
539 c->inputs[attr * 4 + 0] = vir_FXCD(c);
540 c->inputs[attr * 4 + 1] = vir_FYCD(c);
541 c->inputs[attr * 4 + 2] = c->payload_z;
542 c->inputs[attr * 4 + 3] = vir_SFU(c, V3D_QPU_WADDR_RECIP,
543 c->payload_w);
544 }
545
546 static struct qreg
547 emit_fragment_varying(struct v3d_compile *c, nir_variable *var,
548 uint8_t swizzle)
549 {
550 struct qreg vary = vir_reg(QFILE_VARY, ~0);
551 struct qreg r5 = vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R5);
552
553 /* For gl_PointCoord input or distance along a line, we'll be called
554 * with no nir_variable, and we don't count toward VPM size so we
555 * don't track an input slot.
556 */
557 if (!var) {
558 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
559 }
560
561 int i = c->num_inputs++;
562 c->input_slots[i] = v3d_slot_from_slot_and_component(var->data.location,
563 swizzle);
564
565 switch (var->data.interpolation) {
566 case INTERP_MODE_NONE:
567 /* If a gl_FrontColor or gl_BackColor input has no interp
568 * qualifier, then flag it for glShadeModel() handling by the
569 * driver.
570 */
571 switch (var->data.location) {
572 case VARYING_SLOT_COL0:
573 case VARYING_SLOT_COL1:
574 case VARYING_SLOT_BFC0:
575 case VARYING_SLOT_BFC1:
576 BITSET_SET(c->shade_model_flags, i);
577 break;
578 default:
579 break;
580 }
581 /* FALLTHROUGH */
582 case INTERP_MODE_SMOOTH:
583 if (var->data.centroid) {
584 return vir_FADD(c, vir_FMUL(c, vary,
585 c->payload_w_centroid), r5);
586 } else {
587 return vir_FADD(c, vir_FMUL(c, vary, c->payload_w), r5);
588 }
589 case INTERP_MODE_NOPERSPECTIVE:
590 /* C appears after the mov from the varying.
591 XXX: improve ldvary setup.
592 */
593 return vir_FADD(c, vir_MOV(c, vary), r5);
594 case INTERP_MODE_FLAT:
595 BITSET_SET(c->flat_shade_flags, i);
596 vir_MOV_dest(c, c->undef, vary);
597 return vir_MOV(c, r5);
598 default:
599 unreachable("Bad interp mode");
600 }
601 }
602
603 static void
604 emit_fragment_input(struct v3d_compile *c, int attr, nir_variable *var)
605 {
606 for (int i = 0; i < glsl_get_vector_elements(var->type); i++) {
607 c->inputs[attr * 4 + i] =
608 emit_fragment_varying(c, var, i);
609 }
610 }
611
612 static void
613 add_output(struct v3d_compile *c,
614 uint32_t decl_offset,
615 uint8_t slot,
616 uint8_t swizzle)
617 {
618 uint32_t old_array_size = c->outputs_array_size;
619 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
620 decl_offset + 1);
621
622 if (old_array_size != c->outputs_array_size) {
623 c->output_slots = reralloc(c,
624 c->output_slots,
625 struct v3d_varying_slot,
626 c->outputs_array_size);
627 }
628
629 c->output_slots[decl_offset] =
630 v3d_slot_from_slot_and_component(slot, swizzle);
631 }
632
633 static void
634 declare_uniform_range(struct v3d_compile *c, uint32_t start, uint32_t size)
635 {
636 unsigned array_id = c->num_ubo_ranges++;
637 if (array_id >= c->ubo_ranges_array_size) {
638 c->ubo_ranges_array_size = MAX2(c->ubo_ranges_array_size * 2,
639 array_id + 1);
640 c->ubo_ranges = reralloc(c, c->ubo_ranges,
641 struct v3d_ubo_range,
642 c->ubo_ranges_array_size);
643 c->ubo_range_used = reralloc(c, c->ubo_range_used,
644 bool,
645 c->ubo_ranges_array_size);
646 }
647
648 c->ubo_ranges[array_id].dst_offset = 0;
649 c->ubo_ranges[array_id].src_offset = start;
650 c->ubo_ranges[array_id].size = size;
651 c->ubo_range_used[array_id] = false;
652 }
653
654 /**
655 * If compare_instr is a valid comparison instruction, emits the
656 * compare_instr's comparison and returns the sel_instr's return value based
657 * on the compare_instr's result.
658 */
659 static bool
660 ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest,
661 nir_alu_instr *compare_instr,
662 nir_alu_instr *sel_instr)
663 {
664 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
665 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
666 bool cond_invert = false;
667
668 switch (compare_instr->op) {
669 case nir_op_feq:
670 case nir_op_seq:
671 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
672 break;
673 case nir_op_ieq:
674 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
675 break;
676
677 case nir_op_fne:
678 case nir_op_sne:
679 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ);
680 cond_invert = true;
681 break;
682 case nir_op_ine:
683 vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ);
684 cond_invert = true;
685 break;
686
687 case nir_op_fge:
688 case nir_op_sge:
689 vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC);
690 break;
691 case nir_op_ige:
692 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
693 cond_invert = true;
694 break;
695 case nir_op_uge:
696 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
697 cond_invert = true;
698 break;
699
700 case nir_op_slt:
701 case nir_op_flt:
702 vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN);
703 break;
704 case nir_op_ilt:
705 vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC);
706 break;
707 case nir_op_ult:
708 vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC);
709 break;
710
711 default:
712 return false;
713 }
714
715 enum v3d_qpu_cond cond = (cond_invert ?
716 V3D_QPU_COND_IFNA :
717 V3D_QPU_COND_IFA);
718
719 switch (sel_instr->op) {
720 case nir_op_seq:
721 case nir_op_sne:
722 case nir_op_sge:
723 case nir_op_slt:
724 *dest = vir_SEL(c, cond,
725 vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0));
726 break;
727
728 case nir_op_bcsel:
729 *dest = vir_SEL(c, cond,
730 ntq_get_alu_src(c, sel_instr, 1),
731 ntq_get_alu_src(c, sel_instr, 2));
732 break;
733
734 default:
735 *dest = vir_SEL(c, cond,
736 vir_uniform_ui(c, ~0), vir_uniform_ui(c, 0));
737 break;
738 }
739
740 /* Make the temporary for nir_store_dest(). */
741 *dest = vir_MOV(c, *dest);
742
743 return true;
744 }
745
746 /**
747 * Attempts to fold a comparison generating a boolean result into the
748 * condition code for selecting between two values, instead of comparing the
749 * boolean result against 0 to generate the condition code.
750 */
751 static struct qreg ntq_emit_bcsel(struct v3d_compile *c, nir_alu_instr *instr,
752 struct qreg *src)
753 {
754 if (!instr->src[0].src.is_ssa)
755 goto out;
756 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
757 goto out;
758 nir_alu_instr *compare =
759 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
760 if (!compare)
761 goto out;
762
763 struct qreg dest;
764 if (ntq_emit_comparison(c, &dest, compare, instr))
765 return dest;
766
767 out:
768 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
769 return vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA, src[1], src[2]));
770 }
771
772
773 static void
774 ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr)
775 {
776 /* This should always be lowered to ALU operations for V3D. */
777 assert(!instr->dest.saturate);
778
779 /* Vectors are special in that they have non-scalarized writemasks,
780 * and just take the first swizzle channel for each argument in order
781 * into each writemask channel.
782 */
783 if (instr->op == nir_op_vec2 ||
784 instr->op == nir_op_vec3 ||
785 instr->op == nir_op_vec4) {
786 struct qreg srcs[4];
787 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
788 srcs[i] = ntq_get_src(c, instr->src[i].src,
789 instr->src[i].swizzle[0]);
790 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
791 ntq_store_dest(c, &instr->dest.dest, i,
792 vir_MOV(c, srcs[i]));
793 return;
794 }
795
796 /* General case: We can just grab the one used channel per src. */
797 struct qreg src[nir_op_infos[instr->op].num_inputs];
798 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
799 src[i] = ntq_get_alu_src(c, instr, i);
800 }
801
802 struct qreg result;
803
804 switch (instr->op) {
805 case nir_op_fmov:
806 case nir_op_imov:
807 result = vir_MOV(c, src[0]);
808 break;
809
810 case nir_op_fneg:
811 result = vir_XOR(c, src[0], vir_uniform_ui(c, 1 << 31));
812 break;
813 case nir_op_ineg:
814 result = vir_NEG(c, src[0]);
815 break;
816
817 case nir_op_fmul:
818 result = vir_FMUL(c, src[0], src[1]);
819 break;
820 case nir_op_fadd:
821 result = vir_FADD(c, src[0], src[1]);
822 break;
823 case nir_op_fsub:
824 result = vir_FSUB(c, src[0], src[1]);
825 break;
826 case nir_op_fmin:
827 result = vir_FMIN(c, src[0], src[1]);
828 break;
829 case nir_op_fmax:
830 result = vir_FMAX(c, src[0], src[1]);
831 break;
832
833 case nir_op_f2i32:
834 result = vir_FTOIZ(c, src[0]);
835 break;
836 case nir_op_f2u32:
837 result = vir_FTOUZ(c, src[0]);
838 break;
839 case nir_op_i2f32:
840 result = vir_ITOF(c, src[0]);
841 break;
842 case nir_op_u2f32:
843 result = vir_UTOF(c, src[0]);
844 break;
845 case nir_op_b2f:
846 result = vir_AND(c, src[0], vir_uniform_f(c, 1.0));
847 break;
848 case nir_op_b2i:
849 result = vir_AND(c, src[0], vir_uniform_ui(c, 1));
850 break;
851 case nir_op_i2b:
852 case nir_op_f2b:
853 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
854 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
855 vir_uniform_ui(c, ~0),
856 vir_uniform_ui(c, 0)));
857 break;
858
859 case nir_op_iadd:
860 result = vir_ADD(c, src[0], src[1]);
861 break;
862 case nir_op_ushr:
863 result = vir_SHR(c, src[0], src[1]);
864 break;
865 case nir_op_isub:
866 result = vir_SUB(c, src[0], src[1]);
867 break;
868 case nir_op_ishr:
869 result = vir_ASR(c, src[0], src[1]);
870 break;
871 case nir_op_ishl:
872 result = vir_SHL(c, src[0], src[1]);
873 break;
874 case nir_op_imin:
875 result = vir_MIN(c, src[0], src[1]);
876 break;
877 case nir_op_umin:
878 result = vir_UMIN(c, src[0], src[1]);
879 break;
880 case nir_op_imax:
881 result = vir_MAX(c, src[0], src[1]);
882 break;
883 case nir_op_umax:
884 result = vir_UMAX(c, src[0], src[1]);
885 break;
886 case nir_op_iand:
887 result = vir_AND(c, src[0], src[1]);
888 break;
889 case nir_op_ior:
890 result = vir_OR(c, src[0], src[1]);
891 break;
892 case nir_op_ixor:
893 result = vir_XOR(c, src[0], src[1]);
894 break;
895 case nir_op_inot:
896 result = vir_NOT(c, src[0]);
897 break;
898
899 case nir_op_imul:
900 result = ntq_umul(c, src[0], src[1]);
901 break;
902
903 case nir_op_seq:
904 case nir_op_sne:
905 case nir_op_sge:
906 case nir_op_slt:
907 case nir_op_feq:
908 case nir_op_fne:
909 case nir_op_fge:
910 case nir_op_flt:
911 case nir_op_ieq:
912 case nir_op_ine:
913 case nir_op_ige:
914 case nir_op_uge:
915 case nir_op_ilt:
916 case nir_op_ult:
917 if (!ntq_emit_comparison(c, &result, instr, instr)) {
918 fprintf(stderr, "Bad comparison instruction\n");
919 }
920 break;
921
922 case nir_op_bcsel:
923 result = ntq_emit_bcsel(c, instr, src);
924 break;
925 case nir_op_fcsel:
926 vir_PF(c, src[0], V3D_QPU_PF_PUSHZ);
927 result = vir_MOV(c, vir_SEL(c, V3D_QPU_COND_IFNA,
928 src[1], src[2]));
929 break;
930
931 case nir_op_frcp:
932 result = vir_SFU(c, V3D_QPU_WADDR_RECIP, src[0]);
933 break;
934 case nir_op_frsq:
935 result = vir_SFU(c, V3D_QPU_WADDR_RSQRT, src[0]);
936 break;
937 case nir_op_fexp2:
938 result = vir_SFU(c, V3D_QPU_WADDR_EXP, src[0]);
939 break;
940 case nir_op_flog2:
941 result = vir_SFU(c, V3D_QPU_WADDR_LOG, src[0]);
942 break;
943
944 case nir_op_fceil:
945 result = vir_FCEIL(c, src[0]);
946 break;
947 case nir_op_ffloor:
948 result = vir_FFLOOR(c, src[0]);
949 break;
950 case nir_op_fround_even:
951 result = vir_FROUND(c, src[0]);
952 break;
953 case nir_op_ftrunc:
954 result = vir_FTRUNC(c, src[0]);
955 break;
956 case nir_op_ffract:
957 result = vir_FSUB(c, src[0], vir_FFLOOR(c, src[0]));
958 break;
959
960 case nir_op_fsin:
961 result = ntq_fsincos(c, src[0], false);
962 break;
963 case nir_op_fcos:
964 result = ntq_fsincos(c, src[0], true);
965 break;
966
967 case nir_op_fsign:
968 result = ntq_fsign(c, src[0]);
969 break;
970 case nir_op_isign:
971 result = ntq_isign(c, src[0]);
972 break;
973
974 case nir_op_fabs: {
975 result = vir_FMOV(c, src[0]);
976 vir_set_unpack(c->defs[result.index], 0, V3D_QPU_UNPACK_ABS);
977 break;
978 }
979
980 case nir_op_iabs:
981 result = vir_MAX(c, src[0],
982 vir_SUB(c, vir_uniform_ui(c, 0), src[0]));
983 break;
984
985 case nir_op_fddx:
986 case nir_op_fddx_coarse:
987 case nir_op_fddx_fine:
988 result = vir_FDX(c, src[0]);
989 break;
990
991 case nir_op_fddy:
992 case nir_op_fddy_coarse:
993 case nir_op_fddy_fine:
994 result = vir_FDY(c, src[0]);
995 break;
996
997 default:
998 fprintf(stderr, "unknown NIR ALU inst: ");
999 nir_print_instr(&instr->instr, stderr);
1000 fprintf(stderr, "\n");
1001 abort();
1002 }
1003
1004 /* We have a scalar result, so the instruction should only have a
1005 * single channel written to.
1006 */
1007 assert(util_is_power_of_two(instr->dest.write_mask));
1008 ntq_store_dest(c, &instr->dest.dest,
1009 ffs(instr->dest.write_mask) - 1, result);
1010 }
1011
1012 /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
1013 * specifier. They come from a register that's preloaded with 0xffffffff
1014 * (0xff gets you normal vec4 f16 RT0 writes), and when one is neaded the low
1015 * 8 bits are shifted off the bottom and 0xff shifted in from the top.
1016 */
1017 #define TLB_TYPE_F16_COLOR (3 << 6)
1018 #define TLB_TYPE_I32_COLOR (1 << 6)
1019 #define TLB_TYPE_F32_COLOR (0 << 6)
1020 #define TLB_RENDER_TARGET_SHIFT 3 /* Reversed! 7 = RT 0, 0 = RT 7. */
1021 #define TLB_SAMPLE_MODE_PER_SAMPLE (0 << 2)
1022 #define TLB_SAMPLE_MODE_PER_PIXEL (1 << 2)
1023 #define TLB_F16_SWAP_HI_LO (1 << 1)
1024 #define TLB_VEC_SIZE_4_F16 (1 << 0)
1025 #define TLB_VEC_SIZE_2_F16 (0 << 0)
1026 #define TLB_VEC_SIZE_MINUS_1_SHIFT 0
1027
1028 /* Triggers Z/Stencil testing, used when the shader state's "FS modifies Z"
1029 * flag is set.
1030 */
1031 #define TLB_TYPE_DEPTH ((2 << 6) | (0 << 4))
1032 #define TLB_DEPTH_TYPE_INVARIANT (0 << 2) /* Unmodified sideband input used */
1033 #define TLB_DEPTH_TYPE_PER_PIXEL (1 << 2) /* QPU result used */
1034
1035 /* Stencil is a single 32-bit write. */
1036 #define TLB_TYPE_STENCIL_ALPHA ((2 << 6) | (1 << 4))
1037
1038 static void
1039 emit_frag_end(struct v3d_compile *c)
1040 {
1041 /* XXX
1042 if (c->output_sample_mask_index != -1) {
1043 vir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1044 }
1045 */
1046
1047 if (c->output_position_index != -1) {
1048 struct qinst *inst = vir_MOV_dest(c,
1049 vir_reg(QFILE_TLBU, 0),
1050 c->outputs[c->output_position_index]);
1051
1052 inst->src[vir_get_implicit_uniform_src(inst)] =
1053 vir_uniform_ui(c,
1054 TLB_TYPE_DEPTH |
1055 TLB_DEPTH_TYPE_PER_PIXEL |
1056 0xffffff00);
1057 } else if (c->s->info.fs.uses_discard) {
1058 struct qinst *inst = vir_MOV_dest(c,
1059 vir_reg(QFILE_TLBU, 0),
1060 vir_reg(QFILE_NULL, 0));
1061
1062 inst->src[vir_get_implicit_uniform_src(inst)] =
1063 vir_uniform_ui(c,
1064 TLB_TYPE_DEPTH |
1065 TLB_DEPTH_TYPE_INVARIANT |
1066 0xffffff00);
1067 }
1068
1069 /* XXX: Performance improvement: Merge Z write and color writes TLB
1070 * uniform setup
1071 */
1072
1073 for (int rt = 0; rt < c->fs_key->nr_cbufs; rt++) {
1074 if (!c->output_color_var[rt])
1075 continue;
1076
1077 nir_variable *var = c->output_color_var[rt];
1078 struct qreg *color = &c->outputs[var->data.driver_location * 4];
1079 int num_components = glsl_get_vector_elements(var->type);
1080 uint32_t conf = 0xffffff00;
1081 struct qinst *inst;
1082
1083 conf |= TLB_SAMPLE_MODE_PER_PIXEL;
1084 conf |= (7 - rt) << TLB_RENDER_TARGET_SHIFT;
1085
1086 assert(num_components != 0);
1087 switch (glsl_get_base_type(var->type)) {
1088 case GLSL_TYPE_UINT:
1089 case GLSL_TYPE_INT:
1090 conf |= TLB_TYPE_I32_COLOR;
1091 conf |= ((num_components - 1) <<
1092 TLB_VEC_SIZE_MINUS_1_SHIFT);
1093
1094 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1095 inst->src[vir_get_implicit_uniform_src(inst)] =
1096 vir_uniform_ui(c, conf);
1097
1098 for (int i = 1; i < num_components; i++) {
1099 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1100 color[i]);
1101 }
1102 break;
1103
1104 default: {
1105 struct qreg r = color[0];
1106 struct qreg g = color[1];
1107 struct qreg b = color[2];
1108 struct qreg a = color[3];
1109
1110 if (c->fs_key->f32_color_rb) {
1111 conf |= TLB_TYPE_F32_COLOR;
1112 conf |= ((num_components - 1) <<
1113 TLB_VEC_SIZE_MINUS_1_SHIFT);
1114 } else {
1115 conf |= TLB_TYPE_F16_COLOR;
1116 conf |= TLB_F16_SWAP_HI_LO;
1117 if (num_components >= 3)
1118 conf |= TLB_VEC_SIZE_4_F16;
1119 else
1120 conf |= TLB_VEC_SIZE_2_F16;
1121 }
1122
1123 if (c->fs_key->swap_color_rb & (1 << rt)) {
1124 r = color[2];
1125 b = color[0];
1126 }
1127
1128 if (c->fs_key->f32_color_rb & (1 << rt)) {
1129 inst = vir_MOV_dest(c, vir_reg(QFILE_TLBU, 0), color[0]);
1130 inst->src[vir_get_implicit_uniform_src(inst)] =
1131 vir_uniform_ui(c, conf);
1132
1133 for (int i = 1; i < num_components; i++) {
1134 inst = vir_MOV_dest(c, vir_reg(QFILE_TLB, 0),
1135 color[i]);
1136 }
1137 } else {
1138 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), r, g);
1139 if (conf != ~0) {
1140 inst->dst.file = QFILE_TLBU;
1141 inst->src[vir_get_implicit_uniform_src(inst)] =
1142 vir_uniform_ui(c, conf);
1143 }
1144
1145 inst = vir_VFPACK_dest(c, vir_reg(QFILE_TLB, 0), b, a);
1146 }
1147 break;
1148 }
1149 }
1150 }
1151 }
1152
1153 static void
1154 emit_scaled_viewport_write(struct v3d_compile *c, struct qreg rcp_w)
1155 {
1156 for (int i = 0; i < 2; i++) {
1157 struct qreg coord = c->outputs[c->output_position_index + i];
1158 coord = vir_FMUL(c, coord,
1159 vir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i,
1160 0));
1161 coord = vir_FMUL(c, coord, rcp_w);
1162 vir_FTOIN_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1163 coord);
1164 }
1165
1166 }
1167
1168 static void
1169 emit_zs_write(struct v3d_compile *c, struct qreg rcp_w)
1170 {
1171 struct qreg zscale = vir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1172 struct qreg zoffset = vir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1173
1174 vir_FADD_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_VPM),
1175 vir_FMUL(c, vir_FMUL(c,
1176 c->outputs[c->output_position_index + 2],
1177 zscale),
1178 rcp_w),
1179 zoffset);
1180 }
1181
1182 static void
1183 emit_rcp_wc_write(struct v3d_compile *c, struct qreg rcp_w)
1184 {
1185 vir_VPM_WRITE(c, rcp_w);
1186 }
1187
1188 static void
1189 emit_point_size_write(struct v3d_compile *c)
1190 {
1191 struct qreg point_size;
1192
1193 if (c->output_point_size_index != -1)
1194 point_size = c->outputs[c->output_point_size_index];
1195 else
1196 point_size = vir_uniform_f(c, 1.0);
1197
1198 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1199 * BCM21553).
1200 */
1201 point_size = vir_FMAX(c, point_size, vir_uniform_f(c, .125));
1202
1203 vir_VPM_WRITE(c, point_size);
1204 }
1205
1206 static void
1207 emit_vpm_write_setup(struct v3d_compile *c)
1208 {
1209 uint32_t packed;
1210 struct V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP unpacked = {
1211 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_header,
1212
1213 .horiz = true,
1214 .laned = false,
1215 .segs = true,
1216 .stride = 1,
1217 .size = VPM_SETUP_SIZE_32_BIT,
1218 .addr = 0,
1219 };
1220
1221 V3D33_VPM_GENERIC_BLOCK_WRITE_SETUP_pack(NULL,
1222 (uint8_t *)&packed,
1223 &unpacked);
1224 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1225 }
1226
1227 static void
1228 emit_vert_end(struct v3d_compile *c)
1229 {
1230 struct qreg rcp_w = vir_SFU(c, V3D_QPU_WADDR_RECIP,
1231 c->outputs[c->output_position_index + 3]);
1232
1233 emit_vpm_write_setup(c);
1234
1235 if (c->vs_key->is_coord) {
1236 for (int i = 0; i < 4; i++)
1237 vir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1238 emit_scaled_viewport_write(c, rcp_w);
1239 if (c->vs_key->per_vertex_point_size) {
1240 emit_point_size_write(c);
1241 /* emit_rcp_wc_write(c, rcp_w); */
1242 }
1243 /* XXX: Z-only rendering */
1244 if (0)
1245 emit_zs_write(c, rcp_w);
1246 } else {
1247 emit_scaled_viewport_write(c, rcp_w);
1248 emit_zs_write(c, rcp_w);
1249 emit_rcp_wc_write(c, rcp_w);
1250 if (c->vs_key->per_vertex_point_size)
1251 emit_point_size_write(c);
1252 }
1253
1254 for (int i = 0; i < c->vs_key->num_fs_inputs; i++) {
1255 struct v3d_varying_slot input = c->vs_key->fs_inputs[i];
1256 int j;
1257
1258 for (j = 0; j < c->num_outputs; j++) {
1259 struct v3d_varying_slot output = c->output_slots[j];
1260
1261 if (!memcmp(&input, &output, sizeof(input))) {
1262 vir_VPM_WRITE(c, c->outputs[j]);
1263 break;
1264 }
1265 }
1266 /* Emit padding if we didn't find a declared VS output for
1267 * this FS input.
1268 */
1269 if (j == c->num_outputs)
1270 vir_VPM_WRITE(c, vir_uniform_f(c, 0.0));
1271 }
1272 }
1273
1274 void
1275 v3d_optimize_nir(struct nir_shader *s)
1276 {
1277 bool progress;
1278
1279 do {
1280 progress = false;
1281
1282 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1283 NIR_PASS(progress, s, nir_lower_alu_to_scalar);
1284 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1285 NIR_PASS(progress, s, nir_copy_prop);
1286 NIR_PASS(progress, s, nir_opt_remove_phis);
1287 NIR_PASS(progress, s, nir_opt_dce);
1288 NIR_PASS(progress, s, nir_opt_dead_cf);
1289 NIR_PASS(progress, s, nir_opt_cse);
1290 NIR_PASS(progress, s, nir_opt_peephole_select, 8);
1291 NIR_PASS(progress, s, nir_opt_algebraic);
1292 NIR_PASS(progress, s, nir_opt_constant_folding);
1293 NIR_PASS(progress, s, nir_opt_undef);
1294 } while (progress);
1295 }
1296
1297 static int
1298 driver_location_compare(const void *in_a, const void *in_b)
1299 {
1300 const nir_variable *const *a = in_a;
1301 const nir_variable *const *b = in_b;
1302
1303 return (*a)->data.driver_location - (*b)->data.driver_location;
1304 }
1305
1306 static struct qreg
1307 ntq_emit_vpm_read(struct v3d_compile *c,
1308 uint32_t *num_components_queued,
1309 uint32_t *remaining,
1310 uint32_t vpm_index)
1311 {
1312 struct qreg vpm = vir_reg(QFILE_VPM, vpm_index);
1313
1314 if (*num_components_queued != 0) {
1315 (*num_components_queued)--;
1316 c->num_inputs++;
1317 return vir_MOV(c, vpm);
1318 }
1319
1320 uint32_t num_components = MIN2(*remaining, 32);
1321
1322 struct V3D33_VPM_GENERIC_BLOCK_READ_SETUP unpacked = {
1323 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_header,
1324
1325 .horiz = true,
1326 .laned = false,
1327 /* If the field is 0, that means a read count of 32. */
1328 .num = num_components & 31,
1329 .segs = true,
1330 .stride = 1,
1331 .size = VPM_SETUP_SIZE_32_BIT,
1332 .addr = c->num_inputs,
1333 };
1334
1335 uint32_t packed;
1336 V3D33_VPM_GENERIC_BLOCK_READ_SETUP_pack(NULL,
1337 (uint8_t *)&packed,
1338 &unpacked);
1339 vir_VPMSETUP(c, vir_uniform_ui(c, packed));
1340
1341 *num_components_queued = num_components - 1;
1342 *remaining -= num_components;
1343 c->num_inputs++;
1344
1345 return vir_MOV(c, vpm);
1346 }
1347
1348 static void
1349 ntq_setup_inputs(struct v3d_compile *c)
1350 {
1351 unsigned num_entries = 0;
1352 unsigned num_components = 0;
1353 nir_foreach_variable(var, &c->s->inputs) {
1354 num_entries++;
1355 num_components += glsl_get_components(var->type);
1356 }
1357
1358 nir_variable *vars[num_entries];
1359
1360 unsigned i = 0;
1361 nir_foreach_variable(var, &c->s->inputs)
1362 vars[i++] = var;
1363
1364 /* Sort the variables so that we emit the input setup in
1365 * driver_location order. This is required for VPM reads, whose data
1366 * is fetched into the VPM in driver_location (TGSI register index)
1367 * order.
1368 */
1369 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1370
1371 uint32_t vpm_components_queued = 0;
1372 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1373 bool uses_iid = c->s->info.system_values_read &
1374 (1ull << SYSTEM_VALUE_INSTANCE_ID);
1375 bool uses_vid = c->s->info.system_values_read &
1376 (1ull << SYSTEM_VALUE_VERTEX_ID);
1377
1378 num_components += uses_iid;
1379 num_components += uses_vid;
1380
1381 if (uses_iid) {
1382 c->iid = ntq_emit_vpm_read(c, &vpm_components_queued,
1383 &num_components, ~0);
1384 }
1385
1386 if (uses_vid) {
1387 c->vid = ntq_emit_vpm_read(c, &vpm_components_queued,
1388 &num_components, ~0);
1389 }
1390 }
1391
1392 for (unsigned i = 0; i < num_entries; i++) {
1393 nir_variable *var = vars[i];
1394 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1395 unsigned loc = var->data.driver_location;
1396
1397 assert(array_len == 1);
1398 (void)array_len;
1399 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1400 (loc + 1) * 4);
1401
1402 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1403 if (var->data.location == VARYING_SLOT_POS) {
1404 emit_fragcoord_input(c, loc);
1405 } else if (var->data.location == VARYING_SLOT_PNTC ||
1406 (var->data.location >= VARYING_SLOT_VAR0 &&
1407 (c->fs_key->point_sprite_mask &
1408 (1 << (var->data.location -
1409 VARYING_SLOT_VAR0))))) {
1410 c->inputs[loc * 4 + 0] = c->point_x;
1411 c->inputs[loc * 4 + 1] = c->point_y;
1412 } else {
1413 emit_fragment_input(c, loc, var);
1414 }
1415 } else {
1416 int var_components = glsl_get_components(var->type);
1417
1418 for (int i = 0; i < var_components; i++) {
1419 c->inputs[loc * 4 + i] =
1420 ntq_emit_vpm_read(c,
1421 &vpm_components_queued,
1422 &num_components,
1423 loc * 4 + i);
1424
1425 }
1426 c->vattr_sizes[loc] = var_components;
1427 }
1428 }
1429
1430 if (c->s->info.stage == MESA_SHADER_VERTEX) {
1431 assert(vpm_components_queued == 0);
1432 assert(num_components == 0);
1433 }
1434 }
1435
1436 static void
1437 ntq_setup_outputs(struct v3d_compile *c)
1438 {
1439 nir_foreach_variable(var, &c->s->outputs) {
1440 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1441 unsigned loc = var->data.driver_location * 4;
1442
1443 assert(array_len == 1);
1444 (void)array_len;
1445
1446 for (int i = 0; i < 4; i++)
1447 add_output(c, loc + i, var->data.location, i);
1448
1449 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1450 switch (var->data.location) {
1451 case FRAG_RESULT_COLOR:
1452 c->output_color_var[0] = var;
1453 c->output_color_var[1] = var;
1454 c->output_color_var[2] = var;
1455 c->output_color_var[3] = var;
1456 break;
1457 case FRAG_RESULT_DATA0:
1458 case FRAG_RESULT_DATA1:
1459 case FRAG_RESULT_DATA2:
1460 case FRAG_RESULT_DATA3:
1461 c->output_color_var[var->data.location -
1462 FRAG_RESULT_DATA0] = var;
1463 break;
1464 case FRAG_RESULT_DEPTH:
1465 c->output_position_index = loc;
1466 break;
1467 case FRAG_RESULT_SAMPLE_MASK:
1468 c->output_sample_mask_index = loc;
1469 break;
1470 }
1471 } else {
1472 switch (var->data.location) {
1473 case VARYING_SLOT_POS:
1474 c->output_position_index = loc;
1475 break;
1476 case VARYING_SLOT_PSIZ:
1477 c->output_point_size_index = loc;
1478 break;
1479 }
1480 }
1481 }
1482 }
1483
1484 static void
1485 ntq_setup_uniforms(struct v3d_compile *c)
1486 {
1487 nir_foreach_variable(var, &c->s->uniforms) {
1488 uint32_t vec4_count = glsl_count_attribute_slots(var->type,
1489 false);
1490 unsigned vec4_size = 4 * sizeof(float);
1491
1492 declare_uniform_range(c, var->data.driver_location * vec4_size,
1493 vec4_count * vec4_size);
1494
1495 }
1496 }
1497
1498 /**
1499 * Sets up the mapping from nir_register to struct qreg *.
1500 *
1501 * Each nir_register gets a struct qreg per 32-bit component being stored.
1502 */
1503 static void
1504 ntq_setup_registers(struct v3d_compile *c, struct exec_list *list)
1505 {
1506 foreach_list_typed(nir_register, nir_reg, node, list) {
1507 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1508 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1509 array_len *
1510 nir_reg->num_components);
1511
1512 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1513
1514 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1515 qregs[i] = vir_get_temp(c);
1516 }
1517 }
1518
1519 static void
1520 ntq_emit_load_const(struct v3d_compile *c, nir_load_const_instr *instr)
1521 {
1522 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1523 for (int i = 0; i < instr->def.num_components; i++)
1524 qregs[i] = vir_uniform_ui(c, instr->value.u32[i]);
1525
1526 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1527 }
1528
1529 static void
1530 ntq_emit_ssa_undef(struct v3d_compile *c, nir_ssa_undef_instr *instr)
1531 {
1532 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1533
1534 /* VIR needs there to be *some* value, so pick 0 (same as for
1535 * ntq_setup_registers().
1536 */
1537 for (int i = 0; i < instr->def.num_components; i++)
1538 qregs[i] = vir_uniform_ui(c, 0);
1539 }
1540
1541 static void
1542 ntq_emit_intrinsic(struct v3d_compile *c, nir_intrinsic_instr *instr)
1543 {
1544 nir_const_value *const_offset;
1545 unsigned offset;
1546
1547 switch (instr->intrinsic) {
1548 case nir_intrinsic_load_uniform:
1549 assert(instr->num_components == 1);
1550 const_offset = nir_src_as_const_value(instr->src[0]);
1551 if (const_offset) {
1552 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1553 assert(offset % 4 == 0);
1554 /* We need dwords */
1555 offset = offset / 4;
1556 ntq_store_dest(c, &instr->dest, 0,
1557 vir_uniform(c, QUNIFORM_UNIFORM,
1558 offset));
1559 } else {
1560 ntq_store_dest(c, &instr->dest, 0,
1561 indirect_uniform_load(c, instr));
1562 }
1563 break;
1564
1565 case nir_intrinsic_load_ubo:
1566 for (int i = 0; i < instr->num_components; i++) {
1567 int ubo = nir_src_as_const_value(instr->src[0])->u32[0];
1568
1569 /* Adjust for where we stored the TGSI register base. */
1570 vir_ADD_dest(c,
1571 vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_TMUA),
1572 vir_uniform(c, QUNIFORM_UBO_ADDR, 1 + ubo),
1573 vir_ADD(c,
1574 ntq_get_src(c, instr->src[1], 0),
1575 vir_uniform_ui(c, i * 4)));
1576
1577 ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
1578 }
1579 break;
1580
1581 const_offset = nir_src_as_const_value(instr->src[0]);
1582 if (const_offset) {
1583 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1584 assert(offset % 4 == 0);
1585 /* We need dwords */
1586 offset = offset / 4;
1587 ntq_store_dest(c, &instr->dest, 0,
1588 vir_uniform(c, QUNIFORM_UNIFORM,
1589 offset));
1590 } else {
1591 ntq_store_dest(c, &instr->dest, 0,
1592 indirect_uniform_load(c, instr));
1593 }
1594 break;
1595
1596 case nir_intrinsic_load_user_clip_plane:
1597 for (int i = 0; i < instr->num_components; i++) {
1598 ntq_store_dest(c, &instr->dest, i,
1599 vir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1600 nir_intrinsic_ucp_id(instr) *
1601 4 + i));
1602 }
1603 break;
1604
1605 case nir_intrinsic_load_alpha_ref_float:
1606 ntq_store_dest(c, &instr->dest, 0,
1607 vir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1608 break;
1609
1610 case nir_intrinsic_load_sample_mask_in:
1611 ntq_store_dest(c, &instr->dest, 0,
1612 vir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1613 break;
1614
1615 case nir_intrinsic_load_front_face:
1616 /* The register contains 0 (front) or 1 (back), and we need to
1617 * turn it into a NIR bool where true means front.
1618 */
1619 ntq_store_dest(c, &instr->dest, 0,
1620 vir_ADD(c,
1621 vir_uniform_ui(c, -1),
1622 vir_REVF(c)));
1623 break;
1624
1625 case nir_intrinsic_load_instance_id:
1626 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->iid));
1627 break;
1628
1629 case nir_intrinsic_load_vertex_id:
1630 ntq_store_dest(c, &instr->dest, 0, vir_MOV(c, c->vid));
1631 break;
1632
1633 case nir_intrinsic_load_input:
1634 const_offset = nir_src_as_const_value(instr->src[0]);
1635 assert(const_offset && "v3d doesn't support indirect inputs");
1636 for (int i = 0; i < instr->num_components; i++) {
1637 offset = nir_intrinsic_base(instr) + const_offset->u32[0];
1638 int comp = nir_intrinsic_component(instr) + i;
1639 ntq_store_dest(c, &instr->dest, i,
1640 vir_MOV(c, c->inputs[offset * 4 + comp]));
1641 }
1642 break;
1643
1644 case nir_intrinsic_store_output:
1645 const_offset = nir_src_as_const_value(instr->src[1]);
1646 assert(const_offset && "v3d doesn't support indirect outputs");
1647 offset = ((nir_intrinsic_base(instr) +
1648 const_offset->u32[0]) * 4 +
1649 nir_intrinsic_component(instr));
1650
1651 for (int i = 0; i < instr->num_components; i++) {
1652 c->outputs[offset + i] =
1653 vir_MOV(c, ntq_get_src(c, instr->src[0], i));
1654 }
1655 c->num_outputs = MAX2(c->num_outputs,
1656 offset + instr->num_components);
1657 break;
1658
1659 case nir_intrinsic_discard:
1660 if (c->execute.file != QFILE_NULL) {
1661 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1662 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1663 vir_uniform_ui(c, 0)),
1664 V3D_QPU_COND_IFA);
1665 } else {
1666 vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1667 vir_uniform_ui(c, 0));
1668 }
1669 break;
1670
1671 case nir_intrinsic_discard_if: {
1672 /* true (~0) if we're discarding */
1673 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1674
1675 if (c->execute.file != QFILE_NULL) {
1676 /* execute == 0 means the channel is active. Invert
1677 * the condition so that we can use zero as "executing
1678 * and discarding."
1679 */
1680 vir_PF(c, vir_AND(c, c->execute, vir_NOT(c, cond)),
1681 V3D_QPU_PF_PUSHZ);
1682 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1683 vir_uniform_ui(c, 0)),
1684 V3D_QPU_COND_IFA);
1685 } else {
1686 vir_PF(c, cond, V3D_QPU_PF_PUSHZ);
1687 vir_set_cond(vir_SETMSF_dest(c, vir_reg(QFILE_NULL, 0),
1688 vir_uniform_ui(c, 0)),
1689 V3D_QPU_COND_IFNA);
1690 }
1691
1692 break;
1693 }
1694
1695 default:
1696 fprintf(stderr, "Unknown intrinsic: ");
1697 nir_print_instr(&instr->instr, stderr);
1698 fprintf(stderr, "\n");
1699 break;
1700 }
1701 }
1702
1703 /* Clears (activates) the execute flags for any channels whose jump target
1704 * matches this block.
1705 */
1706 static void
1707 ntq_activate_execute_for_block(struct v3d_compile *c)
1708 {
1709 vir_PF(c, vir_SUB(c, c->execute, vir_uniform_ui(c, c->cur_block->index)),
1710 V3D_QPU_PF_PUSHZ);
1711
1712 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1713 }
1714
1715 static void
1716 ntq_emit_if(struct v3d_compile *c, nir_if *if_stmt)
1717 {
1718 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1719 bool empty_else_block =
1720 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1721 exec_list_is_empty(&nir_else_block->instr_list));
1722
1723 struct qblock *then_block = vir_new_block(c);
1724 struct qblock *after_block = vir_new_block(c);
1725 struct qblock *else_block;
1726 if (empty_else_block)
1727 else_block = after_block;
1728 else
1729 else_block = vir_new_block(c);
1730
1731 bool was_top_level = false;
1732 if (c->execute.file == QFILE_NULL) {
1733 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1734 was_top_level = true;
1735 }
1736
1737 /* Set A for executing (execute == 0) and jumping (if->condition ==
1738 * 0) channels, and then update execute flags for those to point to
1739 * the ELSE block.
1740 */
1741 vir_PF(c, vir_OR(c,
1742 c->execute,
1743 ntq_get_src(c, if_stmt->condition, 0)),
1744 V3D_QPU_PF_PUSHZ);
1745 vir_MOV_cond(c, V3D_QPU_COND_IFA,
1746 c->execute,
1747 vir_uniform_ui(c, else_block->index));
1748
1749 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1750 * through.
1751 */
1752 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1753 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLNA);
1754 vir_link_blocks(c->cur_block, else_block);
1755 vir_link_blocks(c->cur_block, then_block);
1756
1757 /* Process the THEN block. */
1758 vir_set_emit_block(c, then_block);
1759 ntq_emit_cf_list(c, &if_stmt->then_list);
1760
1761 if (!empty_else_block) {
1762 /* Handle the end of the THEN block. First, all currently
1763 * active channels update their execute flags to point to
1764 * ENDIF
1765 */
1766 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1767 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1768 vir_uniform_ui(c, after_block->index));
1769
1770 /* If everything points at ENDIF, then jump there immediately. */
1771 vir_PF(c, vir_SUB(c, c->execute,
1772 vir_uniform_ui(c, after_block->index)),
1773 V3D_QPU_PF_PUSHZ);
1774 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ALLA);
1775 vir_link_blocks(c->cur_block, after_block);
1776 vir_link_blocks(c->cur_block, else_block);
1777
1778 vir_set_emit_block(c, else_block);
1779 ntq_activate_execute_for_block(c);
1780 ntq_emit_cf_list(c, &if_stmt->else_list);
1781 }
1782
1783 vir_link_blocks(c->cur_block, after_block);
1784
1785 vir_set_emit_block(c, after_block);
1786 if (was_top_level)
1787 c->execute = c->undef;
1788 else
1789 ntq_activate_execute_for_block(c);
1790 }
1791
1792 static void
1793 ntq_emit_jump(struct v3d_compile *c, nir_jump_instr *jump)
1794 {
1795 switch (jump->type) {
1796 case nir_jump_break:
1797 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1798 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1799 vir_uniform_ui(c, c->loop_break_block->index));
1800 break;
1801
1802 case nir_jump_continue:
1803 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1804 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute,
1805 vir_uniform_ui(c, c->loop_cont_block->index));
1806 break;
1807
1808 case nir_jump_return:
1809 unreachable("All returns shouold be lowered\n");
1810 }
1811 }
1812
1813 static void
1814 ntq_emit_instr(struct v3d_compile *c, nir_instr *instr)
1815 {
1816 switch (instr->type) {
1817 case nir_instr_type_alu:
1818 ntq_emit_alu(c, nir_instr_as_alu(instr));
1819 break;
1820
1821 case nir_instr_type_intrinsic:
1822 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
1823 break;
1824
1825 case nir_instr_type_load_const:
1826 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
1827 break;
1828
1829 case nir_instr_type_ssa_undef:
1830 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
1831 break;
1832
1833 case nir_instr_type_tex:
1834 ntq_emit_tex(c, nir_instr_as_tex(instr));
1835 break;
1836
1837 case nir_instr_type_jump:
1838 ntq_emit_jump(c, nir_instr_as_jump(instr));
1839 break;
1840
1841 default:
1842 fprintf(stderr, "Unknown NIR instr type: ");
1843 nir_print_instr(instr, stderr);
1844 fprintf(stderr, "\n");
1845 abort();
1846 }
1847 }
1848
1849 static void
1850 ntq_emit_block(struct v3d_compile *c, nir_block *block)
1851 {
1852 nir_foreach_instr(instr, block) {
1853 ntq_emit_instr(c, instr);
1854 }
1855 }
1856
1857 static void ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list);
1858
1859 static void
1860 ntq_emit_loop(struct v3d_compile *c, nir_loop *loop)
1861 {
1862 bool was_top_level = false;
1863 if (c->execute.file == QFILE_NULL) {
1864 c->execute = vir_MOV(c, vir_uniform_ui(c, 0));
1865 was_top_level = true;
1866 }
1867
1868 struct qblock *save_loop_cont_block = c->loop_cont_block;
1869 struct qblock *save_loop_break_block = c->loop_break_block;
1870
1871 c->loop_cont_block = vir_new_block(c);
1872 c->loop_break_block = vir_new_block(c);
1873
1874 vir_link_blocks(c->cur_block, c->loop_cont_block);
1875 vir_set_emit_block(c, c->loop_cont_block);
1876 ntq_activate_execute_for_block(c);
1877
1878 ntq_emit_cf_list(c, &loop->body);
1879
1880 /* Re-enable any previous continues now, so our ANYA check below
1881 * works.
1882 *
1883 * XXX: Use the .ORZ flags update, instead.
1884 */
1885 vir_PF(c, vir_SUB(c,
1886 c->execute,
1887 vir_uniform_ui(c, c->loop_cont_block->index)),
1888 V3D_QPU_PF_PUSHZ);
1889 vir_MOV_cond(c, V3D_QPU_COND_IFA, c->execute, vir_uniform_ui(c, 0));
1890
1891 vir_PF(c, c->execute, V3D_QPU_PF_PUSHZ);
1892
1893 vir_BRANCH(c, V3D_QPU_BRANCH_COND_ANYA);
1894 vir_link_blocks(c->cur_block, c->loop_cont_block);
1895 vir_link_blocks(c->cur_block, c->loop_break_block);
1896
1897 vir_set_emit_block(c, c->loop_break_block);
1898 if (was_top_level)
1899 c->execute = c->undef;
1900 else
1901 ntq_activate_execute_for_block(c);
1902
1903 c->loop_break_block = save_loop_break_block;
1904 c->loop_cont_block = save_loop_cont_block;
1905 }
1906
1907 static void
1908 ntq_emit_function(struct v3d_compile *c, nir_function_impl *func)
1909 {
1910 fprintf(stderr, "FUNCTIONS not handled.\n");
1911 abort();
1912 }
1913
1914 static void
1915 ntq_emit_cf_list(struct v3d_compile *c, struct exec_list *list)
1916 {
1917 foreach_list_typed(nir_cf_node, node, node, list) {
1918 switch (node->type) {
1919 case nir_cf_node_block:
1920 ntq_emit_block(c, nir_cf_node_as_block(node));
1921 break;
1922
1923 case nir_cf_node_if:
1924 ntq_emit_if(c, nir_cf_node_as_if(node));
1925 break;
1926
1927 case nir_cf_node_loop:
1928 ntq_emit_loop(c, nir_cf_node_as_loop(node));
1929 break;
1930
1931 case nir_cf_node_function:
1932 ntq_emit_function(c, nir_cf_node_as_function(node));
1933 break;
1934
1935 default:
1936 fprintf(stderr, "Unknown NIR node type\n");
1937 abort();
1938 }
1939 }
1940 }
1941
1942 static void
1943 ntq_emit_impl(struct v3d_compile *c, nir_function_impl *impl)
1944 {
1945 ntq_setup_registers(c, &impl->registers);
1946 ntq_emit_cf_list(c, &impl->body);
1947 }
1948
1949 static void
1950 nir_to_vir(struct v3d_compile *c)
1951 {
1952 if (c->s->info.stage == MESA_SHADER_FRAGMENT) {
1953 c->payload_w = vir_MOV(c, vir_reg(QFILE_REG, 0));
1954 c->payload_w_centroid = vir_MOV(c, vir_reg(QFILE_REG, 1));
1955 c->payload_z = vir_MOV(c, vir_reg(QFILE_REG, 2));
1956
1957 if (c->fs_key->is_points) {
1958 c->point_x = emit_fragment_varying(c, NULL, 0);
1959 c->point_y = emit_fragment_varying(c, NULL, 0);
1960 } else if (c->fs_key->is_lines) {
1961 c->line_x = emit_fragment_varying(c, NULL, 0);
1962 }
1963 }
1964
1965 ntq_setup_inputs(c);
1966 ntq_setup_outputs(c);
1967 ntq_setup_uniforms(c);
1968 ntq_setup_registers(c, &c->s->registers);
1969
1970 /* Find the main function and emit the body. */
1971 nir_foreach_function(function, c->s) {
1972 assert(strcmp(function->name, "main") == 0);
1973 assert(function->impl);
1974 ntq_emit_impl(c, function->impl);
1975 }
1976 }
1977
1978 const nir_shader_compiler_options v3d_nir_options = {
1979 .lower_extract_byte = true,
1980 .lower_extract_word = true,
1981 .lower_bitfield_insert = true,
1982 .lower_bitfield_extract = true,
1983 .lower_pack_unorm_2x16 = true,
1984 .lower_pack_snorm_2x16 = true,
1985 .lower_pack_unorm_4x8 = true,
1986 .lower_pack_snorm_4x8 = true,
1987 .lower_unpack_unorm_4x8 = true,
1988 .lower_unpack_snorm_4x8 = true,
1989 .lower_fdiv = true,
1990 .lower_ffma = true,
1991 .lower_flrp32 = true,
1992 .lower_fpow = true,
1993 .lower_fsat = true,
1994 .lower_fsqrt = true,
1995 .native_integers = true,
1996 };
1997
1998
1999 #if 0
2000 static int
2001 count_nir_instrs(nir_shader *nir)
2002 {
2003 int count = 0;
2004 nir_foreach_function(function, nir) {
2005 if (!function->impl)
2006 continue;
2007 nir_foreach_block(block, function->impl) {
2008 nir_foreach_instr(instr, block)
2009 count++;
2010 }
2011 }
2012 return count;
2013 }
2014 #endif
2015
2016 void
2017 v3d_nir_to_vir(struct v3d_compile *c)
2018 {
2019 if (V3D_DEBUG & (V3D_DEBUG_NIR |
2020 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2021 fprintf(stderr, "%s prog %d/%d NIR:\n",
2022 vir_get_stage_name(c),
2023 c->program_id, c->variant_id);
2024 nir_print_shader(c->s, stderr);
2025 }
2026
2027 nir_to_vir(c);
2028
2029 switch (c->s->info.stage) {
2030 case MESA_SHADER_FRAGMENT:
2031 emit_frag_end(c);
2032 break;
2033 case MESA_SHADER_VERTEX:
2034 emit_vert_end(c);
2035 break;
2036 default:
2037 unreachable("bad stage");
2038 }
2039
2040 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2041 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2042 fprintf(stderr, "%s prog %d/%d pre-opt VIR:\n",
2043 vir_get_stage_name(c),
2044 c->program_id, c->variant_id);
2045 vir_dump(c);
2046 fprintf(stderr, "\n");
2047 }
2048
2049 vir_optimize(c);
2050 vir_lower_uniforms(c);
2051
2052 /* XXX: vir_schedule_instructions(c); */
2053
2054 if (V3D_DEBUG & (V3D_DEBUG_VIR |
2055 v3d_debug_flag_for_shader_stage(c->s->info.stage))) {
2056 fprintf(stderr, "%s prog %d/%d VIR:\n",
2057 vir_get_stage_name(c),
2058 c->program_id, c->variant_id);
2059 vir_dump(c);
2060 fprintf(stderr, "\n");
2061 }
2062
2063 v3d_vir_to_qpu(c);
2064 }