2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2017 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
37 #include "qpu/qpu_disasm.h"
38 #include "v3d_compiler.h"
39 #include "util/ralloc.h"
43 struct schedule_node_child
;
45 struct schedule_node
{
46 struct list_head link
;
48 struct schedule_node_child
*children
;
50 uint32_t child_array_size
;
51 uint32_t parent_count
;
53 /* Longest cycles + instruction_latency() of any parent of this node. */
54 uint32_t unblocked_time
;
57 * Minimum number of cycles from scheduling this instruction until the
58 * end of the program, based on the slowest dependency chain through
64 * cycles between this instruction being scheduled and when its result
70 struct schedule_node_child
{
71 struct schedule_node
*node
;
72 bool write_after_read
;
75 /* When walking the instructions in reverse, we need to swap before/after in
78 enum direction
{ F
, R
};
80 struct schedule_state
{
81 const struct v3d_device_info
*devinfo
;
82 struct schedule_node
*last_r
[6];
83 struct schedule_node
*last_rf
[64];
84 struct schedule_node
*last_sf
;
85 struct schedule_node
*last_vpm_read
;
86 struct schedule_node
*last_tmu_write
;
87 struct schedule_node
*last_tmu_config
;
88 struct schedule_node
*last_tlb
;
89 struct schedule_node
*last_vpm
;
90 struct schedule_node
*last_unif
;
91 struct schedule_node
*last_rtop
;
93 /* Estimated cycle when the current instruction would start. */
98 add_dep(struct schedule_state
*state
,
99 struct schedule_node
*before
,
100 struct schedule_node
*after
,
103 bool write_after_read
= !write
&& state
->dir
== R
;
105 if (!before
|| !after
)
108 assert(before
!= after
);
110 if (state
->dir
== R
) {
111 struct schedule_node
*t
= before
;
116 for (int i
= 0; i
< before
->child_count
; i
++) {
117 if (before
->children
[i
].node
== after
&&
118 (before
->children
[i
].write_after_read
== write_after_read
)) {
123 if (before
->child_array_size
<= before
->child_count
) {
124 before
->child_array_size
= MAX2(before
->child_array_size
* 2, 16);
125 before
->children
= reralloc(before
, before
->children
,
126 struct schedule_node_child
,
127 before
->child_array_size
);
130 before
->children
[before
->child_count
].node
= after
;
131 before
->children
[before
->child_count
].write_after_read
=
133 before
->child_count
++;
134 after
->parent_count
++;
138 add_read_dep(struct schedule_state
*state
,
139 struct schedule_node
*before
,
140 struct schedule_node
*after
)
142 add_dep(state
, before
, after
, false);
146 add_write_dep(struct schedule_state
*state
,
147 struct schedule_node
**before
,
148 struct schedule_node
*after
)
150 add_dep(state
, *before
, after
, true);
155 qpu_inst_is_tlb(const struct v3d_qpu_instr
*inst
)
157 if (inst
->type
!= V3D_QPU_INSTR_TYPE_ALU
)
160 if (inst
->alu
.add
.magic_write
&&
161 (inst
->alu
.add
.waddr
== V3D_QPU_WADDR_TLB
||
162 inst
->alu
.add
.waddr
== V3D_QPU_WADDR_TLBU
))
165 if (inst
->alu
.mul
.magic_write
&&
166 (inst
->alu
.mul
.waddr
== V3D_QPU_WADDR_TLB
||
167 inst
->alu
.mul
.waddr
== V3D_QPU_WADDR_TLBU
))
174 process_mux_deps(struct schedule_state
*state
, struct schedule_node
*n
,
175 enum v3d_qpu_mux mux
)
179 add_read_dep(state
, state
->last_rf
[n
->inst
->qpu
.raddr_a
], n
);
182 add_read_dep(state
, state
->last_rf
[n
->inst
->qpu
.raddr_b
], n
);
185 add_read_dep(state
, state
->last_r
[mux
- V3D_QPU_MUX_R0
], n
);
192 process_waddr_deps(struct schedule_state
*state
, struct schedule_node
*n
,
193 uint32_t waddr
, bool magic
)
196 add_write_dep(state
, &state
->last_rf
[waddr
], n
);
197 } else if (v3d_qpu_magic_waddr_is_tmu(waddr
)) {
198 /* XXX perf: For V3D 4.x, we could reorder TMU writes other
199 * than the TMUS/TMUD/TMUA to improve scheduling flexibility.
201 add_write_dep(state
, &state
->last_tmu_write
, n
);
203 case V3D_QPU_WADDR_TMUS
:
204 case V3D_QPU_WADDR_TMUSCM
:
205 case V3D_QPU_WADDR_TMUSF
:
206 case V3D_QPU_WADDR_TMUSLOD
:
207 add_write_dep(state
, &state
->last_tmu_config
, n
);
212 } else if (v3d_qpu_magic_waddr_is_sfu(waddr
)) {
213 /* Handled by v3d_qpu_writes_r4() check. */
216 case V3D_QPU_WADDR_R0
:
217 case V3D_QPU_WADDR_R1
:
218 case V3D_QPU_WADDR_R2
:
220 &state
->last_r
[waddr
- V3D_QPU_WADDR_R0
],
223 case V3D_QPU_WADDR_R3
:
224 case V3D_QPU_WADDR_R4
:
225 case V3D_QPU_WADDR_R5
:
226 /* Handled by v3d_qpu_writes_r*() checks below. */
229 case V3D_QPU_WADDR_VPM
:
230 case V3D_QPU_WADDR_VPMU
:
231 add_write_dep(state
, &state
->last_vpm
, n
);
234 case V3D_QPU_WADDR_TLB
:
235 case V3D_QPU_WADDR_TLBU
:
236 add_write_dep(state
, &state
->last_tlb
, n
);
239 case V3D_QPU_WADDR_SYNC
:
240 case V3D_QPU_WADDR_SYNCB
:
241 case V3D_QPU_WADDR_SYNCU
:
242 /* For CS barrier(): Sync against any other memory
243 * accesses. There doesn't appear to be any need for
244 * barriers to affect ALU operations.
246 add_write_dep(state
, &state
->last_tmu_write
, n
);
249 case V3D_QPU_WADDR_NOP
:
253 fprintf(stderr
, "Unknown waddr %d\n", waddr
);
260 * Common code for dependencies that need to be tracked both forward and
263 * This is for things like "all reads of r4 have to happen between the r4
264 * writes that surround them".
267 calculate_deps(struct schedule_state
*state
, struct schedule_node
*n
)
269 const struct v3d_device_info
*devinfo
= state
->devinfo
;
270 struct qinst
*qinst
= n
->inst
;
271 struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
272 /* If the input and output segments are shared, then all VPM reads to
273 * a location need to happen before all writes. We handle this by
274 * serializing all VPM operations for now.
276 bool separate_vpm_segment
= false;
278 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
) {
279 if (inst
->branch
.cond
!= V3D_QPU_BRANCH_COND_ALWAYS
)
280 add_read_dep(state
, state
->last_sf
, n
);
287 add_write_dep(state
, &state
->last_unif
, n
);
291 assert(inst
->type
== V3D_QPU_INSTR_TYPE_ALU
);
295 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 0)
296 process_mux_deps(state
, n
, inst
->alu
.add
.a
);
297 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 1)
298 process_mux_deps(state
, n
, inst
->alu
.add
.b
);
300 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 0)
301 process_mux_deps(state
, n
, inst
->alu
.mul
.a
);
302 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 1)
303 process_mux_deps(state
, n
, inst
->alu
.mul
.b
);
305 switch (inst
->alu
.add
.op
) {
306 case V3D_QPU_A_VPMSETUP
:
307 /* Could distinguish read/write by unpacking the uniform. */
308 add_write_dep(state
, &state
->last_vpm
, n
);
309 add_write_dep(state
, &state
->last_vpm_read
, n
);
312 case V3D_QPU_A_STVPMV
:
313 case V3D_QPU_A_STVPMD
:
314 case V3D_QPU_A_STVPMP
:
315 add_write_dep(state
, &state
->last_vpm
, n
);
318 case V3D_QPU_A_LDVPMV_IN
:
319 case V3D_QPU_A_LDVPMD_IN
:
320 case V3D_QPU_A_LDVPMG_IN
:
321 case V3D_QPU_A_LDVPMP
:
322 if (!separate_vpm_segment
)
323 add_write_dep(state
, &state
->last_vpm
, n
);
326 case V3D_QPU_A_VPMWT
:
327 add_read_dep(state
, state
->last_vpm
, n
);
331 add_read_dep(state
, state
->last_tlb
, n
);
334 case V3D_QPU_A_SETMSF
:
335 case V3D_QPU_A_SETREVF
:
336 add_write_dep(state
, &state
->last_tlb
, n
);
343 switch (inst
->alu
.mul
.op
) {
344 case V3D_QPU_M_MULTOP
:
345 case V3D_QPU_M_UMUL24
:
346 /* MULTOP sets rtop, and UMUL24 implicitly reads rtop and
347 * resets it to 0. We could possibly reorder umul24s relative
348 * to each other, but for now just keep all the MUL parts in
351 add_write_dep(state
, &state
->last_rtop
, n
);
357 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
358 process_waddr_deps(state
, n
, inst
->alu
.add
.waddr
,
359 inst
->alu
.add
.magic_write
);
361 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
362 process_waddr_deps(state
, n
, inst
->alu
.mul
.waddr
,
363 inst
->alu
.mul
.magic_write
);
365 if (v3d_qpu_sig_writes_address(devinfo
, &inst
->sig
)) {
366 process_waddr_deps(state
, n
, inst
->sig_addr
,
370 if (v3d_qpu_writes_r3(devinfo
, inst
))
371 add_write_dep(state
, &state
->last_r
[3], n
);
372 if (v3d_qpu_writes_r4(devinfo
, inst
))
373 add_write_dep(state
, &state
->last_r
[4], n
);
374 if (v3d_qpu_writes_r5(devinfo
, inst
))
375 add_write_dep(state
, &state
->last_r
[5], n
);
377 if (inst
->sig
.thrsw
) {
378 /* All accumulator contents and flags are undefined after the
381 for (int i
= 0; i
< ARRAY_SIZE(state
->last_r
); i
++)
382 add_write_dep(state
, &state
->last_r
[i
], n
);
383 add_write_dep(state
, &state
->last_sf
, n
);
384 add_write_dep(state
, &state
->last_rtop
, n
);
386 /* Scoreboard-locking operations have to stay after the last
389 add_write_dep(state
, &state
->last_tlb
, n
);
391 add_write_dep(state
, &state
->last_tmu_write
, n
);
392 add_write_dep(state
, &state
->last_tmu_config
, n
);
395 if (v3d_qpu_waits_on_tmu(inst
)) {
396 /* TMU loads are coming from a FIFO, so ordering is important.
398 add_write_dep(state
, &state
->last_tmu_write
, n
);
401 if (inst
->sig
.wrtmuc
)
402 add_write_dep(state
, &state
->last_tmu_config
, n
);
404 if (inst
->sig
.ldtlb
| inst
->sig
.ldtlbu
)
405 add_read_dep(state
, state
->last_tlb
, n
);
407 if (inst
->sig
.ldvpm
) {
408 add_write_dep(state
, &state
->last_vpm_read
, n
);
410 /* At least for now, we're doing shared I/O segments, so queue
411 * all writes after all reads.
413 if (!separate_vpm_segment
)
414 add_write_dep(state
, &state
->last_vpm
, n
);
417 /* inst->sig.ldunif or sideband uniform read */
418 if (qinst
->uniform
!= ~0)
419 add_write_dep(state
, &state
->last_unif
, n
);
421 if (v3d_qpu_reads_flags(inst
))
422 add_read_dep(state
, state
->last_sf
, n
);
423 if (v3d_qpu_writes_flags(inst
))
424 add_write_dep(state
, &state
->last_sf
, n
);
428 calculate_forward_deps(struct v3d_compile
*c
, struct list_head
*schedule_list
)
430 struct schedule_state state
;
432 memset(&state
, 0, sizeof(state
));
433 state
.devinfo
= c
->devinfo
;
436 list_for_each_entry(struct schedule_node
, node
, schedule_list
, link
)
437 calculate_deps(&state
, node
);
441 calculate_reverse_deps(struct v3d_compile
*c
, struct list_head
*schedule_list
)
443 struct list_head
*node
;
444 struct schedule_state state
;
446 memset(&state
, 0, sizeof(state
));
447 state
.devinfo
= c
->devinfo
;
450 for (node
= schedule_list
->prev
; schedule_list
!= node
; node
= node
->prev
) {
451 calculate_deps(&state
, (struct schedule_node
*)node
);
455 struct choose_scoreboard
{
457 int last_magic_sfu_write_tick
;
458 int last_ldvary_tick
;
459 int last_uniforms_reset_tick
;
465 mux_reads_too_soon(struct choose_scoreboard
*scoreboard
,
466 const struct v3d_qpu_instr
*inst
, enum v3d_qpu_mux mux
)
470 if (scoreboard
->tick
- scoreboard
->last_magic_sfu_write_tick
<= 2)
475 if (scoreboard
->tick
- scoreboard
->last_ldvary_tick
<= 1)
486 reads_too_soon_after_write(struct choose_scoreboard
*scoreboard
,
489 const struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
491 /* XXX: Branching off of raddr. */
492 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
)
495 assert(inst
->type
== V3D_QPU_INSTR_TYPE_ALU
);
497 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
498 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 0 &&
499 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.add
.a
)) {
502 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 1 &&
503 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.add
.b
)) {
508 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
509 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 0 &&
510 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.mul
.a
)) {
513 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 1 &&
514 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.mul
.b
)) {
525 writes_too_soon_after_write(const struct v3d_device_info
*devinfo
,
526 struct choose_scoreboard
*scoreboard
,
529 const struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
531 /* Don't schedule any other r4 write too soon after an SFU write.
532 * This would normally be prevented by dependency tracking, but might
533 * occur if a dead SFU computation makes it to scheduling.
535 if (scoreboard
->tick
- scoreboard
->last_magic_sfu_write_tick
< 2 &&
536 v3d_qpu_writes_r4(devinfo
, inst
))
543 pixel_scoreboard_too_soon(struct choose_scoreboard
*scoreboard
,
544 const struct v3d_qpu_instr
*inst
)
546 return (scoreboard
->tick
== 0 && qpu_inst_is_tlb(inst
));
550 get_instruction_priority(const struct v3d_qpu_instr
*inst
)
552 uint32_t baseline_score
;
553 uint32_t next_score
= 0;
555 /* Schedule TLB operations as late as possible, to get more
556 * parallelism between shaders.
558 if (qpu_inst_is_tlb(inst
))
562 /* Schedule texture read results collection late to hide latency. */
563 if (v3d_qpu_waits_on_tmu(inst
))
567 /* XXX perf: We should schedule SFU ALU ops so that the reader is 2
568 * instructions after the producer if possible, not just 1.
571 /* Default score for things that aren't otherwise special. */
572 baseline_score
= next_score
;
575 /* Schedule texture read setup early to hide their latency better. */
576 if (v3d_qpu_writes_tmu(inst
))
580 return baseline_score
;
584 qpu_magic_waddr_is_periph(enum v3d_qpu_waddr waddr
)
586 return (v3d_qpu_magic_waddr_is_tmu(waddr
) ||
587 v3d_qpu_magic_waddr_is_sfu(waddr
) ||
588 v3d_qpu_magic_waddr_is_tlb(waddr
) ||
589 v3d_qpu_magic_waddr_is_vpm(waddr
) ||
590 v3d_qpu_magic_waddr_is_tsy(waddr
));
594 qpu_accesses_peripheral(const struct v3d_qpu_instr
*inst
)
596 if (v3d_qpu_uses_vpm(inst
))
598 if (v3d_qpu_uses_sfu(inst
))
601 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
602 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
&&
603 inst
->alu
.add
.magic_write
&&
604 qpu_magic_waddr_is_periph(inst
->alu
.add
.waddr
)) {
608 if (inst
->alu
.add
.op
== V3D_QPU_A_TMUWT
)
611 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
&&
612 inst
->alu
.mul
.magic_write
&&
613 qpu_magic_waddr_is_periph(inst
->alu
.mul
.waddr
)) {
618 return (inst
->sig
.ldvpm
||
626 qpu_merge_inst(const struct v3d_device_info
*devinfo
,
627 struct v3d_qpu_instr
*result
,
628 const struct v3d_qpu_instr
*a
,
629 const struct v3d_qpu_instr
*b
)
631 if (a
->type
!= V3D_QPU_INSTR_TYPE_ALU
||
632 b
->type
!= V3D_QPU_INSTR_TYPE_ALU
) {
636 /* Can't do more than one peripheral access in an instruction.
638 * XXX: V3D 4.1 allows TMU read along with a VPM read or write, and
639 * WRTMUC with a TMU magic register write (other than tmuc).
641 if (qpu_accesses_peripheral(a
) && qpu_accesses_peripheral(b
))
644 struct v3d_qpu_instr merge
= *a
;
646 if (b
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
647 if (a
->alu
.add
.op
!= V3D_QPU_A_NOP
)
649 merge
.alu
.add
= b
->alu
.add
;
651 merge
.flags
.ac
= b
->flags
.ac
;
652 merge
.flags
.apf
= b
->flags
.apf
;
653 merge
.flags
.auf
= b
->flags
.auf
;
656 if (b
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
657 if (a
->alu
.mul
.op
!= V3D_QPU_M_NOP
)
659 merge
.alu
.mul
= b
->alu
.mul
;
661 merge
.flags
.mc
= b
->flags
.mc
;
662 merge
.flags
.mpf
= b
->flags
.mpf
;
663 merge
.flags
.muf
= b
->flags
.muf
;
666 if (v3d_qpu_uses_mux(b
, V3D_QPU_MUX_A
)) {
667 if (v3d_qpu_uses_mux(a
, V3D_QPU_MUX_A
) &&
668 a
->raddr_a
!= b
->raddr_a
) {
671 merge
.raddr_a
= b
->raddr_a
;
674 if (v3d_qpu_uses_mux(b
, V3D_QPU_MUX_B
)) {
675 if (v3d_qpu_uses_mux(a
, V3D_QPU_MUX_B
) &&
676 (a
->raddr_b
!= b
->raddr_b
||
677 a
->sig
.small_imm
!= b
->sig
.small_imm
)) {
680 merge
.raddr_b
= b
->raddr_b
;
683 merge
.sig
.thrsw
|= b
->sig
.thrsw
;
684 merge
.sig
.ldunif
|= b
->sig
.ldunif
;
685 merge
.sig
.ldunifrf
|= b
->sig
.ldunifrf
;
686 merge
.sig
.ldunifa
|= b
->sig
.ldunifa
;
687 merge
.sig
.ldunifarf
|= b
->sig
.ldunifarf
;
688 merge
.sig
.ldtmu
|= b
->sig
.ldtmu
;
689 merge
.sig
.ldvary
|= b
->sig
.ldvary
;
690 merge
.sig
.ldvpm
|= b
->sig
.ldvpm
;
691 merge
.sig
.small_imm
|= b
->sig
.small_imm
;
692 merge
.sig
.ldtlb
|= b
->sig
.ldtlb
;
693 merge
.sig
.ldtlbu
|= b
->sig
.ldtlbu
;
694 merge
.sig
.ucb
|= b
->sig
.ucb
;
695 merge
.sig
.rotate
|= b
->sig
.rotate
;
696 merge
.sig
.wrtmuc
|= b
->sig
.wrtmuc
;
698 if (v3d_qpu_sig_writes_address(devinfo
, &a
->sig
) &&
699 v3d_qpu_sig_writes_address(devinfo
, &b
->sig
))
701 merge
.sig_addr
|= b
->sig_addr
;
702 merge
.sig_magic
|= b
->sig_magic
;
705 bool ok
= v3d_qpu_instr_pack(devinfo
, &merge
, &packed
);
708 /* No modifying the real instructions on failure. */
709 assert(ok
|| (a
!= result
&& b
!= result
));
714 static struct schedule_node
*
715 choose_instruction_to_schedule(const struct v3d_device_info
*devinfo
,
716 struct choose_scoreboard
*scoreboard
,
717 struct list_head
*schedule_list
,
718 struct schedule_node
*prev_inst
)
720 struct schedule_node
*chosen
= NULL
;
723 /* Don't pair up anything with a thread switch signal -- emit_thrsw()
724 * will handle pairing it along with filling the delay slots.
727 if (prev_inst
->inst
->qpu
.sig
.thrsw
)
731 list_for_each_entry(struct schedule_node
, n
, schedule_list
, link
) {
732 const struct v3d_qpu_instr
*inst
= &n
->inst
->qpu
;
734 /* Don't choose the branch instruction until it's the last one
735 * left. We'll move it up to fit its delay slots after we
738 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
&&
739 !list_is_singular(schedule_list
)) {
743 /* "An instruction must not read from a location in physical
744 * regfile A or B that was written to by the previous
747 if (reads_too_soon_after_write(scoreboard
, n
->inst
))
750 if (writes_too_soon_after_write(devinfo
, scoreboard
, n
->inst
))
753 /* "A scoreboard wait must not occur in the first two
754 * instructions of a fragment shader. This is either the
755 * explicit Wait for Scoreboard signal or an implicit wait
756 * with the first tile-buffer read or write instruction."
758 if (pixel_scoreboard_too_soon(scoreboard
, inst
))
761 /* ldunif and ldvary both write r5, but ldunif does so a tick
762 * sooner. If the ldvary's r5 wasn't used, then ldunif might
763 * otherwise get scheduled so ldunif and ldvary try to update
764 * r5 in the same tick.
766 * XXX perf: To get good pipelining of a sequence of varying
767 * loads, we need to figure out how to pair the ldvary signal
768 * up to the instruction before the last r5 user in the
769 * previous ldvary sequence. Currently, it usually pairs with
772 if ((inst
->sig
.ldunif
|| inst
->sig
.ldunifa
) &&
773 scoreboard
->tick
== scoreboard
->last_ldvary_tick
+ 1) {
777 /* If we're trying to pair with another instruction, check
778 * that they're compatible.
781 /* Don't pair up a thread switch signal -- we'll
782 * handle pairing it when we pick it on its own.
787 if (prev_inst
->inst
->uniform
!= -1 &&
788 n
->inst
->uniform
!= -1)
791 /* Don't merge in something that will lock the TLB.
792 * Hopwefully what we have in inst will release some
793 * other instructions, allowing us to delay the
794 * TLB-locking instruction until later.
796 if (!scoreboard
->tlb_locked
&& qpu_inst_is_tlb(inst
))
799 struct v3d_qpu_instr merged_inst
;
800 if (!qpu_merge_inst(devinfo
, &merged_inst
,
801 &prev_inst
->inst
->qpu
, inst
)) {
806 int prio
= get_instruction_priority(inst
);
808 /* Found a valid instruction. If nothing better comes along,
817 if (prio
> chosen_prio
) {
820 } else if (prio
< chosen_prio
) {
824 if (n
->delay
> chosen
->delay
) {
827 } else if (n
->delay
< chosen
->delay
) {
836 update_scoreboard_for_magic_waddr(struct choose_scoreboard
*scoreboard
,
837 enum v3d_qpu_waddr waddr
)
839 if (v3d_qpu_magic_waddr_is_sfu(waddr
))
840 scoreboard
->last_magic_sfu_write_tick
= scoreboard
->tick
;
844 update_scoreboard_for_chosen(struct choose_scoreboard
*scoreboard
,
845 const struct v3d_qpu_instr
*inst
)
847 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
)
850 assert(inst
->type
== V3D_QPU_INSTR_TYPE_ALU
);
852 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
853 if (inst
->alu
.add
.magic_write
) {
854 update_scoreboard_for_magic_waddr(scoreboard
,
855 inst
->alu
.add
.waddr
);
859 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
860 if (inst
->alu
.mul
.magic_write
) {
861 update_scoreboard_for_magic_waddr(scoreboard
,
862 inst
->alu
.mul
.waddr
);
866 if (inst
->sig
.ldvary
)
867 scoreboard
->last_ldvary_tick
= scoreboard
->tick
;
869 if (qpu_inst_is_tlb(inst
))
870 scoreboard
->tlb_locked
= true;
874 dump_state(const struct v3d_device_info
*devinfo
,
875 struct list_head
*schedule_list
)
877 list_for_each_entry(struct schedule_node
, n
, schedule_list
, link
) {
878 fprintf(stderr
, " t=%4d: ", n
->unblocked_time
);
879 v3d_qpu_dump(devinfo
, &n
->inst
->qpu
);
880 fprintf(stderr
, "\n");
882 for (int i
= 0; i
< n
->child_count
; i
++) {
883 struct schedule_node
*child
= n
->children
[i
].node
;
887 fprintf(stderr
, " - ");
888 v3d_qpu_dump(devinfo
, &child
->inst
->qpu
);
889 fprintf(stderr
, " (%d parents, %c)\n",
891 n
->children
[i
].write_after_read
? 'w' : 'r');
896 static uint32_t magic_waddr_latency(enum v3d_qpu_waddr waddr
,
897 const struct v3d_qpu_instr
*after
)
899 /* Apply some huge latency between texture fetch requests and getting
900 * their results back.
902 * FIXME: This is actually pretty bogus. If we do:
911 * we count that as worse than
920 * because we associate the first load_tmu0 with the *second* tmu0_s.
922 if (v3d_qpu_magic_waddr_is_tmu(waddr
) && v3d_qpu_waits_on_tmu(after
))
925 /* Assume that anything depending on us is consuming the SFU result. */
926 if (v3d_qpu_magic_waddr_is_sfu(waddr
))
933 instruction_latency(struct schedule_node
*before
, struct schedule_node
*after
)
935 const struct v3d_qpu_instr
*before_inst
= &before
->inst
->qpu
;
936 const struct v3d_qpu_instr
*after_inst
= &after
->inst
->qpu
;
937 uint32_t latency
= 1;
939 if (before_inst
->type
!= V3D_QPU_INSTR_TYPE_ALU
||
940 after_inst
->type
!= V3D_QPU_INSTR_TYPE_ALU
)
943 if (before_inst
->alu
.add
.magic_write
) {
944 latency
= MAX2(latency
,
945 magic_waddr_latency(before_inst
->alu
.add
.waddr
,
949 if (before_inst
->alu
.mul
.magic_write
) {
950 latency
= MAX2(latency
,
951 magic_waddr_latency(before_inst
->alu
.mul
.waddr
,
958 /** Recursive computation of the delay member of a node. */
960 compute_delay(struct schedule_node
*n
)
962 if (!n
->child_count
) {
965 for (int i
= 0; i
< n
->child_count
; i
++) {
966 if (!n
->children
[i
].node
->delay
)
967 compute_delay(n
->children
[i
].node
);
968 n
->delay
= MAX2(n
->delay
,
969 n
->children
[i
].node
->delay
+
970 instruction_latency(n
, n
->children
[i
].node
));
976 mark_instruction_scheduled(struct list_head
*schedule_list
,
978 struct schedule_node
*node
,
984 for (int i
= node
->child_count
- 1; i
>= 0; i
--) {
985 struct schedule_node
*child
=
986 node
->children
[i
].node
;
991 if (war_only
&& !node
->children
[i
].write_after_read
)
994 /* If the requirement is only that the node not appear before
995 * the last read of its destination, then it can be scheduled
996 * immediately after (or paired with!) the thing reading the
999 uint32_t latency
= 0;
1001 latency
= instruction_latency(node
,
1002 node
->children
[i
].node
);
1005 child
->unblocked_time
= MAX2(child
->unblocked_time
,
1007 child
->parent_count
--;
1008 if (child
->parent_count
== 0)
1009 list_add(&child
->link
, schedule_list
);
1011 node
->children
[i
].node
= NULL
;
1016 insert_scheduled_instruction(struct v3d_compile
*c
,
1017 struct qblock
*block
,
1018 struct choose_scoreboard
*scoreboard
,
1021 list_addtail(&inst
->link
, &block
->instructions
);
1023 update_scoreboard_for_chosen(scoreboard
, &inst
->qpu
);
1024 c
->qpu_inst_count
++;
1028 static struct qinst
*
1031 struct qreg undef
= { QFILE_NULL
, 0 };
1032 struct qinst
*qinst
= vir_add_inst(V3D_QPU_A_NOP
, undef
, undef
, undef
);
1038 emit_nop(struct v3d_compile
*c
, struct qblock
*block
,
1039 struct choose_scoreboard
*scoreboard
)
1041 insert_scheduled_instruction(c
, block
, scoreboard
, vir_nop());
1045 qpu_instruction_valid_in_thrend_slot(struct v3d_compile
*c
,
1046 const struct qinst
*qinst
, int slot
)
1048 const struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
1050 /* Only TLB Z writes are prohibited in the last slot, but we don't
1051 * have those flagged so prohibit all TLB ops for now.
1053 if (slot
== 2 && qpu_inst_is_tlb(inst
))
1056 if (slot
> 0 && qinst
->uniform
!= ~0)
1059 if (v3d_qpu_uses_vpm(inst
))
1062 if (inst
->sig
.ldvary
)
1065 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
1066 /* GFXH-1625: TMUWT not allowed in the final instruction. */
1067 if (slot
== 2 && inst
->alu
.add
.op
== V3D_QPU_A_TMUWT
)
1070 /* No writing physical registers at the end. */
1071 if (!inst
->alu
.add
.magic_write
||
1072 !inst
->alu
.mul
.magic_write
) {
1076 if (c
->devinfo
->ver
< 40 && inst
->alu
.add
.op
== V3D_QPU_A_SETMSF
)
1079 /* RF0-2 might be overwritten during the delay slots by
1080 * fragment shader setup.
1082 if (inst
->raddr_a
< 3 &&
1083 (inst
->alu
.add
.a
== V3D_QPU_MUX_A
||
1084 inst
->alu
.add
.b
== V3D_QPU_MUX_A
||
1085 inst
->alu
.mul
.a
== V3D_QPU_MUX_A
||
1086 inst
->alu
.mul
.b
== V3D_QPU_MUX_A
)) {
1090 if (inst
->raddr_b
< 3 &&
1091 !inst
->sig
.small_imm
&&
1092 (inst
->alu
.add
.a
== V3D_QPU_MUX_B
||
1093 inst
->alu
.add
.b
== V3D_QPU_MUX_B
||
1094 inst
->alu
.mul
.a
== V3D_QPU_MUX_B
||
1095 inst
->alu
.mul
.b
== V3D_QPU_MUX_B
)) {
1104 valid_thrsw_sequence(struct v3d_compile
*c
, struct choose_scoreboard
*scoreboard
,
1105 struct qinst
*qinst
, int instructions_in_sequence
,
1108 /* No emitting our thrsw while the previous thrsw hasn't happened yet. */
1109 if (scoreboard
->last_thrsw_tick
+ 3 >
1110 scoreboard
->tick
- instructions_in_sequence
) {
1114 for (int slot
= 0; slot
< instructions_in_sequence
; slot
++) {
1115 /* No scheduling SFU when the result would land in the other
1116 * thread. The simulator complains for safety, though it
1117 * would only occur for dead code in our case.
1120 qinst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
1121 (v3d_qpu_magic_waddr_is_sfu(qinst
->qpu
.alu
.add
.waddr
) ||
1122 v3d_qpu_magic_waddr_is_sfu(qinst
->qpu
.alu
.mul
.waddr
))) {
1126 if (slot
> 0 && qinst
->qpu
.sig
.ldvary
)
1130 !qpu_instruction_valid_in_thrend_slot(c
, qinst
, slot
)) {
1134 /* Note that the list is circular, so we can only do this up
1135 * to instructions_in_sequence.
1137 qinst
= (struct qinst
*)qinst
->link
.next
;
1144 * Emits a THRSW signal in the stream, trying to move it up to pair with
1145 * another instruction.
1148 emit_thrsw(struct v3d_compile
*c
,
1149 struct qblock
*block
,
1150 struct choose_scoreboard
*scoreboard
,
1156 /* There should be nothing in a thrsw inst being scheduled other than
1159 assert(inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
);
1160 assert(inst
->qpu
.alu
.add
.op
== V3D_QPU_A_NOP
);
1161 assert(inst
->qpu
.alu
.mul
.op
== V3D_QPU_M_NOP
);
1163 /* Find how far back into previous instructions we can put the THRSW. */
1164 int slots_filled
= 0;
1165 struct qinst
*merge_inst
= NULL
;
1166 vir_for_each_inst_rev(prev_inst
, block
) {
1167 struct v3d_qpu_sig sig
= prev_inst
->qpu
.sig
;
1169 uint32_t packed_sig
;
1171 if (!v3d_qpu_sig_pack(c
->devinfo
, &sig
, &packed_sig
))
1174 if (!valid_thrsw_sequence(c
, scoreboard
,
1175 prev_inst
, slots_filled
+ 1,
1180 merge_inst
= prev_inst
;
1181 if (++slots_filled
== 3)
1185 bool needs_free
= false;
1187 merge_inst
->qpu
.sig
.thrsw
= true;
1189 scoreboard
->last_thrsw_tick
= scoreboard
->tick
- slots_filled
;
1191 scoreboard
->last_thrsw_tick
= scoreboard
->tick
;
1192 insert_scheduled_instruction(c
, block
, scoreboard
, inst
);
1198 /* Insert any extra delay slot NOPs we need. */
1199 for (int i
= 0; i
< 3 - slots_filled
; i
++) {
1200 emit_nop(c
, block
, scoreboard
);
1204 /* If we're emitting the last THRSW (other than program end), then
1205 * signal that to the HW by emitting two THRSWs in a row.
1207 if (inst
->is_last_thrsw
) {
1208 struct qinst
*second_inst
=
1209 (struct qinst
*)merge_inst
->link
.next
;
1210 second_inst
->qpu
.sig
.thrsw
= true;
1213 /* If we put our THRSW into another instruction, free up the
1214 * instruction that didn't end up scheduled into the list.
1223 schedule_instructions(struct v3d_compile
*c
,
1224 struct choose_scoreboard
*scoreboard
,
1225 struct qblock
*block
,
1226 struct list_head
*schedule_list
,
1227 enum quniform_contents
*orig_uniform_contents
,
1228 uint32_t *orig_uniform_data
,
1229 uint32_t *next_uniform
)
1231 const struct v3d_device_info
*devinfo
= c
->devinfo
;
1235 fprintf(stderr
, "initial deps:\n");
1236 dump_state(devinfo
, schedule_list
);
1237 fprintf(stderr
, "\n");
1240 /* Remove non-DAG heads from the list. */
1241 list_for_each_entry_safe(struct schedule_node
, n
, schedule_list
, link
) {
1242 if (n
->parent_count
!= 0)
1246 while (!list_empty(schedule_list
)) {
1247 struct schedule_node
*chosen
=
1248 choose_instruction_to_schedule(devinfo
,
1252 struct schedule_node
*merge
= NULL
;
1254 /* If there are no valid instructions to schedule, drop a NOP
1257 struct qinst
*qinst
= chosen
? chosen
->inst
: vir_nop();
1258 struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
1261 fprintf(stderr
, "t=%4d: current list:\n",
1263 dump_state(devinfo
, schedule_list
);
1264 fprintf(stderr
, "t=%4d: chose: ", time
);
1265 v3d_qpu_dump(devinfo
, inst
);
1266 fprintf(stderr
, "\n");
1269 /* We can't mark_instruction_scheduled() the chosen inst until
1270 * we're done identifying instructions to merge, so put the
1271 * merged instructions on a list for a moment.
1273 struct list_head merged_list
;
1274 list_inithead(&merged_list
);
1276 /* Schedule this instruction onto the QPU list. Also try to
1277 * find an instruction to pair with it.
1280 time
= MAX2(chosen
->unblocked_time
, time
);
1281 list_del(&chosen
->link
);
1282 mark_instruction_scheduled(schedule_list
, time
,
1286 choose_instruction_to_schedule(devinfo
,
1290 time
= MAX2(merge
->unblocked_time
, time
);
1291 list_del(&merge
->link
);
1292 list_addtail(&merge
->link
, &merged_list
);
1293 (void)qpu_merge_inst(devinfo
, inst
,
1294 inst
, &merge
->inst
->qpu
);
1295 if (merge
->inst
->uniform
!= -1) {
1296 chosen
->inst
->uniform
=
1297 merge
->inst
->uniform
;
1301 fprintf(stderr
, "t=%4d: merging: ",
1303 v3d_qpu_dump(devinfo
, &merge
->inst
->qpu
);
1304 fprintf(stderr
, "\n");
1305 fprintf(stderr
, " result: ");
1306 v3d_qpu_dump(devinfo
, inst
);
1307 fprintf(stderr
, "\n");
1312 /* Update the uniform index for the rewritten location --
1313 * branch target updating will still need to change
1314 * c->uniform_data[] using this index.
1316 if (qinst
->uniform
!= -1) {
1317 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
)
1318 block
->branch_uniform
= *next_uniform
;
1320 c
->uniform_data
[*next_uniform
] =
1321 orig_uniform_data
[qinst
->uniform
];
1322 c
->uniform_contents
[*next_uniform
] =
1323 orig_uniform_contents
[qinst
->uniform
];
1324 qinst
->uniform
= *next_uniform
;
1329 fprintf(stderr
, "\n");
1332 /* Now that we've scheduled a new instruction, some of its
1333 * children can be promoted to the list of instructions ready to
1334 * be scheduled. Update the children's unblocked time for this
1335 * DAG edge as we do so.
1337 mark_instruction_scheduled(schedule_list
, time
, chosen
, false);
1338 list_for_each_entry(struct schedule_node
, merge
, &merged_list
,
1340 mark_instruction_scheduled(schedule_list
, time
, merge
,
1343 /* The merged VIR instruction doesn't get re-added to the
1344 * block, so free it now.
1349 if (inst
->sig
.thrsw
) {
1350 time
+= emit_thrsw(c
, block
, scoreboard
, qinst
, false);
1352 insert_scheduled_instruction(c
, block
,
1355 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
) {
1356 block
->branch_qpu_ip
= c
->qpu_inst_count
- 1;
1357 /* Fill the delay slots.
1359 * We should fill these with actual instructions,
1360 * instead, but that will probably need to be done
1361 * after this, once we know what the leading
1362 * instructions of the successors are (so we can
1363 * handle A/B register file write latency)
1365 for (int i
= 0; i
< 3; i
++)
1366 emit_nop(c
, block
, scoreboard
);
1375 qpu_schedule_instructions_block(struct v3d_compile
*c
,
1376 struct choose_scoreboard
*scoreboard
,
1377 struct qblock
*block
,
1378 enum quniform_contents
*orig_uniform_contents
,
1379 uint32_t *orig_uniform_data
,
1380 uint32_t *next_uniform
)
1382 void *mem_ctx
= ralloc_context(NULL
);
1383 struct list_head schedule_list
;
1385 list_inithead(&schedule_list
);
1387 /* Wrap each instruction in a scheduler structure. */
1388 while (!list_empty(&block
->instructions
)) {
1389 struct qinst
*qinst
= (struct qinst
*)block
->instructions
.next
;
1390 struct schedule_node
*n
=
1391 rzalloc(mem_ctx
, struct schedule_node
);
1395 list_del(&qinst
->link
);
1396 list_addtail(&n
->link
, &schedule_list
);
1399 calculate_forward_deps(c
, &schedule_list
);
1400 calculate_reverse_deps(c
, &schedule_list
);
1402 list_for_each_entry(struct schedule_node
, n
, &schedule_list
, link
) {
1406 uint32_t cycles
= schedule_instructions(c
, scoreboard
, block
,
1408 orig_uniform_contents
,
1412 ralloc_free(mem_ctx
);
1418 qpu_set_branch_targets(struct v3d_compile
*c
)
1420 vir_for_each_block(block
, c
) {
1421 /* The end block of the program has no branch. */
1422 if (!block
->successors
[0])
1425 /* If there was no branch instruction, then the successor
1426 * block must follow immediately after this one.
1428 if (block
->branch_qpu_ip
== ~0) {
1429 assert(block
->end_qpu_ip
+ 1 ==
1430 block
->successors
[0]->start_qpu_ip
);
1434 /* Walk back through the delay slots to find the branch
1437 struct list_head
*entry
= block
->instructions
.prev
;
1438 for (int i
= 0; i
< 3; i
++)
1439 entry
= entry
->prev
;
1440 struct qinst
*branch
= container_of(entry
, branch
, link
);
1441 assert(branch
->qpu
.type
== V3D_QPU_INSTR_TYPE_BRANCH
);
1443 /* Make sure that the if-we-don't-jump
1444 * successor was scheduled just after the
1447 assert(!block
->successors
[1] ||
1448 block
->successors
[1]->start_qpu_ip
==
1449 block
->branch_qpu_ip
+ 4);
1451 branch
->qpu
.branch
.offset
=
1452 ((block
->successors
[0]->start_qpu_ip
-
1453 (block
->branch_qpu_ip
+ 4)) *
1456 /* Set up the relative offset to jump in the
1459 * Use a temporary here, because
1460 * uniform_data[inst->uniform] may be shared
1461 * between multiple instructions.
1463 assert(c
->uniform_contents
[branch
->uniform
] == QUNIFORM_CONSTANT
);
1464 c
->uniform_data
[branch
->uniform
] =
1465 (block
->successors
[0]->start_uniform
-
1466 (block
->branch_uniform
+ 1)) * 4;
1471 v3d_qpu_schedule_instructions(struct v3d_compile
*c
)
1473 const struct v3d_device_info
*devinfo
= c
->devinfo
;
1474 struct qblock
*end_block
= list_last_entry(&c
->blocks
,
1475 struct qblock
, link
);
1477 /* We reorder the uniforms as we schedule instructions, so save the
1478 * old data off and replace it.
1480 uint32_t *uniform_data
= c
->uniform_data
;
1481 enum quniform_contents
*uniform_contents
= c
->uniform_contents
;
1482 c
->uniform_contents
= ralloc_array(c
, enum quniform_contents
,
1484 c
->uniform_data
= ralloc_array(c
, uint32_t, c
->num_uniforms
);
1485 c
->uniform_array_size
= c
->num_uniforms
;
1486 uint32_t next_uniform
= 0;
1488 struct choose_scoreboard scoreboard
;
1489 memset(&scoreboard
, 0, sizeof(scoreboard
));
1490 scoreboard
.last_ldvary_tick
= -10;
1491 scoreboard
.last_magic_sfu_write_tick
= -10;
1492 scoreboard
.last_uniforms_reset_tick
= -10;
1493 scoreboard
.last_thrsw_tick
= -10;
1496 fprintf(stderr
, "Pre-schedule instructions\n");
1497 vir_for_each_block(block
, c
) {
1498 fprintf(stderr
, "BLOCK %d\n", block
->index
);
1499 list_for_each_entry(struct qinst
, qinst
,
1500 &block
->instructions
, link
) {
1501 v3d_qpu_dump(devinfo
, &qinst
->qpu
);
1502 fprintf(stderr
, "\n");
1505 fprintf(stderr
, "\n");
1508 uint32_t cycles
= 0;
1509 vir_for_each_block(block
, c
) {
1510 block
->start_qpu_ip
= c
->qpu_inst_count
;
1511 block
->branch_qpu_ip
= ~0;
1512 block
->start_uniform
= next_uniform
;
1514 cycles
+= qpu_schedule_instructions_block(c
,
1521 block
->end_qpu_ip
= c
->qpu_inst_count
- 1;
1524 /* Emit the program-end THRSW instruction. */;
1525 struct qinst
*thrsw
= vir_nop();
1526 thrsw
->qpu
.sig
.thrsw
= true;
1527 emit_thrsw(c
, end_block
, &scoreboard
, thrsw
, true);
1529 qpu_set_branch_targets(c
);
1531 assert(next_uniform
== c
->num_uniforms
);