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egl: Let the caller of dri2_create_drawable decide about loaderPrivate.
[mesa.git] / src / broadcom / compiler / qpu_schedule.c
1 /*
2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2017 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 /**
26 * @file
27 *
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
32 *
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
35 */
36
37 #include "qpu/qpu_disasm.h"
38 #include "v3d_compiler.h"
39 #include "util/ralloc.h"
40 #include "util/dag.h"
41
42 static bool debug;
43
44 struct schedule_node_child;
45
46 struct schedule_node {
47 struct dag_node dag;
48 struct list_head link;
49 struct qinst *inst;
50
51 /* Longest cycles + instruction_latency() of any parent of this node. */
52 uint32_t unblocked_time;
53
54 /**
55 * Minimum number of cycles from scheduling this instruction until the
56 * end of the program, based on the slowest dependency chain through
57 * the children.
58 */
59 uint32_t delay;
60
61 /**
62 * cycles between this instruction being scheduled and when its result
63 * can be consumed.
64 */
65 uint32_t latency;
66 };
67
68 /* When walking the instructions in reverse, we need to swap before/after in
69 * add_dep().
70 */
71 enum direction { F, R };
72
73 struct schedule_state {
74 const struct v3d_device_info *devinfo;
75 struct dag *dag;
76 struct schedule_node *last_r[6];
77 struct schedule_node *last_rf[64];
78 struct schedule_node *last_sf;
79 struct schedule_node *last_vpm_read;
80 struct schedule_node *last_tmu_write;
81 struct schedule_node *last_tmu_config;
82 struct schedule_node *last_tlb;
83 struct schedule_node *last_vpm;
84 struct schedule_node *last_unif;
85 struct schedule_node *last_rtop;
86 enum direction dir;
87 /* Estimated cycle when the current instruction would start. */
88 uint32_t time;
89 };
90
91 static void
92 add_dep(struct schedule_state *state,
93 struct schedule_node *before,
94 struct schedule_node *after,
95 bool write)
96 {
97 bool write_after_read = !write && state->dir == R;
98 void *edge_data = (void *)(uintptr_t)write_after_read;
99
100 if (!before || !after)
101 return;
102
103 assert(before != after);
104
105 if (state->dir == F)
106 dag_add_edge(&before->dag, &after->dag, edge_data);
107 else
108 dag_add_edge(&after->dag, &before->dag, edge_data);
109 }
110
111 static void
112 add_read_dep(struct schedule_state *state,
113 struct schedule_node *before,
114 struct schedule_node *after)
115 {
116 add_dep(state, before, after, false);
117 }
118
119 static void
120 add_write_dep(struct schedule_state *state,
121 struct schedule_node **before,
122 struct schedule_node *after)
123 {
124 add_dep(state, *before, after, true);
125 *before = after;
126 }
127
128 static bool
129 qpu_inst_is_tlb(const struct v3d_qpu_instr *inst)
130 {
131 if (inst->type != V3D_QPU_INSTR_TYPE_ALU)
132 return false;
133
134 if (inst->alu.add.magic_write &&
135 (inst->alu.add.waddr == V3D_QPU_WADDR_TLB ||
136 inst->alu.add.waddr == V3D_QPU_WADDR_TLBU))
137 return true;
138
139 if (inst->alu.mul.magic_write &&
140 (inst->alu.mul.waddr == V3D_QPU_WADDR_TLB ||
141 inst->alu.mul.waddr == V3D_QPU_WADDR_TLBU))
142 return true;
143
144 return false;
145 }
146
147 static void
148 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
149 enum v3d_qpu_mux mux)
150 {
151 switch (mux) {
152 case V3D_QPU_MUX_A:
153 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n);
154 break;
155 case V3D_QPU_MUX_B:
156 if (!n->inst->qpu.sig.small_imm) {
157 add_read_dep(state,
158 state->last_rf[n->inst->qpu.raddr_b], n);
159 }
160 break;
161 default:
162 add_read_dep(state, state->last_r[mux - V3D_QPU_MUX_R0], n);
163 break;
164 }
165 }
166
167
168 static void
169 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
170 uint32_t waddr, bool magic)
171 {
172 if (!magic) {
173 add_write_dep(state, &state->last_rf[waddr], n);
174 } else if (v3d_qpu_magic_waddr_is_tmu(waddr)) {
175 /* XXX perf: For V3D 4.x, we could reorder TMU writes other
176 * than the TMUS/TMUD/TMUA to improve scheduling flexibility.
177 */
178 add_write_dep(state, &state->last_tmu_write, n);
179 switch (waddr) {
180 case V3D_QPU_WADDR_TMUS:
181 case V3D_QPU_WADDR_TMUSCM:
182 case V3D_QPU_WADDR_TMUSF:
183 case V3D_QPU_WADDR_TMUSLOD:
184 add_write_dep(state, &state->last_tmu_config, n);
185 break;
186 default:
187 break;
188 }
189 } else if (v3d_qpu_magic_waddr_is_sfu(waddr)) {
190 /* Handled by v3d_qpu_writes_r4() check. */
191 } else {
192 switch (waddr) {
193 case V3D_QPU_WADDR_R0:
194 case V3D_QPU_WADDR_R1:
195 case V3D_QPU_WADDR_R2:
196 add_write_dep(state,
197 &state->last_r[waddr - V3D_QPU_WADDR_R0],
198 n);
199 break;
200 case V3D_QPU_WADDR_R3:
201 case V3D_QPU_WADDR_R4:
202 case V3D_QPU_WADDR_R5:
203 /* Handled by v3d_qpu_writes_r*() checks below. */
204 break;
205
206 case V3D_QPU_WADDR_VPM:
207 case V3D_QPU_WADDR_VPMU:
208 add_write_dep(state, &state->last_vpm, n);
209 break;
210
211 case V3D_QPU_WADDR_TLB:
212 case V3D_QPU_WADDR_TLBU:
213 add_write_dep(state, &state->last_tlb, n);
214 break;
215
216 case V3D_QPU_WADDR_SYNC:
217 case V3D_QPU_WADDR_SYNCB:
218 case V3D_QPU_WADDR_SYNCU:
219 /* For CS barrier(): Sync against any other memory
220 * accesses. There doesn't appear to be any need for
221 * barriers to affect ALU operations.
222 */
223 add_write_dep(state, &state->last_tmu_write, n);
224 break;
225
226 case V3D_QPU_WADDR_NOP:
227 break;
228
229 default:
230 fprintf(stderr, "Unknown waddr %d\n", waddr);
231 abort();
232 }
233 }
234 }
235
236 /**
237 * Common code for dependencies that need to be tracked both forward and
238 * backward.
239 *
240 * This is for things like "all reads of r4 have to happen between the r4
241 * writes that surround them".
242 */
243 static void
244 calculate_deps(struct schedule_state *state, struct schedule_node *n)
245 {
246 const struct v3d_device_info *devinfo = state->devinfo;
247 struct qinst *qinst = n->inst;
248 struct v3d_qpu_instr *inst = &qinst->qpu;
249 /* If the input and output segments are shared, then all VPM reads to
250 * a location need to happen before all writes. We handle this by
251 * serializing all VPM operations for now.
252 */
253 bool separate_vpm_segment = false;
254
255 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
256 if (inst->branch.cond != V3D_QPU_BRANCH_COND_ALWAYS)
257 add_read_dep(state, state->last_sf, n);
258
259 /* XXX: BDI */
260 /* XXX: BDU */
261 /* XXX: ub */
262 /* XXX: raddr_a */
263
264 add_write_dep(state, &state->last_unif, n);
265 return;
266 }
267
268 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
269
270 /* XXX: LOAD_IMM */
271
272 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0)
273 process_mux_deps(state, n, inst->alu.add.a);
274 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1)
275 process_mux_deps(state, n, inst->alu.add.b);
276
277 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0)
278 process_mux_deps(state, n, inst->alu.mul.a);
279 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1)
280 process_mux_deps(state, n, inst->alu.mul.b);
281
282 switch (inst->alu.add.op) {
283 case V3D_QPU_A_VPMSETUP:
284 /* Could distinguish read/write by unpacking the uniform. */
285 add_write_dep(state, &state->last_vpm, n);
286 add_write_dep(state, &state->last_vpm_read, n);
287 break;
288
289 case V3D_QPU_A_STVPMV:
290 case V3D_QPU_A_STVPMD:
291 case V3D_QPU_A_STVPMP:
292 add_write_dep(state, &state->last_vpm, n);
293 break;
294
295 case V3D_QPU_A_LDVPMV_IN:
296 case V3D_QPU_A_LDVPMD_IN:
297 case V3D_QPU_A_LDVPMG_IN:
298 case V3D_QPU_A_LDVPMP:
299 if (!separate_vpm_segment)
300 add_write_dep(state, &state->last_vpm, n);
301 break;
302
303 case V3D_QPU_A_VPMWT:
304 add_read_dep(state, state->last_vpm, n);
305 break;
306
307 case V3D_QPU_A_MSF:
308 add_read_dep(state, state->last_tlb, n);
309 break;
310
311 case V3D_QPU_A_SETMSF:
312 case V3D_QPU_A_SETREVF:
313 add_write_dep(state, &state->last_tlb, n);
314 break;
315
316 default:
317 break;
318 }
319
320 switch (inst->alu.mul.op) {
321 case V3D_QPU_M_MULTOP:
322 case V3D_QPU_M_UMUL24:
323 /* MULTOP sets rtop, and UMUL24 implicitly reads rtop and
324 * resets it to 0. We could possibly reorder umul24s relative
325 * to each other, but for now just keep all the MUL parts in
326 * order.
327 */
328 add_write_dep(state, &state->last_rtop, n);
329 break;
330 default:
331 break;
332 }
333
334 if (inst->alu.add.op != V3D_QPU_A_NOP) {
335 process_waddr_deps(state, n, inst->alu.add.waddr,
336 inst->alu.add.magic_write);
337 }
338 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
339 process_waddr_deps(state, n, inst->alu.mul.waddr,
340 inst->alu.mul.magic_write);
341 }
342 if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) {
343 process_waddr_deps(state, n, inst->sig_addr,
344 inst->sig_magic);
345 }
346
347 if (v3d_qpu_writes_r3(devinfo, inst))
348 add_write_dep(state, &state->last_r[3], n);
349 if (v3d_qpu_writes_r4(devinfo, inst))
350 add_write_dep(state, &state->last_r[4], n);
351 if (v3d_qpu_writes_r5(devinfo, inst))
352 add_write_dep(state, &state->last_r[5], n);
353
354 if (inst->sig.thrsw) {
355 /* All accumulator contents and flags are undefined after the
356 * switch.
357 */
358 for (int i = 0; i < ARRAY_SIZE(state->last_r); i++)
359 add_write_dep(state, &state->last_r[i], n);
360 add_write_dep(state, &state->last_sf, n);
361 add_write_dep(state, &state->last_rtop, n);
362
363 /* Scoreboard-locking operations have to stay after the last
364 * thread switch.
365 */
366 add_write_dep(state, &state->last_tlb, n);
367
368 add_write_dep(state, &state->last_tmu_write, n);
369 add_write_dep(state, &state->last_tmu_config, n);
370 }
371
372 if (v3d_qpu_waits_on_tmu(inst)) {
373 /* TMU loads are coming from a FIFO, so ordering is important.
374 */
375 add_write_dep(state, &state->last_tmu_write, n);
376 }
377
378 if (inst->sig.wrtmuc)
379 add_write_dep(state, &state->last_tmu_config, n);
380
381 if (inst->sig.ldtlb | inst->sig.ldtlbu)
382 add_read_dep(state, state->last_tlb, n);
383
384 if (inst->sig.ldvpm) {
385 add_write_dep(state, &state->last_vpm_read, n);
386
387 /* At least for now, we're doing shared I/O segments, so queue
388 * all writes after all reads.
389 */
390 if (!separate_vpm_segment)
391 add_write_dep(state, &state->last_vpm, n);
392 }
393
394 /* inst->sig.ldunif or sideband uniform read */
395 if (vir_has_uniform(qinst))
396 add_write_dep(state, &state->last_unif, n);
397
398 if (v3d_qpu_reads_flags(inst))
399 add_read_dep(state, state->last_sf, n);
400 if (v3d_qpu_writes_flags(inst))
401 add_write_dep(state, &state->last_sf, n);
402 }
403
404 static void
405 calculate_forward_deps(struct v3d_compile *c, struct dag *dag,
406 struct list_head *schedule_list)
407 {
408 struct schedule_state state;
409
410 memset(&state, 0, sizeof(state));
411 state.dag = dag;
412 state.devinfo = c->devinfo;
413 state.dir = F;
414
415 list_for_each_entry(struct schedule_node, node, schedule_list, link)
416 calculate_deps(&state, node);
417 }
418
419 static void
420 calculate_reverse_deps(struct v3d_compile *c, struct dag *dag,
421 struct list_head *schedule_list)
422 {
423 struct schedule_state state;
424
425 memset(&state, 0, sizeof(state));
426 state.dag = dag;
427 state.devinfo = c->devinfo;
428 state.dir = R;
429
430 list_for_each_entry_rev(struct schedule_node, node, schedule_list,
431 link) {
432 calculate_deps(&state, (struct schedule_node *)node);
433 }
434 }
435
436 struct choose_scoreboard {
437 struct dag *dag;
438 int tick;
439 int last_magic_sfu_write_tick;
440 int last_ldvary_tick;
441 int last_uniforms_reset_tick;
442 int last_thrsw_tick;
443 bool tlb_locked;
444 };
445
446 static bool
447 mux_reads_too_soon(struct choose_scoreboard *scoreboard,
448 const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux)
449 {
450 switch (mux) {
451 case V3D_QPU_MUX_R4:
452 if (scoreboard->tick - scoreboard->last_magic_sfu_write_tick <= 2)
453 return true;
454 break;
455
456 case V3D_QPU_MUX_R5:
457 if (scoreboard->tick - scoreboard->last_ldvary_tick <= 1)
458 return true;
459 break;
460 default:
461 break;
462 }
463
464 return false;
465 }
466
467 static bool
468 reads_too_soon_after_write(struct choose_scoreboard *scoreboard,
469 struct qinst *qinst)
470 {
471 const struct v3d_qpu_instr *inst = &qinst->qpu;
472
473 /* XXX: Branching off of raddr. */
474 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
475 return false;
476
477 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
478
479 if (inst->alu.add.op != V3D_QPU_A_NOP) {
480 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0 &&
481 mux_reads_too_soon(scoreboard, inst, inst->alu.add.a)) {
482 return true;
483 }
484 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1 &&
485 mux_reads_too_soon(scoreboard, inst, inst->alu.add.b)) {
486 return true;
487 }
488 }
489
490 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
491 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0 &&
492 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.a)) {
493 return true;
494 }
495 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1 &&
496 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.b)) {
497 return true;
498 }
499 }
500
501 /* XXX: imm */
502
503 return false;
504 }
505
506 static bool
507 writes_too_soon_after_write(const struct v3d_device_info *devinfo,
508 struct choose_scoreboard *scoreboard,
509 struct qinst *qinst)
510 {
511 const struct v3d_qpu_instr *inst = &qinst->qpu;
512
513 /* Don't schedule any other r4 write too soon after an SFU write.
514 * This would normally be prevented by dependency tracking, but might
515 * occur if a dead SFU computation makes it to scheduling.
516 */
517 if (scoreboard->tick - scoreboard->last_magic_sfu_write_tick < 2 &&
518 v3d_qpu_writes_r4(devinfo, inst))
519 return true;
520
521 return false;
522 }
523
524 static bool
525 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard,
526 const struct v3d_qpu_instr *inst)
527 {
528 return (scoreboard->tick == 0 && qpu_inst_is_tlb(inst));
529 }
530
531 static int
532 get_instruction_priority(const struct v3d_qpu_instr *inst)
533 {
534 uint32_t baseline_score;
535 uint32_t next_score = 0;
536
537 /* Schedule TLB operations as late as possible, to get more
538 * parallelism between shaders.
539 */
540 if (qpu_inst_is_tlb(inst))
541 return next_score;
542 next_score++;
543
544 /* Schedule texture read results collection late to hide latency. */
545 if (v3d_qpu_waits_on_tmu(inst))
546 return next_score;
547 next_score++;
548
549 /* XXX perf: We should schedule SFU ALU ops so that the reader is 2
550 * instructions after the producer if possible, not just 1.
551 */
552
553 /* Default score for things that aren't otherwise special. */
554 baseline_score = next_score;
555 next_score++;
556
557 /* Schedule texture read setup early to hide their latency better. */
558 if (v3d_qpu_writes_tmu(inst))
559 return next_score;
560 next_score++;
561
562 return baseline_score;
563 }
564
565 static bool
566 qpu_magic_waddr_is_periph(enum v3d_qpu_waddr waddr)
567 {
568 return (v3d_qpu_magic_waddr_is_tmu(waddr) ||
569 v3d_qpu_magic_waddr_is_sfu(waddr) ||
570 v3d_qpu_magic_waddr_is_tlb(waddr) ||
571 v3d_qpu_magic_waddr_is_vpm(waddr) ||
572 v3d_qpu_magic_waddr_is_tsy(waddr));
573 }
574
575 static bool
576 qpu_accesses_peripheral(const struct v3d_qpu_instr *inst)
577 {
578 if (v3d_qpu_uses_vpm(inst))
579 return true;
580 if (v3d_qpu_uses_sfu(inst))
581 return true;
582
583 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
584 if (inst->alu.add.op != V3D_QPU_A_NOP &&
585 inst->alu.add.magic_write &&
586 qpu_magic_waddr_is_periph(inst->alu.add.waddr)) {
587 return true;
588 }
589
590 if (inst->alu.add.op == V3D_QPU_A_TMUWT)
591 return true;
592
593 if (inst->alu.mul.op != V3D_QPU_M_NOP &&
594 inst->alu.mul.magic_write &&
595 qpu_magic_waddr_is_periph(inst->alu.mul.waddr)) {
596 return true;
597 }
598 }
599
600 return (inst->sig.ldvpm ||
601 inst->sig.ldtmu ||
602 inst->sig.ldtlb ||
603 inst->sig.ldtlbu ||
604 inst->sig.wrtmuc);
605 }
606
607 static bool
608 qpu_merge_inst(const struct v3d_device_info *devinfo,
609 struct v3d_qpu_instr *result,
610 const struct v3d_qpu_instr *a,
611 const struct v3d_qpu_instr *b)
612 {
613 if (a->type != V3D_QPU_INSTR_TYPE_ALU ||
614 b->type != V3D_QPU_INSTR_TYPE_ALU) {
615 return false;
616 }
617
618 /* Can't do more than one peripheral access in an instruction.
619 *
620 * XXX: V3D 4.1 allows TMU read along with a VPM read or write, and
621 * WRTMUC with a TMU magic register write (other than tmuc).
622 */
623 if (qpu_accesses_peripheral(a) && qpu_accesses_peripheral(b))
624 return false;
625
626 struct v3d_qpu_instr merge = *a;
627
628 if (b->alu.add.op != V3D_QPU_A_NOP) {
629 if (a->alu.add.op != V3D_QPU_A_NOP)
630 return false;
631 merge.alu.add = b->alu.add;
632
633 merge.flags.ac = b->flags.ac;
634 merge.flags.apf = b->flags.apf;
635 merge.flags.auf = b->flags.auf;
636 }
637
638 if (b->alu.mul.op != V3D_QPU_M_NOP) {
639 if (a->alu.mul.op != V3D_QPU_M_NOP)
640 return false;
641 merge.alu.mul = b->alu.mul;
642
643 merge.flags.mc = b->flags.mc;
644 merge.flags.mpf = b->flags.mpf;
645 merge.flags.muf = b->flags.muf;
646 }
647
648 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_A)) {
649 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_A) &&
650 a->raddr_a != b->raddr_a) {
651 return false;
652 }
653 merge.raddr_a = b->raddr_a;
654 }
655
656 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_B)) {
657 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_B) &&
658 (a->raddr_b != b->raddr_b ||
659 a->sig.small_imm != b->sig.small_imm)) {
660 return false;
661 }
662 merge.raddr_b = b->raddr_b;
663 }
664
665 merge.sig.thrsw |= b->sig.thrsw;
666 merge.sig.ldunif |= b->sig.ldunif;
667 merge.sig.ldunifrf |= b->sig.ldunifrf;
668 merge.sig.ldunifa |= b->sig.ldunifa;
669 merge.sig.ldunifarf |= b->sig.ldunifarf;
670 merge.sig.ldtmu |= b->sig.ldtmu;
671 merge.sig.ldvary |= b->sig.ldvary;
672 merge.sig.ldvpm |= b->sig.ldvpm;
673 merge.sig.small_imm |= b->sig.small_imm;
674 merge.sig.ldtlb |= b->sig.ldtlb;
675 merge.sig.ldtlbu |= b->sig.ldtlbu;
676 merge.sig.ucb |= b->sig.ucb;
677 merge.sig.rotate |= b->sig.rotate;
678 merge.sig.wrtmuc |= b->sig.wrtmuc;
679
680 if (v3d_qpu_sig_writes_address(devinfo, &a->sig) &&
681 v3d_qpu_sig_writes_address(devinfo, &b->sig))
682 return false;
683 merge.sig_addr |= b->sig_addr;
684 merge.sig_magic |= b->sig_magic;
685
686 uint64_t packed;
687 bool ok = v3d_qpu_instr_pack(devinfo, &merge, &packed);
688
689 *result = merge;
690 /* No modifying the real instructions on failure. */
691 assert(ok || (a != result && b != result));
692
693 return ok;
694 }
695
696 static struct schedule_node *
697 choose_instruction_to_schedule(const struct v3d_device_info *devinfo,
698 struct choose_scoreboard *scoreboard,
699 struct schedule_node *prev_inst)
700 {
701 struct schedule_node *chosen = NULL;
702 int chosen_prio = 0;
703
704 /* Don't pair up anything with a thread switch signal -- emit_thrsw()
705 * will handle pairing it along with filling the delay slots.
706 */
707 if (prev_inst) {
708 if (prev_inst->inst->qpu.sig.thrsw)
709 return NULL;
710 }
711
712 list_for_each_entry(struct schedule_node, n, &scoreboard->dag->heads,
713 dag.link) {
714 const struct v3d_qpu_instr *inst = &n->inst->qpu;
715
716 /* Don't choose the branch instruction until it's the last one
717 * left. We'll move it up to fit its delay slots after we
718 * choose it.
719 */
720 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH &&
721 !list_is_singular(&scoreboard->dag->heads)) {
722 continue;
723 }
724
725 /* "An instruction must not read from a location in physical
726 * regfile A or B that was written to by the previous
727 * instruction."
728 */
729 if (reads_too_soon_after_write(scoreboard, n->inst))
730 continue;
731
732 if (writes_too_soon_after_write(devinfo, scoreboard, n->inst))
733 continue;
734
735 /* "A scoreboard wait must not occur in the first two
736 * instructions of a fragment shader. This is either the
737 * explicit Wait for Scoreboard signal or an implicit wait
738 * with the first tile-buffer read or write instruction."
739 */
740 if (pixel_scoreboard_too_soon(scoreboard, inst))
741 continue;
742
743 /* ldunif and ldvary both write r5, but ldunif does so a tick
744 * sooner. If the ldvary's r5 wasn't used, then ldunif might
745 * otherwise get scheduled so ldunif and ldvary try to update
746 * r5 in the same tick.
747 *
748 * XXX perf: To get good pipelining of a sequence of varying
749 * loads, we need to figure out how to pair the ldvary signal
750 * up to the instruction before the last r5 user in the
751 * previous ldvary sequence. Currently, it usually pairs with
752 * the last r5 user.
753 */
754 if ((inst->sig.ldunif || inst->sig.ldunifa) &&
755 scoreboard->tick == scoreboard->last_ldvary_tick + 1) {
756 continue;
757 }
758
759 /* If we're trying to pair with another instruction, check
760 * that they're compatible.
761 */
762 if (prev_inst) {
763 /* Don't pair up a thread switch signal -- we'll
764 * handle pairing it when we pick it on its own.
765 */
766 if (inst->sig.thrsw)
767 continue;
768
769 if (prev_inst->inst->uniform != -1 &&
770 n->inst->uniform != -1)
771 continue;
772
773 /* Don't merge in something that will lock the TLB.
774 * Hopwefully what we have in inst will release some
775 * other instructions, allowing us to delay the
776 * TLB-locking instruction until later.
777 */
778 if (!scoreboard->tlb_locked && qpu_inst_is_tlb(inst))
779 continue;
780
781 struct v3d_qpu_instr merged_inst;
782 if (!qpu_merge_inst(devinfo, &merged_inst,
783 &prev_inst->inst->qpu, inst)) {
784 continue;
785 }
786 }
787
788 int prio = get_instruction_priority(inst);
789
790 /* Found a valid instruction. If nothing better comes along,
791 * this one works.
792 */
793 if (!chosen) {
794 chosen = n;
795 chosen_prio = prio;
796 continue;
797 }
798
799 if (prio > chosen_prio) {
800 chosen = n;
801 chosen_prio = prio;
802 } else if (prio < chosen_prio) {
803 continue;
804 }
805
806 if (n->delay > chosen->delay) {
807 chosen = n;
808 chosen_prio = prio;
809 } else if (n->delay < chosen->delay) {
810 continue;
811 }
812 }
813
814 return chosen;
815 }
816
817 static void
818 update_scoreboard_for_magic_waddr(struct choose_scoreboard *scoreboard,
819 enum v3d_qpu_waddr waddr)
820 {
821 if (v3d_qpu_magic_waddr_is_sfu(waddr))
822 scoreboard->last_magic_sfu_write_tick = scoreboard->tick;
823 }
824
825 static void
826 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
827 const struct v3d_qpu_instr *inst)
828 {
829 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
830 return;
831
832 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
833
834 if (inst->alu.add.op != V3D_QPU_A_NOP) {
835 if (inst->alu.add.magic_write) {
836 update_scoreboard_for_magic_waddr(scoreboard,
837 inst->alu.add.waddr);
838 }
839 }
840
841 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
842 if (inst->alu.mul.magic_write) {
843 update_scoreboard_for_magic_waddr(scoreboard,
844 inst->alu.mul.waddr);
845 }
846 }
847
848 if (inst->sig.ldvary)
849 scoreboard->last_ldvary_tick = scoreboard->tick;
850
851 if (qpu_inst_is_tlb(inst))
852 scoreboard->tlb_locked = true;
853 }
854
855 static void
856 dump_state(const struct v3d_device_info *devinfo, struct dag *dag)
857 {
858 list_for_each_entry(struct schedule_node, n, &dag->heads, dag.link) {
859 fprintf(stderr, " t=%4d: ", n->unblocked_time);
860 v3d_qpu_dump(devinfo, &n->inst->qpu);
861 fprintf(stderr, "\n");
862
863 util_dynarray_foreach(&n->dag.edges, struct dag_edge, edge) {
864 struct schedule_node *child =
865 (struct schedule_node *)edge->child;
866 if (!child)
867 continue;
868
869 fprintf(stderr, " - ");
870 v3d_qpu_dump(devinfo, &child->inst->qpu);
871 fprintf(stderr, " (%d parents, %c)\n",
872 child->dag.parent_count,
873 edge->data ? 'w' : 'r');
874 }
875 }
876 }
877
878 static uint32_t magic_waddr_latency(enum v3d_qpu_waddr waddr,
879 const struct v3d_qpu_instr *after)
880 {
881 /* Apply some huge latency between texture fetch requests and getting
882 * their results back.
883 *
884 * FIXME: This is actually pretty bogus. If we do:
885 *
886 * mov tmu0_s, a
887 * <a bit of math>
888 * mov tmu0_s, b
889 * load_tmu0
890 * <more math>
891 * load_tmu0
892 *
893 * we count that as worse than
894 *
895 * mov tmu0_s, a
896 * mov tmu0_s, b
897 * <lots of math>
898 * load_tmu0
899 * <more math>
900 * load_tmu0
901 *
902 * because we associate the first load_tmu0 with the *second* tmu0_s.
903 */
904 if (v3d_qpu_magic_waddr_is_tmu(waddr) && v3d_qpu_waits_on_tmu(after))
905 return 100;
906
907 /* Assume that anything depending on us is consuming the SFU result. */
908 if (v3d_qpu_magic_waddr_is_sfu(waddr))
909 return 3;
910
911 return 1;
912 }
913
914 static uint32_t
915 instruction_latency(struct schedule_node *before, struct schedule_node *after)
916 {
917 const struct v3d_qpu_instr *before_inst = &before->inst->qpu;
918 const struct v3d_qpu_instr *after_inst = &after->inst->qpu;
919 uint32_t latency = 1;
920
921 if (before_inst->type != V3D_QPU_INSTR_TYPE_ALU ||
922 after_inst->type != V3D_QPU_INSTR_TYPE_ALU)
923 return latency;
924
925 if (before_inst->alu.add.magic_write) {
926 latency = MAX2(latency,
927 magic_waddr_latency(before_inst->alu.add.waddr,
928 after_inst));
929 }
930
931 if (before_inst->alu.mul.magic_write) {
932 latency = MAX2(latency,
933 magic_waddr_latency(before_inst->alu.mul.waddr,
934 after_inst));
935 }
936
937 return latency;
938 }
939
940 /** Recursive computation of the delay member of a node. */
941 static void
942 compute_delay(struct dag_node *node, void *state)
943 {
944 struct schedule_node *n = (struct schedule_node *)node;
945
946 n->delay = 1;
947
948 util_dynarray_foreach(&n->dag.edges, struct dag_edge, edge) {
949 struct schedule_node *child =
950 (struct schedule_node *)edge->child;
951
952 n->delay = MAX2(n->delay, (child->delay +
953 instruction_latency(n, child)));
954 }
955 }
956
957 /* Removes a DAG head, but removing only the WAR edges. (dag_prune_head()
958 * should be called on it later to finish pruning the other edges).
959 */
960 static void
961 pre_remove_head(struct dag *dag, struct schedule_node *n)
962 {
963 list_delinit(&n->dag.link);
964
965 util_dynarray_foreach(&n->dag.edges, struct dag_edge, edge) {
966 if (edge->data)
967 dag_remove_edge(dag, edge);
968 }
969 }
970
971 static void
972 mark_instruction_scheduled(struct dag *dag,
973 uint32_t time,
974 struct schedule_node *node)
975 {
976 if (!node)
977 return;
978
979 util_dynarray_foreach(&node->dag.edges, struct dag_edge, edge) {
980 struct schedule_node *child =
981 (struct schedule_node *)edge->child;
982
983 if (!child)
984 continue;
985
986 uint32_t latency = instruction_latency(node, child);
987
988 child->unblocked_time = MAX2(child->unblocked_time,
989 time + latency);
990 }
991 dag_prune_head(dag, &node->dag);
992 }
993
994 static void
995 insert_scheduled_instruction(struct v3d_compile *c,
996 struct qblock *block,
997 struct choose_scoreboard *scoreboard,
998 struct qinst *inst)
999 {
1000 list_addtail(&inst->link, &block->instructions);
1001
1002 update_scoreboard_for_chosen(scoreboard, &inst->qpu);
1003 c->qpu_inst_count++;
1004 scoreboard->tick++;
1005 }
1006
1007 static struct qinst *
1008 vir_nop()
1009 {
1010 struct qreg undef = vir_nop_reg();
1011 struct qinst *qinst = vir_add_inst(V3D_QPU_A_NOP, undef, undef, undef);
1012
1013 return qinst;
1014 }
1015
1016 static void
1017 emit_nop(struct v3d_compile *c, struct qblock *block,
1018 struct choose_scoreboard *scoreboard)
1019 {
1020 insert_scheduled_instruction(c, block, scoreboard, vir_nop());
1021 }
1022
1023 static bool
1024 qpu_instruction_valid_in_thrend_slot(struct v3d_compile *c,
1025 const struct qinst *qinst, int slot)
1026 {
1027 const struct v3d_qpu_instr *inst = &qinst->qpu;
1028
1029 /* Only TLB Z writes are prohibited in the last slot, but we don't
1030 * have those flagged so prohibit all TLB ops for now.
1031 */
1032 if (slot == 2 && qpu_inst_is_tlb(inst))
1033 return false;
1034
1035 if (slot > 0 && qinst->uniform != ~0)
1036 return false;
1037
1038 if (v3d_qpu_uses_vpm(inst))
1039 return false;
1040
1041 if (inst->sig.ldvary)
1042 return false;
1043
1044 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
1045 /* GFXH-1625: TMUWT not allowed in the final instruction. */
1046 if (slot == 2 && inst->alu.add.op == V3D_QPU_A_TMUWT)
1047 return false;
1048
1049 /* No writing physical registers at the end. */
1050 if (!inst->alu.add.magic_write ||
1051 !inst->alu.mul.magic_write) {
1052 return false;
1053 }
1054
1055 if (c->devinfo->ver < 40 && inst->alu.add.op == V3D_QPU_A_SETMSF)
1056 return false;
1057
1058 /* RF0-2 might be overwritten during the delay slots by
1059 * fragment shader setup.
1060 */
1061 if (inst->raddr_a < 3 &&
1062 (inst->alu.add.a == V3D_QPU_MUX_A ||
1063 inst->alu.add.b == V3D_QPU_MUX_A ||
1064 inst->alu.mul.a == V3D_QPU_MUX_A ||
1065 inst->alu.mul.b == V3D_QPU_MUX_A)) {
1066 return false;
1067 }
1068
1069 if (inst->raddr_b < 3 &&
1070 !inst->sig.small_imm &&
1071 (inst->alu.add.a == V3D_QPU_MUX_B ||
1072 inst->alu.add.b == V3D_QPU_MUX_B ||
1073 inst->alu.mul.a == V3D_QPU_MUX_B ||
1074 inst->alu.mul.b == V3D_QPU_MUX_B)) {
1075 return false;
1076 }
1077 }
1078
1079 return true;
1080 }
1081
1082 static bool
1083 valid_thrsw_sequence(struct v3d_compile *c, struct choose_scoreboard *scoreboard,
1084 struct qinst *qinst, int instructions_in_sequence,
1085 bool is_thrend)
1086 {
1087 /* No emitting our thrsw while the previous thrsw hasn't happened yet. */
1088 if (scoreboard->last_thrsw_tick + 3 >
1089 scoreboard->tick - instructions_in_sequence) {
1090 return false;
1091 }
1092
1093 for (int slot = 0; slot < instructions_in_sequence; slot++) {
1094 /* No scheduling SFU when the result would land in the other
1095 * thread. The simulator complains for safety, though it
1096 * would only occur for dead code in our case.
1097 */
1098 if (slot > 0 &&
1099 qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
1100 (v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.add.waddr) ||
1101 v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.mul.waddr))) {
1102 return false;
1103 }
1104
1105 if (slot > 0 && qinst->qpu.sig.ldvary)
1106 return false;
1107
1108 if (is_thrend &&
1109 !qpu_instruction_valid_in_thrend_slot(c, qinst, slot)) {
1110 return false;
1111 }
1112
1113 /* Note that the list is circular, so we can only do this up
1114 * to instructions_in_sequence.
1115 */
1116 qinst = (struct qinst *)qinst->link.next;
1117 }
1118
1119 return true;
1120 }
1121
1122 /**
1123 * Emits a THRSW signal in the stream, trying to move it up to pair with
1124 * another instruction.
1125 */
1126 static int
1127 emit_thrsw(struct v3d_compile *c,
1128 struct qblock *block,
1129 struct choose_scoreboard *scoreboard,
1130 struct qinst *inst,
1131 bool is_thrend)
1132 {
1133 int time = 0;
1134
1135 /* There should be nothing in a thrsw inst being scheduled other than
1136 * the signal bits.
1137 */
1138 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);
1139 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP);
1140 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP);
1141
1142 /* Find how far back into previous instructions we can put the THRSW. */
1143 int slots_filled = 0;
1144 struct qinst *merge_inst = NULL;
1145 vir_for_each_inst_rev(prev_inst, block) {
1146 struct v3d_qpu_sig sig = prev_inst->qpu.sig;
1147 sig.thrsw = true;
1148 uint32_t packed_sig;
1149
1150 if (!v3d_qpu_sig_pack(c->devinfo, &sig, &packed_sig))
1151 break;
1152
1153 if (!valid_thrsw_sequence(c, scoreboard,
1154 prev_inst, slots_filled + 1,
1155 is_thrend)) {
1156 break;
1157 }
1158
1159 merge_inst = prev_inst;
1160 if (++slots_filled == 3)
1161 break;
1162 }
1163
1164 bool needs_free = false;
1165 if (merge_inst) {
1166 merge_inst->qpu.sig.thrsw = true;
1167 needs_free = true;
1168 scoreboard->last_thrsw_tick = scoreboard->tick - slots_filled;
1169 } else {
1170 scoreboard->last_thrsw_tick = scoreboard->tick;
1171 insert_scheduled_instruction(c, block, scoreboard, inst);
1172 time++;
1173 slots_filled++;
1174 merge_inst = inst;
1175 }
1176
1177 /* Insert any extra delay slot NOPs we need. */
1178 for (int i = 0; i < 3 - slots_filled; i++) {
1179 emit_nop(c, block, scoreboard);
1180 time++;
1181 }
1182
1183 /* If we're emitting the last THRSW (other than program end), then
1184 * signal that to the HW by emitting two THRSWs in a row.
1185 */
1186 if (inst->is_last_thrsw) {
1187 struct qinst *second_inst =
1188 (struct qinst *)merge_inst->link.next;
1189 second_inst->qpu.sig.thrsw = true;
1190 }
1191
1192 /* If we put our THRSW into another instruction, free up the
1193 * instruction that didn't end up scheduled into the list.
1194 */
1195 if (needs_free)
1196 free(inst);
1197
1198 return time;
1199 }
1200
1201 static uint32_t
1202 schedule_instructions(struct v3d_compile *c,
1203 struct choose_scoreboard *scoreboard,
1204 struct qblock *block,
1205 enum quniform_contents *orig_uniform_contents,
1206 uint32_t *orig_uniform_data,
1207 uint32_t *next_uniform)
1208 {
1209 const struct v3d_device_info *devinfo = c->devinfo;
1210 uint32_t time = 0;
1211
1212 while (!list_empty(&scoreboard->dag->heads)) {
1213 struct schedule_node *chosen =
1214 choose_instruction_to_schedule(devinfo,
1215 scoreboard,
1216 NULL);
1217 struct schedule_node *merge = NULL;
1218
1219 /* If there are no valid instructions to schedule, drop a NOP
1220 * in.
1221 */
1222 struct qinst *qinst = chosen ? chosen->inst : vir_nop();
1223 struct v3d_qpu_instr *inst = &qinst->qpu;
1224
1225 if (debug) {
1226 fprintf(stderr, "t=%4d: current list:\n",
1227 time);
1228 dump_state(devinfo, scoreboard->dag);
1229 fprintf(stderr, "t=%4d: chose: ", time);
1230 v3d_qpu_dump(devinfo, inst);
1231 fprintf(stderr, "\n");
1232 }
1233
1234 /* We can't mark_instruction_scheduled() the chosen inst until
1235 * we're done identifying instructions to merge, so put the
1236 * merged instructions on a list for a moment.
1237 */
1238 struct list_head merged_list;
1239 list_inithead(&merged_list);
1240
1241 /* Schedule this instruction onto the QPU list. Also try to
1242 * find an instruction to pair with it.
1243 */
1244 if (chosen) {
1245 time = MAX2(chosen->unblocked_time, time);
1246 pre_remove_head(scoreboard->dag, chosen);
1247
1248 while ((merge =
1249 choose_instruction_to_schedule(devinfo,
1250 scoreboard,
1251 chosen))) {
1252 time = MAX2(merge->unblocked_time, time);
1253 pre_remove_head(scoreboard->dag, chosen);
1254 list_addtail(&merge->link, &merged_list);
1255 (void)qpu_merge_inst(devinfo, inst,
1256 inst, &merge->inst->qpu);
1257 if (merge->inst->uniform != -1) {
1258 chosen->inst->uniform =
1259 merge->inst->uniform;
1260 }
1261
1262 if (debug) {
1263 fprintf(stderr, "t=%4d: merging: ",
1264 time);
1265 v3d_qpu_dump(devinfo, &merge->inst->qpu);
1266 fprintf(stderr, "\n");
1267 fprintf(stderr, " result: ");
1268 v3d_qpu_dump(devinfo, inst);
1269 fprintf(stderr, "\n");
1270 }
1271 }
1272 }
1273
1274 /* Update the uniform index for the rewritten location --
1275 * branch target updating will still need to change
1276 * c->uniform_data[] using this index.
1277 */
1278 if (qinst->uniform != -1) {
1279 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
1280 block->branch_uniform = *next_uniform;
1281
1282 c->uniform_data[*next_uniform] =
1283 orig_uniform_data[qinst->uniform];
1284 c->uniform_contents[*next_uniform] =
1285 orig_uniform_contents[qinst->uniform];
1286 qinst->uniform = *next_uniform;
1287 (*next_uniform)++;
1288 }
1289
1290 if (debug) {
1291 fprintf(stderr, "\n");
1292 }
1293
1294 /* Now that we've scheduled a new instruction, some of its
1295 * children can be promoted to the list of instructions ready to
1296 * be scheduled. Update the children's unblocked time for this
1297 * DAG edge as we do so.
1298 */
1299 mark_instruction_scheduled(scoreboard->dag, time, chosen);
1300 list_for_each_entry(struct schedule_node, merge, &merged_list,
1301 link) {
1302 mark_instruction_scheduled(scoreboard->dag, time, merge);
1303
1304 /* The merged VIR instruction doesn't get re-added to the
1305 * block, so free it now.
1306 */
1307 free(merge->inst);
1308 }
1309
1310 if (inst->sig.thrsw) {
1311 time += emit_thrsw(c, block, scoreboard, qinst, false);
1312 } else {
1313 insert_scheduled_instruction(c, block,
1314 scoreboard, qinst);
1315
1316 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
1317 block->branch_qpu_ip = c->qpu_inst_count - 1;
1318 /* Fill the delay slots.
1319 *
1320 * We should fill these with actual instructions,
1321 * instead, but that will probably need to be done
1322 * after this, once we know what the leading
1323 * instructions of the successors are (so we can
1324 * handle A/B register file write latency)
1325 */
1326 for (int i = 0; i < 3; i++)
1327 emit_nop(c, block, scoreboard);
1328 }
1329 }
1330 }
1331
1332 return time;
1333 }
1334
1335 static uint32_t
1336 qpu_schedule_instructions_block(struct v3d_compile *c,
1337 struct choose_scoreboard *scoreboard,
1338 struct qblock *block,
1339 enum quniform_contents *orig_uniform_contents,
1340 uint32_t *orig_uniform_data,
1341 uint32_t *next_uniform)
1342 {
1343 void *mem_ctx = ralloc_context(NULL);
1344 scoreboard->dag = dag_create(mem_ctx);
1345 struct list_head setup_list;
1346
1347 list_inithead(&setup_list);
1348
1349 /* Wrap each instruction in a scheduler structure. */
1350 while (!list_empty(&block->instructions)) {
1351 struct qinst *qinst = (struct qinst *)block->instructions.next;
1352 struct schedule_node *n =
1353 rzalloc(mem_ctx, struct schedule_node);
1354
1355 dag_init_node(scoreboard->dag, &n->dag);
1356 n->inst = qinst;
1357
1358 list_del(&qinst->link);
1359 list_addtail(&n->link, &setup_list);
1360 }
1361
1362 calculate_forward_deps(c, scoreboard->dag, &setup_list);
1363 calculate_reverse_deps(c, scoreboard->dag, &setup_list);
1364
1365 dag_traverse_bottom_up(scoreboard->dag, compute_delay, NULL);
1366
1367 uint32_t cycles = schedule_instructions(c, scoreboard, block,
1368 orig_uniform_contents,
1369 orig_uniform_data,
1370 next_uniform);
1371
1372 ralloc_free(mem_ctx);
1373 scoreboard->dag = NULL;
1374
1375 return cycles;
1376 }
1377
1378 static void
1379 qpu_set_branch_targets(struct v3d_compile *c)
1380 {
1381 vir_for_each_block(block, c) {
1382 /* The end block of the program has no branch. */
1383 if (!block->successors[0])
1384 continue;
1385
1386 /* If there was no branch instruction, then the successor
1387 * block must follow immediately after this one.
1388 */
1389 if (block->branch_qpu_ip == ~0) {
1390 assert(block->end_qpu_ip + 1 ==
1391 block->successors[0]->start_qpu_ip);
1392 continue;
1393 }
1394
1395 /* Walk back through the delay slots to find the branch
1396 * instr.
1397 */
1398 struct list_head *entry = block->instructions.prev;
1399 for (int i = 0; i < 3; i++)
1400 entry = entry->prev;
1401 struct qinst *branch = container_of(entry, branch, link);
1402 assert(branch->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH);
1403
1404 /* Make sure that the if-we-don't-jump
1405 * successor was scheduled just after the
1406 * delay slots.
1407 */
1408 assert(!block->successors[1] ||
1409 block->successors[1]->start_qpu_ip ==
1410 block->branch_qpu_ip + 4);
1411
1412 branch->qpu.branch.offset =
1413 ((block->successors[0]->start_qpu_ip -
1414 (block->branch_qpu_ip + 4)) *
1415 sizeof(uint64_t));
1416
1417 /* Set up the relative offset to jump in the
1418 * uniform stream.
1419 *
1420 * Use a temporary here, because
1421 * uniform_data[inst->uniform] may be shared
1422 * between multiple instructions.
1423 */
1424 assert(c->uniform_contents[branch->uniform] == QUNIFORM_CONSTANT);
1425 c->uniform_data[branch->uniform] =
1426 (block->successors[0]->start_uniform -
1427 (block->branch_uniform + 1)) * 4;
1428 }
1429 }
1430
1431 uint32_t
1432 v3d_qpu_schedule_instructions(struct v3d_compile *c)
1433 {
1434 const struct v3d_device_info *devinfo = c->devinfo;
1435 struct qblock *end_block = list_last_entry(&c->blocks,
1436 struct qblock, link);
1437
1438 /* We reorder the uniforms as we schedule instructions, so save the
1439 * old data off and replace it.
1440 */
1441 uint32_t *uniform_data = c->uniform_data;
1442 enum quniform_contents *uniform_contents = c->uniform_contents;
1443 c->uniform_contents = ralloc_array(c, enum quniform_contents,
1444 c->num_uniforms);
1445 c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
1446 c->uniform_array_size = c->num_uniforms;
1447 uint32_t next_uniform = 0;
1448
1449 struct choose_scoreboard scoreboard;
1450 memset(&scoreboard, 0, sizeof(scoreboard));
1451 scoreboard.last_ldvary_tick = -10;
1452 scoreboard.last_magic_sfu_write_tick = -10;
1453 scoreboard.last_uniforms_reset_tick = -10;
1454 scoreboard.last_thrsw_tick = -10;
1455
1456 if (debug) {
1457 fprintf(stderr, "Pre-schedule instructions\n");
1458 vir_for_each_block(block, c) {
1459 fprintf(stderr, "BLOCK %d\n", block->index);
1460 list_for_each_entry(struct qinst, qinst,
1461 &block->instructions, link) {
1462 v3d_qpu_dump(devinfo, &qinst->qpu);
1463 fprintf(stderr, "\n");
1464 }
1465 }
1466 fprintf(stderr, "\n");
1467 }
1468
1469 uint32_t cycles = 0;
1470 vir_for_each_block(block, c) {
1471 block->start_qpu_ip = c->qpu_inst_count;
1472 block->branch_qpu_ip = ~0;
1473 block->start_uniform = next_uniform;
1474
1475 cycles += qpu_schedule_instructions_block(c,
1476 &scoreboard,
1477 block,
1478 uniform_contents,
1479 uniform_data,
1480 &next_uniform);
1481
1482 block->end_qpu_ip = c->qpu_inst_count - 1;
1483 }
1484
1485 /* Emit the program-end THRSW instruction. */;
1486 struct qinst *thrsw = vir_nop();
1487 thrsw->qpu.sig.thrsw = true;
1488 emit_thrsw(c, end_block, &scoreboard, thrsw, true);
1489
1490 qpu_set_branch_targets(c);
1491
1492 assert(next_uniform == c->num_uniforms);
1493
1494 return cycles;
1495 }