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v3d: Add support for the TMUWT instruction.
[mesa.git] / src / broadcom / compiler / qpu_schedule.c
1 /*
2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2017 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 /**
26 * @file
27 *
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
32 *
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
35 */
36
37 #include "qpu/qpu_disasm.h"
38 #include "v3d_compiler.h"
39 #include "util/ralloc.h"
40
41 static bool debug;
42
43 struct schedule_node_child;
44
45 struct schedule_node {
46 struct list_head link;
47 struct qinst *inst;
48 struct schedule_node_child *children;
49 uint32_t child_count;
50 uint32_t child_array_size;
51 uint32_t parent_count;
52
53 /* Longest cycles + instruction_latency() of any parent of this node. */
54 uint32_t unblocked_time;
55
56 /**
57 * Minimum number of cycles from scheduling this instruction until the
58 * end of the program, based on the slowest dependency chain through
59 * the children.
60 */
61 uint32_t delay;
62
63 /**
64 * cycles between this instruction being scheduled and when its result
65 * can be consumed.
66 */
67 uint32_t latency;
68 };
69
70 struct schedule_node_child {
71 struct schedule_node *node;
72 bool write_after_read;
73 };
74
75 /* When walking the instructions in reverse, we need to swap before/after in
76 * add_dep().
77 */
78 enum direction { F, R };
79
80 struct schedule_state {
81 const struct v3d_device_info *devinfo;
82 struct schedule_node *last_r[6];
83 struct schedule_node *last_rf[64];
84 struct schedule_node *last_sf;
85 struct schedule_node *last_vpm_read;
86 struct schedule_node *last_tmu_write;
87 struct schedule_node *last_tmu_config;
88 struct schedule_node *last_tlb;
89 struct schedule_node *last_vpm;
90 struct schedule_node *last_unif;
91 struct schedule_node *last_rtop;
92 enum direction dir;
93 /* Estimated cycle when the current instruction would start. */
94 uint32_t time;
95 };
96
97 static void
98 add_dep(struct schedule_state *state,
99 struct schedule_node *before,
100 struct schedule_node *after,
101 bool write)
102 {
103 bool write_after_read = !write && state->dir == R;
104
105 if (!before || !after)
106 return;
107
108 assert(before != after);
109
110 if (state->dir == R) {
111 struct schedule_node *t = before;
112 before = after;
113 after = t;
114 }
115
116 for (int i = 0; i < before->child_count; i++) {
117 if (before->children[i].node == after &&
118 (before->children[i].write_after_read == write_after_read)) {
119 return;
120 }
121 }
122
123 if (before->child_array_size <= before->child_count) {
124 before->child_array_size = MAX2(before->child_array_size * 2, 16);
125 before->children = reralloc(before, before->children,
126 struct schedule_node_child,
127 before->child_array_size);
128 }
129
130 before->children[before->child_count].node = after;
131 before->children[before->child_count].write_after_read =
132 write_after_read;
133 before->child_count++;
134 after->parent_count++;
135 }
136
137 static void
138 add_read_dep(struct schedule_state *state,
139 struct schedule_node *before,
140 struct schedule_node *after)
141 {
142 add_dep(state, before, after, false);
143 }
144
145 static void
146 add_write_dep(struct schedule_state *state,
147 struct schedule_node **before,
148 struct schedule_node *after)
149 {
150 add_dep(state, *before, after, true);
151 *before = after;
152 }
153
154 static bool
155 qpu_inst_is_tlb(const struct v3d_qpu_instr *inst)
156 {
157 if (inst->type != V3D_QPU_INSTR_TYPE_ALU)
158 return false;
159
160 if (inst->alu.add.magic_write &&
161 (inst->alu.add.waddr == V3D_QPU_WADDR_TLB ||
162 inst->alu.add.waddr == V3D_QPU_WADDR_TLBU))
163 return true;
164
165 if (inst->alu.mul.magic_write &&
166 (inst->alu.mul.waddr == V3D_QPU_WADDR_TLB ||
167 inst->alu.mul.waddr == V3D_QPU_WADDR_TLBU))
168 return true;
169
170 return false;
171 }
172
173 static void
174 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
175 enum v3d_qpu_mux mux)
176 {
177 switch (mux) {
178 case V3D_QPU_MUX_A:
179 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n);
180 break;
181 case V3D_QPU_MUX_B:
182 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_b], n);
183 break;
184 default:
185 add_read_dep(state, state->last_r[mux - V3D_QPU_MUX_R0], n);
186 break;
187 }
188 }
189
190
191 static void
192 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
193 uint32_t waddr, bool magic)
194 {
195 if (!magic) {
196 add_write_dep(state, &state->last_rf[waddr], n);
197 } else if (v3d_qpu_magic_waddr_is_tmu(waddr)) {
198 add_write_dep(state, &state->last_tmu_write, n);
199 switch (waddr) {
200 case V3D_QPU_WADDR_TMUS:
201 case V3D_QPU_WADDR_TMUSCM:
202 case V3D_QPU_WADDR_TMUSF:
203 case V3D_QPU_WADDR_TMUSLOD:
204 add_write_dep(state, &state->last_tmu_config, n);
205 break;
206 default:
207 break;
208 }
209 } else if (v3d_qpu_magic_waddr_is_sfu(waddr)) {
210 /* Handled by v3d_qpu_writes_r4() check. */
211 } else {
212 switch (waddr) {
213 case V3D_QPU_WADDR_R0:
214 case V3D_QPU_WADDR_R1:
215 case V3D_QPU_WADDR_R2:
216 add_write_dep(state,
217 &state->last_r[waddr - V3D_QPU_WADDR_R0],
218 n);
219 break;
220 case V3D_QPU_WADDR_R3:
221 case V3D_QPU_WADDR_R4:
222 case V3D_QPU_WADDR_R5:
223 /* Handled by v3d_qpu_writes_r*() checks below. */
224 break;
225
226 case V3D_QPU_WADDR_VPM:
227 case V3D_QPU_WADDR_VPMU:
228 add_write_dep(state, &state->last_vpm, n);
229 break;
230
231 case V3D_QPU_WADDR_TLB:
232 case V3D_QPU_WADDR_TLBU:
233 add_write_dep(state, &state->last_tlb, n);
234 break;
235
236 case V3D_QPU_WADDR_NOP:
237 break;
238
239 default:
240 fprintf(stderr, "Unknown waddr %d\n", waddr);
241 abort();
242 }
243 }
244 }
245
246 static void
247 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
248 enum v3d_qpu_cond cond)
249 {
250 if (cond != V3D_QPU_COND_NONE)
251 add_read_dep(state, state->last_sf, n);
252 }
253
254 static void
255 process_pf_deps(struct schedule_state *state, struct schedule_node *n,
256 enum v3d_qpu_pf pf)
257 {
258 if (pf != V3D_QPU_PF_NONE)
259 add_write_dep(state, &state->last_sf, n);
260 }
261
262 static void
263 process_uf_deps(struct schedule_state *state, struct schedule_node *n,
264 enum v3d_qpu_uf uf)
265 {
266 if (uf != V3D_QPU_UF_NONE)
267 add_write_dep(state, &state->last_sf, n);
268 }
269
270 /**
271 * Common code for dependencies that need to be tracked both forward and
272 * backward.
273 *
274 * This is for things like "all reads of r4 have to happen between the r4
275 * writes that surround them".
276 */
277 static void
278 calculate_deps(struct schedule_state *state, struct schedule_node *n)
279 {
280 const struct v3d_device_info *devinfo = state->devinfo;
281 struct qinst *qinst = n->inst;
282 struct v3d_qpu_instr *inst = &qinst->qpu;
283
284 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
285 if (inst->branch.cond != V3D_QPU_BRANCH_COND_ALWAYS)
286 add_read_dep(state, state->last_sf, n);
287
288 /* XXX: BDI */
289 /* XXX: BDU */
290 /* XXX: ub */
291 /* XXX: raddr_a */
292
293 add_write_dep(state, &state->last_unif, n);
294 return;
295 }
296
297 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
298
299 /* XXX: LOAD_IMM */
300
301 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0)
302 process_mux_deps(state, n, inst->alu.add.a);
303 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1)
304 process_mux_deps(state, n, inst->alu.add.b);
305
306 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0)
307 process_mux_deps(state, n, inst->alu.mul.a);
308 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1)
309 process_mux_deps(state, n, inst->alu.mul.b);
310
311 switch (inst->alu.add.op) {
312 case V3D_QPU_A_VPMSETUP:
313 /* Could distinguish read/write by unpacking the uniform. */
314 add_write_dep(state, &state->last_vpm, n);
315 add_write_dep(state, &state->last_vpm_read, n);
316 break;
317
318 case V3D_QPU_A_STVPMV:
319 case V3D_QPU_A_STVPMD:
320 case V3D_QPU_A_STVPMP:
321 add_write_dep(state, &state->last_vpm, n);
322 break;
323
324 case V3D_QPU_A_VPMWT:
325 add_read_dep(state, state->last_vpm, n);
326 break;
327
328 case V3D_QPU_A_MSF:
329 add_read_dep(state, state->last_tlb, n);
330 break;
331
332 case V3D_QPU_A_SETMSF:
333 case V3D_QPU_A_SETREVF:
334 add_write_dep(state, &state->last_tlb, n);
335 break;
336
337 case V3D_QPU_A_FLAPUSH:
338 case V3D_QPU_A_FLBPUSH:
339 case V3D_QPU_A_VFLA:
340 case V3D_QPU_A_VFLNA:
341 case V3D_QPU_A_VFLB:
342 case V3D_QPU_A_VFLNB:
343 add_read_dep(state, state->last_sf, n);
344 break;
345
346 case V3D_QPU_A_FLPOP:
347 add_write_dep(state, &state->last_sf, n);
348 break;
349
350 default:
351 break;
352 }
353
354 switch (inst->alu.mul.op) {
355 case V3D_QPU_M_MULTOP:
356 case V3D_QPU_M_UMUL24:
357 /* MULTOP sets rtop, and UMUL24 implicitly reads rtop and
358 * resets it to 0. We could possibly reorder umul24s relative
359 * to each other, but for now just keep all the MUL parts in
360 * order.
361 */
362 add_write_dep(state, &state->last_rtop, n);
363 break;
364 default:
365 break;
366 }
367
368 if (inst->alu.add.op != V3D_QPU_A_NOP) {
369 process_waddr_deps(state, n, inst->alu.add.waddr,
370 inst->alu.add.magic_write);
371 }
372 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
373 process_waddr_deps(state, n, inst->alu.mul.waddr,
374 inst->alu.mul.magic_write);
375 }
376 if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) {
377 process_waddr_deps(state, n, inst->sig_addr,
378 inst->sig_magic);
379 }
380
381 if (v3d_qpu_writes_r3(devinfo, inst))
382 add_write_dep(state, &state->last_r[3], n);
383 if (v3d_qpu_writes_r4(devinfo, inst))
384 add_write_dep(state, &state->last_r[4], n);
385 if (v3d_qpu_writes_r5(devinfo, inst))
386 add_write_dep(state, &state->last_r[5], n);
387
388 if (inst->sig.thrsw) {
389 /* All accumulator contents and flags are undefined after the
390 * switch.
391 */
392 for (int i = 0; i < ARRAY_SIZE(state->last_r); i++)
393 add_write_dep(state, &state->last_r[i], n);
394 add_write_dep(state, &state->last_sf, n);
395
396 /* Scoreboard-locking operations have to stay after the last
397 * thread switch.
398 */
399 add_write_dep(state, &state->last_tlb, n);
400
401 add_write_dep(state, &state->last_tmu_write, n);
402 add_write_dep(state, &state->last_tmu_config, n);
403 }
404
405 if (v3d_qpu_waits_on_tmu(inst)) {
406 /* TMU loads are coming from a FIFO, so ordering is important.
407 */
408 add_write_dep(state, &state->last_tmu_write, n);
409 }
410
411 if (inst->sig.wrtmuc)
412 add_write_dep(state, &state->last_tmu_config, n);
413
414 if (inst->sig.ldtlb | inst->sig.ldtlbu)
415 add_read_dep(state, state->last_tlb, n);
416
417 if (inst->sig.ldvpm)
418 add_write_dep(state, &state->last_vpm_read, n);
419
420 /* inst->sig.ldunif or sideband uniform read */
421 if (qinst->uniform != ~0)
422 add_write_dep(state, &state->last_unif, n);
423
424 process_cond_deps(state, n, inst->flags.ac);
425 process_cond_deps(state, n, inst->flags.mc);
426 process_pf_deps(state, n, inst->flags.apf);
427 process_pf_deps(state, n, inst->flags.mpf);
428 process_uf_deps(state, n, inst->flags.auf);
429 process_uf_deps(state, n, inst->flags.muf);
430 }
431
432 static void
433 calculate_forward_deps(struct v3d_compile *c, struct list_head *schedule_list)
434 {
435 struct schedule_state state;
436
437 memset(&state, 0, sizeof(state));
438 state.devinfo = c->devinfo;
439 state.dir = F;
440
441 list_for_each_entry(struct schedule_node, node, schedule_list, link)
442 calculate_deps(&state, node);
443 }
444
445 static void
446 calculate_reverse_deps(struct v3d_compile *c, struct list_head *schedule_list)
447 {
448 struct list_head *node;
449 struct schedule_state state;
450
451 memset(&state, 0, sizeof(state));
452 state.devinfo = c->devinfo;
453 state.dir = R;
454
455 for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
456 calculate_deps(&state, (struct schedule_node *)node);
457 }
458 }
459
460 struct choose_scoreboard {
461 int tick;
462 int last_magic_sfu_write_tick;
463 int last_ldvary_tick;
464 int last_uniforms_reset_tick;
465 bool tlb_locked;
466 };
467
468 static bool
469 mux_reads_too_soon(struct choose_scoreboard *scoreboard,
470 const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux)
471 {
472 switch (mux) {
473 case V3D_QPU_MUX_R4:
474 if (scoreboard->tick - scoreboard->last_magic_sfu_write_tick <= 2)
475 return true;
476 break;
477
478 case V3D_QPU_MUX_R5:
479 if (scoreboard->tick - scoreboard->last_ldvary_tick <= 1)
480 return true;
481 break;
482 default:
483 break;
484 }
485
486 return false;
487 }
488
489 static bool
490 reads_too_soon_after_write(struct choose_scoreboard *scoreboard,
491 struct qinst *qinst)
492 {
493 const struct v3d_qpu_instr *inst = &qinst->qpu;
494
495 /* XXX: Branching off of raddr. */
496 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
497 return false;
498
499 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
500
501 if (inst->alu.add.op != V3D_QPU_A_NOP) {
502 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0 &&
503 mux_reads_too_soon(scoreboard, inst, inst->alu.add.a)) {
504 return true;
505 }
506 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1 &&
507 mux_reads_too_soon(scoreboard, inst, inst->alu.add.b)) {
508 return true;
509 }
510 }
511
512 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
513 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0 &&
514 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.a)) {
515 return true;
516 }
517 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1 &&
518 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.b)) {
519 return true;
520 }
521 }
522
523 /* XXX: imm */
524
525 return false;
526 }
527
528 static bool
529 writes_too_soon_after_write(const struct v3d_device_info *devinfo,
530 struct choose_scoreboard *scoreboard,
531 struct qinst *qinst)
532 {
533 const struct v3d_qpu_instr *inst = &qinst->qpu;
534
535 /* Don't schedule any other r4 write too soon after an SFU write.
536 * This would normally be prevented by dependency tracking, but might
537 * occur if a dead SFU computation makes it to scheduling.
538 */
539 if (scoreboard->tick - scoreboard->last_magic_sfu_write_tick < 2 &&
540 v3d_qpu_writes_r4(devinfo, inst))
541 return true;
542
543 return false;
544 }
545
546 static bool
547 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard,
548 const struct v3d_qpu_instr *inst)
549 {
550 return (scoreboard->tick == 0 && qpu_inst_is_tlb(inst));
551 }
552
553 static int
554 get_instruction_priority(const struct v3d_qpu_instr *inst)
555 {
556 uint32_t baseline_score;
557 uint32_t next_score = 0;
558
559 /* Schedule TLB operations as late as possible, to get more
560 * parallelism between shaders.
561 */
562 if (qpu_inst_is_tlb(inst))
563 return next_score;
564 next_score++;
565
566 /* Schedule texture read results collection late to hide latency. */
567 if (v3d_qpu_waits_on_tmu(inst))
568 return next_score;
569 next_score++;
570
571 /* Default score for things that aren't otherwise special. */
572 baseline_score = next_score;
573 next_score++;
574
575 /* Schedule texture read setup early to hide their latency better. */
576 if (v3d_qpu_writes_tmu(inst))
577 return next_score;
578 next_score++;
579
580 return baseline_score;
581 }
582
583 static bool
584 qpu_magic_waddr_is_periph(enum v3d_qpu_waddr waddr)
585 {
586 return (v3d_qpu_magic_waddr_is_tmu(waddr) ||
587 v3d_qpu_magic_waddr_is_sfu(waddr) ||
588 v3d_qpu_magic_waddr_is_tlb(waddr) ||
589 v3d_qpu_magic_waddr_is_vpm(waddr) ||
590 v3d_qpu_magic_waddr_is_tsy(waddr));
591 }
592
593 static bool
594 qpu_accesses_peripheral(const struct v3d_qpu_instr *inst)
595 {
596 if (v3d_qpu_uses_vpm(inst))
597 return true;
598 if (v3d_qpu_uses_sfu(inst))
599 return true;
600
601 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
602 if (inst->alu.add.op != V3D_QPU_A_NOP &&
603 inst->alu.add.magic_write &&
604 qpu_magic_waddr_is_periph(inst->alu.add.waddr)) {
605 return true;
606 }
607
608 if (inst->alu.add.op == V3D_QPU_A_TMUWT)
609 return true;
610
611 if (inst->alu.mul.op != V3D_QPU_M_NOP &&
612 inst->alu.mul.magic_write &&
613 qpu_magic_waddr_is_periph(inst->alu.mul.waddr)) {
614 return true;
615 }
616 }
617
618 return (inst->sig.ldvpm ||
619 inst->sig.ldtmu ||
620 inst->sig.ldtlb ||
621 inst->sig.ldtlbu ||
622 inst->sig.wrtmuc);
623 }
624
625 static bool
626 qpu_merge_inst(const struct v3d_device_info *devinfo,
627 struct v3d_qpu_instr *result,
628 const struct v3d_qpu_instr *a,
629 const struct v3d_qpu_instr *b)
630 {
631 if (a->type != V3D_QPU_INSTR_TYPE_ALU ||
632 b->type != V3D_QPU_INSTR_TYPE_ALU) {
633 return false;
634 }
635
636 /* Can't do more than one peripheral access in an instruction.
637 *
638 * XXX: V3D 4.1 allows TMU read along with a VPM read or write, and
639 * WRTMUC with a TMU magic register write (other than tmuc).
640 */
641 if (qpu_accesses_peripheral(a) && qpu_accesses_peripheral(b))
642 return false;
643
644 struct v3d_qpu_instr merge = *a;
645
646 if (b->alu.add.op != V3D_QPU_A_NOP) {
647 if (a->alu.add.op != V3D_QPU_A_NOP)
648 return false;
649 merge.alu.add = b->alu.add;
650
651 merge.flags.ac = b->flags.ac;
652 merge.flags.apf = b->flags.apf;
653 merge.flags.auf = b->flags.auf;
654 }
655
656 if (b->alu.mul.op != V3D_QPU_M_NOP) {
657 if (a->alu.mul.op != V3D_QPU_M_NOP)
658 return false;
659 merge.alu.mul = b->alu.mul;
660
661 merge.flags.mc = b->flags.mc;
662 merge.flags.mpf = b->flags.mpf;
663 merge.flags.muf = b->flags.muf;
664 }
665
666 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_A)) {
667 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_A) &&
668 a->raddr_a != b->raddr_a) {
669 return false;
670 }
671 merge.raddr_a = b->raddr_a;
672 }
673
674 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_B)) {
675 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_B) &&
676 (a->raddr_b != b->raddr_b ||
677 a->sig.small_imm != b->sig.small_imm)) {
678 return false;
679 }
680 merge.raddr_b = b->raddr_b;
681 }
682
683 merge.sig.thrsw |= b->sig.thrsw;
684 merge.sig.ldunif |= b->sig.ldunif;
685 merge.sig.ldunifrf |= b->sig.ldunifrf;
686 merge.sig.ldunifa |= b->sig.ldunifa;
687 merge.sig.ldunifarf |= b->sig.ldunifarf;
688 merge.sig.ldtmu |= b->sig.ldtmu;
689 merge.sig.ldvary |= b->sig.ldvary;
690 merge.sig.ldvpm |= b->sig.ldvpm;
691 merge.sig.small_imm |= b->sig.small_imm;
692 merge.sig.ldtlb |= b->sig.ldtlb;
693 merge.sig.ldtlbu |= b->sig.ldtlbu;
694 merge.sig.ucb |= b->sig.ucb;
695 merge.sig.rotate |= b->sig.rotate;
696 merge.sig.wrtmuc |= b->sig.wrtmuc;
697
698 if (v3d_qpu_sig_writes_address(devinfo, &a->sig) &&
699 v3d_qpu_sig_writes_address(devinfo, &b->sig))
700 return false;
701 merge.sig_addr |= b->sig_addr;
702 merge.sig_magic |= b->sig_magic;
703
704 uint64_t packed;
705 bool ok = v3d_qpu_instr_pack(devinfo, &merge, &packed);
706
707 *result = merge;
708 /* No modifying the real instructions on failure. */
709 assert(ok || (a != result && b != result));
710
711 return ok;
712 }
713
714 static struct schedule_node *
715 choose_instruction_to_schedule(const struct v3d_device_info *devinfo,
716 struct choose_scoreboard *scoreboard,
717 struct list_head *schedule_list,
718 struct schedule_node *prev_inst)
719 {
720 struct schedule_node *chosen = NULL;
721 int chosen_prio = 0;
722
723 /* Don't pair up anything with a thread switch signal -- emit_thrsw()
724 * will handle pairing it along with filling the delay slots.
725 */
726 if (prev_inst) {
727 if (prev_inst->inst->qpu.sig.thrsw)
728 return NULL;
729 }
730
731 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
732 const struct v3d_qpu_instr *inst = &n->inst->qpu;
733
734 /* Don't choose the branch instruction until it's the last one
735 * left. We'll move it up to fit its delay slots after we
736 * choose it.
737 */
738 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH &&
739 !list_is_singular(schedule_list)) {
740 continue;
741 }
742
743 /* "An instruction must not read from a location in physical
744 * regfile A or B that was written to by the previous
745 * instruction."
746 */
747 if (reads_too_soon_after_write(scoreboard, n->inst))
748 continue;
749
750 if (writes_too_soon_after_write(devinfo, scoreboard, n->inst))
751 continue;
752
753 /* "A scoreboard wait must not occur in the first two
754 * instructions of a fragment shader. This is either the
755 * explicit Wait for Scoreboard signal or an implicit wait
756 * with the first tile-buffer read or write instruction."
757 */
758 if (pixel_scoreboard_too_soon(scoreboard, inst))
759 continue;
760
761 /* ldunif and ldvary both write r5, but ldunif does so a tick
762 * sooner. If the ldvary's r5 wasn't used, then ldunif might
763 * otherwise get scheduled so ldunif and ldvary try to update
764 * r5 in the same tick.
765 */
766 if ((inst->sig.ldunif || inst->sig.ldunifa) &&
767 scoreboard->tick == scoreboard->last_ldvary_tick + 1) {
768 continue;
769 }
770
771 /* If we're trying to pair with another instruction, check
772 * that they're compatible.
773 */
774 if (prev_inst) {
775 /* Don't pair up a thread switch signal -- we'll
776 * handle pairing it when we pick it on its own.
777 */
778 if (inst->sig.thrsw)
779 continue;
780
781 if (prev_inst->inst->uniform != -1 &&
782 n->inst->uniform != -1)
783 continue;
784
785 /* Don't merge in something that will lock the TLB.
786 * Hopwefully what we have in inst will release some
787 * other instructions, allowing us to delay the
788 * TLB-locking instruction until later.
789 */
790 if (!scoreboard->tlb_locked && qpu_inst_is_tlb(inst))
791 continue;
792
793 struct v3d_qpu_instr merged_inst;
794 if (!qpu_merge_inst(devinfo, &merged_inst,
795 &prev_inst->inst->qpu, inst)) {
796 continue;
797 }
798 }
799
800 int prio = get_instruction_priority(inst);
801
802 /* Found a valid instruction. If nothing better comes along,
803 * this one works.
804 */
805 if (!chosen) {
806 chosen = n;
807 chosen_prio = prio;
808 continue;
809 }
810
811 if (prio > chosen_prio) {
812 chosen = n;
813 chosen_prio = prio;
814 } else if (prio < chosen_prio) {
815 continue;
816 }
817
818 if (n->delay > chosen->delay) {
819 chosen = n;
820 chosen_prio = prio;
821 } else if (n->delay < chosen->delay) {
822 continue;
823 }
824 }
825
826 return chosen;
827 }
828
829 static void
830 update_scoreboard_for_magic_waddr(struct choose_scoreboard *scoreboard,
831 enum v3d_qpu_waddr waddr)
832 {
833 if (v3d_qpu_magic_waddr_is_sfu(waddr))
834 scoreboard->last_magic_sfu_write_tick = scoreboard->tick;
835 }
836
837 static void
838 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
839 const struct v3d_qpu_instr *inst)
840 {
841 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
842 return;
843
844 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
845
846 if (inst->alu.add.op != V3D_QPU_A_NOP) {
847 if (inst->alu.add.magic_write) {
848 update_scoreboard_for_magic_waddr(scoreboard,
849 inst->alu.add.waddr);
850 }
851 }
852
853 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
854 if (inst->alu.mul.magic_write) {
855 update_scoreboard_for_magic_waddr(scoreboard,
856 inst->alu.mul.waddr);
857 }
858 }
859
860 if (inst->sig.ldvary)
861 scoreboard->last_ldvary_tick = scoreboard->tick;
862
863 if (qpu_inst_is_tlb(inst))
864 scoreboard->tlb_locked = true;
865 }
866
867 static void
868 dump_state(const struct v3d_device_info *devinfo,
869 struct list_head *schedule_list)
870 {
871 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
872 fprintf(stderr, " t=%4d: ", n->unblocked_time);
873 v3d_qpu_dump(devinfo, &n->inst->qpu);
874 fprintf(stderr, "\n");
875
876 for (int i = 0; i < n->child_count; i++) {
877 struct schedule_node *child = n->children[i].node;
878 if (!child)
879 continue;
880
881 fprintf(stderr, " - ");
882 v3d_qpu_dump(devinfo, &child->inst->qpu);
883 fprintf(stderr, " (%d parents, %c)\n",
884 child->parent_count,
885 n->children[i].write_after_read ? 'w' : 'r');
886 }
887 }
888 }
889
890 static uint32_t magic_waddr_latency(enum v3d_qpu_waddr waddr,
891 const struct v3d_qpu_instr *after)
892 {
893 /* Apply some huge latency between texture fetch requests and getting
894 * their results back.
895 *
896 * FIXME: This is actually pretty bogus. If we do:
897 *
898 * mov tmu0_s, a
899 * <a bit of math>
900 * mov tmu0_s, b
901 * load_tmu0
902 * <more math>
903 * load_tmu0
904 *
905 * we count that as worse than
906 *
907 * mov tmu0_s, a
908 * mov tmu0_s, b
909 * <lots of math>
910 * load_tmu0
911 * <more math>
912 * load_tmu0
913 *
914 * because we associate the first load_tmu0 with the *second* tmu0_s.
915 */
916 if (v3d_qpu_magic_waddr_is_tmu(waddr) && v3d_qpu_waits_on_tmu(after))
917 return 100;
918
919 /* Assume that anything depending on us is consuming the SFU result. */
920 if (v3d_qpu_magic_waddr_is_sfu(waddr))
921 return 3;
922
923 return 1;
924 }
925
926 static uint32_t
927 instruction_latency(struct schedule_node *before, struct schedule_node *after)
928 {
929 const struct v3d_qpu_instr *before_inst = &before->inst->qpu;
930 const struct v3d_qpu_instr *after_inst = &after->inst->qpu;
931 uint32_t latency = 1;
932
933 if (before_inst->type != V3D_QPU_INSTR_TYPE_ALU ||
934 after_inst->type != V3D_QPU_INSTR_TYPE_ALU)
935 return latency;
936
937 if (before_inst->alu.add.magic_write) {
938 latency = MAX2(latency,
939 magic_waddr_latency(before_inst->alu.add.waddr,
940 after_inst));
941 }
942
943 if (before_inst->alu.mul.magic_write) {
944 latency = MAX2(latency,
945 magic_waddr_latency(before_inst->alu.mul.waddr,
946 after_inst));
947 }
948
949 return latency;
950 }
951
952 /** Recursive computation of the delay member of a node. */
953 static void
954 compute_delay(struct schedule_node *n)
955 {
956 if (!n->child_count) {
957 n->delay = 1;
958 } else {
959 for (int i = 0; i < n->child_count; i++) {
960 if (!n->children[i].node->delay)
961 compute_delay(n->children[i].node);
962 n->delay = MAX2(n->delay,
963 n->children[i].node->delay +
964 instruction_latency(n, n->children[i].node));
965 }
966 }
967 }
968
969 static void
970 mark_instruction_scheduled(struct list_head *schedule_list,
971 uint32_t time,
972 struct schedule_node *node,
973 bool war_only)
974 {
975 if (!node)
976 return;
977
978 for (int i = node->child_count - 1; i >= 0; i--) {
979 struct schedule_node *child =
980 node->children[i].node;
981
982 if (!child)
983 continue;
984
985 if (war_only && !node->children[i].write_after_read)
986 continue;
987
988 /* If the requirement is only that the node not appear before
989 * the last read of its destination, then it can be scheduled
990 * immediately after (or paired with!) the thing reading the
991 * destination.
992 */
993 uint32_t latency = 0;
994 if (!war_only) {
995 latency = instruction_latency(node,
996 node->children[i].node);
997 }
998
999 child->unblocked_time = MAX2(child->unblocked_time,
1000 time + latency);
1001 child->parent_count--;
1002 if (child->parent_count == 0)
1003 list_add(&child->link, schedule_list);
1004
1005 node->children[i].node = NULL;
1006 }
1007 }
1008
1009 static void
1010 insert_scheduled_instruction(struct v3d_compile *c,
1011 struct qblock *block,
1012 struct choose_scoreboard *scoreboard,
1013 struct qinst *inst)
1014 {
1015 list_addtail(&inst->link, &block->instructions);
1016
1017 update_scoreboard_for_chosen(scoreboard, &inst->qpu);
1018 c->qpu_inst_count++;
1019 scoreboard->tick++;
1020 }
1021
1022 static struct qinst *
1023 vir_nop()
1024 {
1025 struct qreg undef = { QFILE_NULL, 0 };
1026 struct qinst *qinst = vir_add_inst(V3D_QPU_A_NOP, undef, undef, undef);
1027
1028 return qinst;
1029 }
1030
1031 static void
1032 emit_nop(struct v3d_compile *c, struct qblock *block,
1033 struct choose_scoreboard *scoreboard)
1034 {
1035 insert_scheduled_instruction(c, block, scoreboard, vir_nop());
1036 }
1037
1038 static bool
1039 qpu_instruction_valid_in_thrend_slot(struct v3d_compile *c,
1040 const struct qinst *qinst, int slot)
1041 {
1042 const struct v3d_qpu_instr *inst = &qinst->qpu;
1043
1044 /* Only TLB Z writes are prohibited in the last slot, but we don't
1045 * have those flagged so prohibit all TLB ops for now.
1046 */
1047 if (slot == 2 && qpu_inst_is_tlb(inst))
1048 return false;
1049
1050 if (slot > 0 && qinst->uniform != ~0)
1051 return false;
1052
1053 if (v3d_qpu_uses_vpm(inst))
1054 return false;
1055
1056 if (inst->sig.ldvary)
1057 return false;
1058
1059 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
1060 /* GFXH-1625: TMUWT not allowed in the final instruction. */
1061 if (slot == 2 && inst->alu.add.op == V3D_QPU_A_TMUWT)
1062 return false;
1063
1064 /* No writing physical registers at the end. */
1065 if (!inst->alu.add.magic_write ||
1066 !inst->alu.mul.magic_write) {
1067 return false;
1068 }
1069
1070 if (c->devinfo->ver < 40 && inst->alu.add.op == V3D_QPU_A_SETMSF)
1071 return false;
1072
1073 /* RF0-2 might be overwritten during the delay slots by
1074 * fragment shader setup.
1075 */
1076 if (inst->raddr_a < 3 &&
1077 (inst->alu.add.a == V3D_QPU_MUX_A ||
1078 inst->alu.add.b == V3D_QPU_MUX_A ||
1079 inst->alu.mul.a == V3D_QPU_MUX_A ||
1080 inst->alu.mul.b == V3D_QPU_MUX_A)) {
1081 return false;
1082 }
1083
1084 if (inst->raddr_b < 3 &&
1085 !inst->sig.small_imm &&
1086 (inst->alu.add.a == V3D_QPU_MUX_B ||
1087 inst->alu.add.b == V3D_QPU_MUX_B ||
1088 inst->alu.mul.a == V3D_QPU_MUX_B ||
1089 inst->alu.mul.b == V3D_QPU_MUX_B)) {
1090 return false;
1091 }
1092 }
1093
1094 return true;
1095 }
1096
1097 static bool
1098 valid_thrsw_sequence(struct v3d_compile *c,
1099 struct qinst *qinst, int instructions_in_sequence,
1100 bool is_thrend)
1101 {
1102 for (int slot = 0; slot < instructions_in_sequence; slot++) {
1103 /* No scheduling SFU when the result would land in the other
1104 * thread. The simulator complains for safety, though it
1105 * would only occur for dead code in our case.
1106 */
1107 if (slot > 0 &&
1108 qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
1109 (v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.add.waddr) ||
1110 v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.mul.waddr))) {
1111 return false;
1112 }
1113
1114 if (slot > 0 && qinst->qpu.sig.ldvary)
1115 return false;
1116
1117 if (is_thrend &&
1118 !qpu_instruction_valid_in_thrend_slot(c, qinst, slot)) {
1119 return false;
1120 }
1121
1122 /* Note that the list is circular, so we can only do this up
1123 * to instructions_in_sequence.
1124 */
1125 qinst = (struct qinst *)qinst->link.next;
1126 }
1127
1128 return true;
1129 }
1130
1131 /**
1132 * Emits a THRSW signal in the stream, trying to move it up to pair with
1133 * another instruction.
1134 */
1135 static int
1136 emit_thrsw(struct v3d_compile *c,
1137 struct qblock *block,
1138 struct choose_scoreboard *scoreboard,
1139 struct qinst *inst,
1140 bool is_thrend)
1141 {
1142 int time = 0;
1143
1144 /* There should be nothing in a thrsw inst being scheduled other than
1145 * the signal bits.
1146 */
1147 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);
1148 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP);
1149 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP);
1150
1151 /* Find how far back into previous instructions we can put the THRSW. */
1152 int slots_filled = 0;
1153 struct qinst *merge_inst = NULL;
1154 vir_for_each_inst_rev(prev_inst, block) {
1155 struct v3d_qpu_sig sig = prev_inst->qpu.sig;
1156 sig.thrsw = true;
1157 uint32_t packed_sig;
1158
1159 if (!v3d_qpu_sig_pack(c->devinfo, &sig, &packed_sig))
1160 break;
1161
1162 if (!valid_thrsw_sequence(c, prev_inst, slots_filled + 1,
1163 is_thrend)) {
1164 break;
1165 }
1166
1167 merge_inst = prev_inst;
1168 if (++slots_filled == 3)
1169 break;
1170 }
1171
1172 bool needs_free = false;
1173 if (merge_inst) {
1174 merge_inst->qpu.sig.thrsw = true;
1175 needs_free = true;
1176 } else {
1177 insert_scheduled_instruction(c, block, scoreboard, inst);
1178 time++;
1179 slots_filled++;
1180 merge_inst = inst;
1181 }
1182
1183 /* Insert any extra delay slot NOPs we need. */
1184 for (int i = 0; i < 3 - slots_filled; i++) {
1185 emit_nop(c, block, scoreboard);
1186 time++;
1187 }
1188
1189 /* If we're emitting the last THRSW (other than program end), then
1190 * signal that to the HW by emitting two THRSWs in a row.
1191 */
1192 if (inst->is_last_thrsw) {
1193 struct qinst *second_inst =
1194 (struct qinst *)merge_inst->link.next;
1195 second_inst->qpu.sig.thrsw = true;
1196 }
1197
1198 /* If we put our THRSW into another instruction, free up the
1199 * instruction that didn't end up scheduled into the list.
1200 */
1201 if (needs_free)
1202 free(inst);
1203
1204 return time;
1205 }
1206
1207 static uint32_t
1208 schedule_instructions(struct v3d_compile *c,
1209 struct choose_scoreboard *scoreboard,
1210 struct qblock *block,
1211 struct list_head *schedule_list,
1212 enum quniform_contents *orig_uniform_contents,
1213 uint32_t *orig_uniform_data,
1214 uint32_t *next_uniform)
1215 {
1216 const struct v3d_device_info *devinfo = c->devinfo;
1217 uint32_t time = 0;
1218
1219 if (debug) {
1220 fprintf(stderr, "initial deps:\n");
1221 dump_state(devinfo, schedule_list);
1222 fprintf(stderr, "\n");
1223 }
1224
1225 /* Remove non-DAG heads from the list. */
1226 list_for_each_entry_safe(struct schedule_node, n, schedule_list, link) {
1227 if (n->parent_count != 0)
1228 list_del(&n->link);
1229 }
1230
1231 while (!list_empty(schedule_list)) {
1232 struct schedule_node *chosen =
1233 choose_instruction_to_schedule(devinfo,
1234 scoreboard,
1235 schedule_list,
1236 NULL);
1237 struct schedule_node *merge = NULL;
1238
1239 /* If there are no valid instructions to schedule, drop a NOP
1240 * in.
1241 */
1242 struct qinst *qinst = chosen ? chosen->inst : vir_nop();
1243 struct v3d_qpu_instr *inst = &qinst->qpu;
1244
1245 if (debug) {
1246 fprintf(stderr, "t=%4d: current list:\n",
1247 time);
1248 dump_state(devinfo, schedule_list);
1249 fprintf(stderr, "t=%4d: chose: ", time);
1250 v3d_qpu_dump(devinfo, inst);
1251 fprintf(stderr, "\n");
1252 }
1253
1254 /* We can't mark_instruction_scheduled() the chosen inst until
1255 * we're done identifying instructions to merge, so put the
1256 * merged instructions on a list for a moment.
1257 */
1258 struct list_head merged_list;
1259 list_inithead(&merged_list);
1260
1261 /* Schedule this instruction onto the QPU list. Also try to
1262 * find an instruction to pair with it.
1263 */
1264 if (chosen) {
1265 time = MAX2(chosen->unblocked_time, time);
1266 list_del(&chosen->link);
1267 mark_instruction_scheduled(schedule_list, time,
1268 chosen, true);
1269
1270 while ((merge =
1271 choose_instruction_to_schedule(devinfo,
1272 scoreboard,
1273 schedule_list,
1274 chosen))) {
1275 time = MAX2(merge->unblocked_time, time);
1276 list_del(&merge->link);
1277 list_addtail(&merge->link, &merged_list);
1278 (void)qpu_merge_inst(devinfo, inst,
1279 inst, &merge->inst->qpu);
1280 if (merge->inst->uniform != -1) {
1281 chosen->inst->uniform =
1282 merge->inst->uniform;
1283 }
1284
1285 if (debug) {
1286 fprintf(stderr, "t=%4d: merging: ",
1287 time);
1288 v3d_qpu_dump(devinfo, &merge->inst->qpu);
1289 fprintf(stderr, "\n");
1290 fprintf(stderr, " result: ");
1291 v3d_qpu_dump(devinfo, inst);
1292 fprintf(stderr, "\n");
1293 }
1294 }
1295 }
1296
1297 /* Update the uniform index for the rewritten location --
1298 * branch target updating will still need to change
1299 * c->uniform_data[] using this index.
1300 */
1301 if (qinst->uniform != -1) {
1302 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
1303 block->branch_uniform = *next_uniform;
1304
1305 c->uniform_data[*next_uniform] =
1306 orig_uniform_data[qinst->uniform];
1307 c->uniform_contents[*next_uniform] =
1308 orig_uniform_contents[qinst->uniform];
1309 qinst->uniform = *next_uniform;
1310 (*next_uniform)++;
1311 }
1312
1313 if (debug) {
1314 fprintf(stderr, "\n");
1315 }
1316
1317 /* Now that we've scheduled a new instruction, some of its
1318 * children can be promoted to the list of instructions ready to
1319 * be scheduled. Update the children's unblocked time for this
1320 * DAG edge as we do so.
1321 */
1322 mark_instruction_scheduled(schedule_list, time, chosen, false);
1323 list_for_each_entry(struct schedule_node, merge, &merged_list,
1324 link) {
1325 mark_instruction_scheduled(schedule_list, time, merge,
1326 false);
1327
1328 /* The merged VIR instruction doesn't get re-added to the
1329 * block, so free it now.
1330 */
1331 free(merge->inst);
1332 }
1333
1334 if (inst->sig.thrsw) {
1335 time += emit_thrsw(c, block, scoreboard, qinst, false);
1336 } else {
1337 insert_scheduled_instruction(c, block,
1338 scoreboard, qinst);
1339
1340 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
1341 block->branch_qpu_ip = c->qpu_inst_count - 1;
1342 /* Fill the delay slots.
1343 *
1344 * We should fill these with actual instructions,
1345 * instead, but that will probably need to be done
1346 * after this, once we know what the leading
1347 * instructions of the successors are (so we can
1348 * handle A/B register file write latency)
1349 */
1350 for (int i = 0; i < 3; i++)
1351 emit_nop(c, block, scoreboard);
1352 }
1353 }
1354 }
1355
1356 return time;
1357 }
1358
1359 static uint32_t
1360 qpu_schedule_instructions_block(struct v3d_compile *c,
1361 struct choose_scoreboard *scoreboard,
1362 struct qblock *block,
1363 enum quniform_contents *orig_uniform_contents,
1364 uint32_t *orig_uniform_data,
1365 uint32_t *next_uniform)
1366 {
1367 void *mem_ctx = ralloc_context(NULL);
1368 struct list_head schedule_list;
1369
1370 list_inithead(&schedule_list);
1371
1372 /* Wrap each instruction in a scheduler structure. */
1373 while (!list_empty(&block->instructions)) {
1374 struct qinst *qinst = (struct qinst *)block->instructions.next;
1375 struct schedule_node *n =
1376 rzalloc(mem_ctx, struct schedule_node);
1377
1378 n->inst = qinst;
1379
1380 list_del(&qinst->link);
1381 list_addtail(&n->link, &schedule_list);
1382 }
1383
1384 calculate_forward_deps(c, &schedule_list);
1385 calculate_reverse_deps(c, &schedule_list);
1386
1387 list_for_each_entry(struct schedule_node, n, &schedule_list, link) {
1388 compute_delay(n);
1389 }
1390
1391 uint32_t cycles = schedule_instructions(c, scoreboard, block,
1392 &schedule_list,
1393 orig_uniform_contents,
1394 orig_uniform_data,
1395 next_uniform);
1396
1397 ralloc_free(mem_ctx);
1398
1399 return cycles;
1400 }
1401
1402 static void
1403 qpu_set_branch_targets(struct v3d_compile *c)
1404 {
1405 vir_for_each_block(block, c) {
1406 /* The end block of the program has no branch. */
1407 if (!block->successors[0])
1408 continue;
1409
1410 /* If there was no branch instruction, then the successor
1411 * block must follow immediately after this one.
1412 */
1413 if (block->branch_qpu_ip == ~0) {
1414 assert(block->end_qpu_ip + 1 ==
1415 block->successors[0]->start_qpu_ip);
1416 continue;
1417 }
1418
1419 /* Walk back through the delay slots to find the branch
1420 * instr.
1421 */
1422 struct list_head *entry = block->instructions.prev;
1423 for (int i = 0; i < 3; i++)
1424 entry = entry->prev;
1425 struct qinst *branch = container_of(entry, branch, link);
1426 assert(branch->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH);
1427
1428 /* Make sure that the if-we-don't-jump
1429 * successor was scheduled just after the
1430 * delay slots.
1431 */
1432 assert(!block->successors[1] ||
1433 block->successors[1]->start_qpu_ip ==
1434 block->branch_qpu_ip + 4);
1435
1436 branch->qpu.branch.offset =
1437 ((block->successors[0]->start_qpu_ip -
1438 (block->branch_qpu_ip + 4)) *
1439 sizeof(uint64_t));
1440
1441 /* Set up the relative offset to jump in the
1442 * uniform stream.
1443 *
1444 * Use a temporary here, because
1445 * uniform_data[inst->uniform] may be shared
1446 * between multiple instructions.
1447 */
1448 assert(c->uniform_contents[branch->uniform] == QUNIFORM_CONSTANT);
1449 c->uniform_data[branch->uniform] =
1450 (block->successors[0]->start_uniform -
1451 (block->branch_uniform + 1)) * 4;
1452 }
1453 }
1454
1455 uint32_t
1456 v3d_qpu_schedule_instructions(struct v3d_compile *c)
1457 {
1458 const struct v3d_device_info *devinfo = c->devinfo;
1459 struct qblock *end_block = list_last_entry(&c->blocks,
1460 struct qblock, link);
1461
1462 /* We reorder the uniforms as we schedule instructions, so save the
1463 * old data off and replace it.
1464 */
1465 uint32_t *uniform_data = c->uniform_data;
1466 enum quniform_contents *uniform_contents = c->uniform_contents;
1467 c->uniform_contents = ralloc_array(c, enum quniform_contents,
1468 c->num_uniforms);
1469 c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
1470 c->uniform_array_size = c->num_uniforms;
1471 uint32_t next_uniform = 0;
1472
1473 struct choose_scoreboard scoreboard;
1474 memset(&scoreboard, 0, sizeof(scoreboard));
1475 scoreboard.last_ldvary_tick = -10;
1476 scoreboard.last_magic_sfu_write_tick = -10;
1477 scoreboard.last_uniforms_reset_tick = -10;
1478
1479 if (debug) {
1480 fprintf(stderr, "Pre-schedule instructions\n");
1481 vir_for_each_block(block, c) {
1482 fprintf(stderr, "BLOCK %d\n", block->index);
1483 list_for_each_entry(struct qinst, qinst,
1484 &block->instructions, link) {
1485 v3d_qpu_dump(devinfo, &qinst->qpu);
1486 fprintf(stderr, "\n");
1487 }
1488 }
1489 fprintf(stderr, "\n");
1490 }
1491
1492 uint32_t cycles = 0;
1493 vir_for_each_block(block, c) {
1494 block->start_qpu_ip = c->qpu_inst_count;
1495 block->branch_qpu_ip = ~0;
1496 block->start_uniform = next_uniform;
1497
1498 cycles += qpu_schedule_instructions_block(c,
1499 &scoreboard,
1500 block,
1501 uniform_contents,
1502 uniform_data,
1503 &next_uniform);
1504
1505 block->end_qpu_ip = c->qpu_inst_count - 1;
1506 }
1507
1508 /* Emit the program-end THRSW instruction. */;
1509 struct qinst *thrsw = vir_nop();
1510 thrsw->qpu.sig.thrsw = true;
1511 emit_thrsw(c, end_block, &scoreboard, thrsw, true);
1512
1513 qpu_set_branch_targets(c);
1514
1515 assert(next_uniform == c->num_uniforms);
1516
1517 return cycles;
1518 }