2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2017 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
37 #include "qpu/qpu_disasm.h"
38 #include "v3d_compiler.h"
39 #include "util/ralloc.h"
44 struct schedule_node_child
;
46 struct schedule_node
{
48 struct list_head link
;
51 /* Longest cycles + instruction_latency() of any parent of this node. */
52 uint32_t unblocked_time
;
55 * Minimum number of cycles from scheduling this instruction until the
56 * end of the program, based on the slowest dependency chain through
62 * cycles between this instruction being scheduled and when its result
68 /* When walking the instructions in reverse, we need to swap before/after in
71 enum direction
{ F
, R
};
73 struct schedule_state
{
74 const struct v3d_device_info
*devinfo
;
76 struct schedule_node
*last_r
[6];
77 struct schedule_node
*last_rf
[64];
78 struct schedule_node
*last_sf
;
79 struct schedule_node
*last_vpm_read
;
80 struct schedule_node
*last_tmu_write
;
81 struct schedule_node
*last_tmu_config
;
82 struct schedule_node
*last_tlb
;
83 struct schedule_node
*last_vpm
;
84 struct schedule_node
*last_unif
;
85 struct schedule_node
*last_rtop
;
87 /* Estimated cycle when the current instruction would start. */
92 add_dep(struct schedule_state
*state
,
93 struct schedule_node
*before
,
94 struct schedule_node
*after
,
97 bool write_after_read
= !write
&& state
->dir
== R
;
98 void *edge_data
= (void *)(uintptr_t)write_after_read
;
100 if (!before
|| !after
)
103 assert(before
!= after
);
106 dag_add_edge(&before
->dag
, &after
->dag
, edge_data
);
108 dag_add_edge(&after
->dag
, &before
->dag
, edge_data
);
112 add_read_dep(struct schedule_state
*state
,
113 struct schedule_node
*before
,
114 struct schedule_node
*after
)
116 add_dep(state
, before
, after
, false);
120 add_write_dep(struct schedule_state
*state
,
121 struct schedule_node
**before
,
122 struct schedule_node
*after
)
124 add_dep(state
, *before
, after
, true);
129 qpu_inst_is_tlb(const struct v3d_qpu_instr
*inst
)
131 if (inst
->sig
.ldtlb
|| inst
->sig
.ldtlbu
)
134 if (inst
->type
!= V3D_QPU_INSTR_TYPE_ALU
)
137 if (inst
->alu
.add
.magic_write
&&
138 (inst
->alu
.add
.waddr
== V3D_QPU_WADDR_TLB
||
139 inst
->alu
.add
.waddr
== V3D_QPU_WADDR_TLBU
))
142 if (inst
->alu
.mul
.magic_write
&&
143 (inst
->alu
.mul
.waddr
== V3D_QPU_WADDR_TLB
||
144 inst
->alu
.mul
.waddr
== V3D_QPU_WADDR_TLBU
))
151 process_mux_deps(struct schedule_state
*state
, struct schedule_node
*n
,
152 enum v3d_qpu_mux mux
)
156 add_read_dep(state
, state
->last_rf
[n
->inst
->qpu
.raddr_a
], n
);
159 if (!n
->inst
->qpu
.sig
.small_imm
) {
161 state
->last_rf
[n
->inst
->qpu
.raddr_b
], n
);
165 add_read_dep(state
, state
->last_r
[mux
- V3D_QPU_MUX_R0
], n
);
172 process_waddr_deps(struct schedule_state
*state
, struct schedule_node
*n
,
173 uint32_t waddr
, bool magic
)
176 add_write_dep(state
, &state
->last_rf
[waddr
], n
);
177 } else if (v3d_qpu_magic_waddr_is_tmu(waddr
)) {
178 /* XXX perf: For V3D 4.x, we could reorder TMU writes other
179 * than the TMUS/TMUD/TMUA to improve scheduling flexibility.
181 add_write_dep(state
, &state
->last_tmu_write
, n
);
183 case V3D_QPU_WADDR_TMUS
:
184 case V3D_QPU_WADDR_TMUSCM
:
185 case V3D_QPU_WADDR_TMUSF
:
186 case V3D_QPU_WADDR_TMUSLOD
:
187 add_write_dep(state
, &state
->last_tmu_config
, n
);
192 } else if (v3d_qpu_magic_waddr_is_sfu(waddr
)) {
193 /* Handled by v3d_qpu_writes_r4() check. */
196 case V3D_QPU_WADDR_R0
:
197 case V3D_QPU_WADDR_R1
:
198 case V3D_QPU_WADDR_R2
:
200 &state
->last_r
[waddr
- V3D_QPU_WADDR_R0
],
203 case V3D_QPU_WADDR_R3
:
204 case V3D_QPU_WADDR_R4
:
205 case V3D_QPU_WADDR_R5
:
206 /* Handled by v3d_qpu_writes_r*() checks below. */
209 case V3D_QPU_WADDR_VPM
:
210 case V3D_QPU_WADDR_VPMU
:
211 add_write_dep(state
, &state
->last_vpm
, n
);
214 case V3D_QPU_WADDR_TLB
:
215 case V3D_QPU_WADDR_TLBU
:
216 add_write_dep(state
, &state
->last_tlb
, n
);
219 case V3D_QPU_WADDR_SYNC
:
220 case V3D_QPU_WADDR_SYNCB
:
221 case V3D_QPU_WADDR_SYNCU
:
222 /* For CS barrier(): Sync against any other memory
223 * accesses. There doesn't appear to be any need for
224 * barriers to affect ALU operations.
226 add_write_dep(state
, &state
->last_tmu_write
, n
);
229 case V3D_QPU_WADDR_NOP
:
233 fprintf(stderr
, "Unknown waddr %d\n", waddr
);
240 * Common code for dependencies that need to be tracked both forward and
243 * This is for things like "all reads of r4 have to happen between the r4
244 * writes that surround them".
247 calculate_deps(struct schedule_state
*state
, struct schedule_node
*n
)
249 const struct v3d_device_info
*devinfo
= state
->devinfo
;
250 struct qinst
*qinst
= n
->inst
;
251 struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
252 /* If the input and output segments are shared, then all VPM reads to
253 * a location need to happen before all writes. We handle this by
254 * serializing all VPM operations for now.
256 bool separate_vpm_segment
= false;
258 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
) {
259 if (inst
->branch
.cond
!= V3D_QPU_BRANCH_COND_ALWAYS
)
260 add_read_dep(state
, state
->last_sf
, n
);
267 add_write_dep(state
, &state
->last_unif
, n
);
271 assert(inst
->type
== V3D_QPU_INSTR_TYPE_ALU
);
275 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 0)
276 process_mux_deps(state
, n
, inst
->alu
.add
.a
);
277 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 1)
278 process_mux_deps(state
, n
, inst
->alu
.add
.b
);
280 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 0)
281 process_mux_deps(state
, n
, inst
->alu
.mul
.a
);
282 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 1)
283 process_mux_deps(state
, n
, inst
->alu
.mul
.b
);
285 switch (inst
->alu
.add
.op
) {
286 case V3D_QPU_A_VPMSETUP
:
287 /* Could distinguish read/write by unpacking the uniform. */
288 add_write_dep(state
, &state
->last_vpm
, n
);
289 add_write_dep(state
, &state
->last_vpm_read
, n
);
292 case V3D_QPU_A_STVPMV
:
293 case V3D_QPU_A_STVPMD
:
294 case V3D_QPU_A_STVPMP
:
295 add_write_dep(state
, &state
->last_vpm
, n
);
298 case V3D_QPU_A_LDVPMV_IN
:
299 case V3D_QPU_A_LDVPMD_IN
:
300 case V3D_QPU_A_LDVPMG_IN
:
301 case V3D_QPU_A_LDVPMP
:
302 if (!separate_vpm_segment
)
303 add_write_dep(state
, &state
->last_vpm
, n
);
306 case V3D_QPU_A_VPMWT
:
307 add_read_dep(state
, state
->last_vpm
, n
);
311 add_read_dep(state
, state
->last_tlb
, n
);
314 case V3D_QPU_A_SETMSF
:
315 case V3D_QPU_A_SETREVF
:
316 add_write_dep(state
, &state
->last_tlb
, n
);
323 switch (inst
->alu
.mul
.op
) {
324 case V3D_QPU_M_MULTOP
:
325 case V3D_QPU_M_UMUL24
:
326 /* MULTOP sets rtop, and UMUL24 implicitly reads rtop and
327 * resets it to 0. We could possibly reorder umul24s relative
328 * to each other, but for now just keep all the MUL parts in
331 add_write_dep(state
, &state
->last_rtop
, n
);
337 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
338 process_waddr_deps(state
, n
, inst
->alu
.add
.waddr
,
339 inst
->alu
.add
.magic_write
);
341 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
342 process_waddr_deps(state
, n
, inst
->alu
.mul
.waddr
,
343 inst
->alu
.mul
.magic_write
);
345 if (v3d_qpu_sig_writes_address(devinfo
, &inst
->sig
)) {
346 process_waddr_deps(state
, n
, inst
->sig_addr
,
350 if (v3d_qpu_writes_r3(devinfo
, inst
))
351 add_write_dep(state
, &state
->last_r
[3], n
);
352 if (v3d_qpu_writes_r4(devinfo
, inst
))
353 add_write_dep(state
, &state
->last_r
[4], n
);
354 if (v3d_qpu_writes_r5(devinfo
, inst
))
355 add_write_dep(state
, &state
->last_r
[5], n
);
357 if (inst
->sig
.thrsw
) {
358 /* All accumulator contents and flags are undefined after the
361 for (int i
= 0; i
< ARRAY_SIZE(state
->last_r
); i
++)
362 add_write_dep(state
, &state
->last_r
[i
], n
);
363 add_write_dep(state
, &state
->last_sf
, n
);
364 add_write_dep(state
, &state
->last_rtop
, n
);
366 /* Scoreboard-locking operations have to stay after the last
369 add_write_dep(state
, &state
->last_tlb
, n
);
371 add_write_dep(state
, &state
->last_tmu_write
, n
);
372 add_write_dep(state
, &state
->last_tmu_config
, n
);
375 if (v3d_qpu_waits_on_tmu(inst
)) {
376 /* TMU loads are coming from a FIFO, so ordering is important.
378 add_write_dep(state
, &state
->last_tmu_write
, n
);
381 if (inst
->sig
.wrtmuc
)
382 add_write_dep(state
, &state
->last_tmu_config
, n
);
384 if (inst
->sig
.ldtlb
| inst
->sig
.ldtlbu
)
385 add_write_dep(state
, &state
->last_tlb
, n
);
387 if (inst
->sig
.ldvpm
) {
388 add_write_dep(state
, &state
->last_vpm_read
, n
);
390 /* At least for now, we're doing shared I/O segments, so queue
391 * all writes after all reads.
393 if (!separate_vpm_segment
)
394 add_write_dep(state
, &state
->last_vpm
, n
);
397 /* inst->sig.ldunif or sideband uniform read */
398 if (vir_has_uniform(qinst
))
399 add_write_dep(state
, &state
->last_unif
, n
);
401 if (v3d_qpu_reads_flags(inst
))
402 add_read_dep(state
, state
->last_sf
, n
);
403 if (v3d_qpu_writes_flags(inst
))
404 add_write_dep(state
, &state
->last_sf
, n
);
408 calculate_forward_deps(struct v3d_compile
*c
, struct dag
*dag
,
409 struct list_head
*schedule_list
)
411 struct schedule_state state
;
413 memset(&state
, 0, sizeof(state
));
415 state
.devinfo
= c
->devinfo
;
418 list_for_each_entry(struct schedule_node
, node
, schedule_list
, link
)
419 calculate_deps(&state
, node
);
423 calculate_reverse_deps(struct v3d_compile
*c
, struct dag
*dag
,
424 struct list_head
*schedule_list
)
426 struct schedule_state state
;
428 memset(&state
, 0, sizeof(state
));
430 state
.devinfo
= c
->devinfo
;
433 list_for_each_entry_rev(struct schedule_node
, node
, schedule_list
,
435 calculate_deps(&state
, (struct schedule_node
*)node
);
439 struct choose_scoreboard
{
442 int last_magic_sfu_write_tick
;
443 int last_stallable_sfu_reg
;
444 int last_stallable_sfu_tick
;
445 int last_ldvary_tick
;
446 int last_uniforms_reset_tick
;
452 mux_reads_too_soon(struct choose_scoreboard
*scoreboard
,
453 const struct v3d_qpu_instr
*inst
, enum v3d_qpu_mux mux
)
457 if (scoreboard
->tick
- scoreboard
->last_magic_sfu_write_tick
<= 2)
462 if (scoreboard
->tick
- scoreboard
->last_ldvary_tick
<= 1)
473 reads_too_soon_after_write(struct choose_scoreboard
*scoreboard
,
476 const struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
478 /* XXX: Branching off of raddr. */
479 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
)
482 assert(inst
->type
== V3D_QPU_INSTR_TYPE_ALU
);
484 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
485 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 0 &&
486 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.add
.a
)) {
489 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 1 &&
490 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.add
.b
)) {
495 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
496 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 0 &&
497 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.mul
.a
)) {
500 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 1 &&
501 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.mul
.b
)) {
512 writes_too_soon_after_write(const struct v3d_device_info
*devinfo
,
513 struct choose_scoreboard
*scoreboard
,
516 const struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
518 /* Don't schedule any other r4 write too soon after an SFU write.
519 * This would normally be prevented by dependency tracking, but might
520 * occur if a dead SFU computation makes it to scheduling.
522 if (scoreboard
->tick
- scoreboard
->last_magic_sfu_write_tick
< 2 &&
523 v3d_qpu_writes_r4(devinfo
, inst
))
530 pixel_scoreboard_too_soon(struct choose_scoreboard
*scoreboard
,
531 const struct v3d_qpu_instr
*inst
)
533 return (scoreboard
->tick
== 0 && qpu_inst_is_tlb(inst
));
537 qpu_instruction_uses_rf(const struct v3d_qpu_instr
*inst
,
540 if (inst
->type
!= V3D_QPU_INSTR_TYPE_ALU
)
543 if (v3d_qpu_uses_mux(inst
, V3D_QPU_MUX_A
) &&
544 inst
->raddr_a
== waddr
)
547 if (v3d_qpu_uses_mux(inst
, V3D_QPU_MUX_B
) &&
548 !inst
->sig
.small_imm
&& (inst
->raddr_b
== waddr
))
555 mux_read_stalls(struct choose_scoreboard
*scoreboard
,
556 const struct v3d_qpu_instr
*inst
)
558 return scoreboard
->tick
== scoreboard
->last_stallable_sfu_tick
+ 1 &&
559 qpu_instruction_uses_rf(inst
,
560 scoreboard
->last_stallable_sfu_reg
);
564 get_instruction_priority(const struct v3d_qpu_instr
*inst
)
566 uint32_t baseline_score
;
567 uint32_t next_score
= 0;
569 /* Schedule TLB operations as late as possible, to get more
570 * parallelism between shaders.
572 if (qpu_inst_is_tlb(inst
))
576 /* Schedule texture read results collection late to hide latency. */
577 if (v3d_qpu_waits_on_tmu(inst
))
581 /* XXX perf: We should schedule SFU ALU ops so that the reader is 2
582 * instructions after the producer if possible, not just 1.
585 /* Default score for things that aren't otherwise special. */
586 baseline_score
= next_score
;
589 /* Schedule texture read setup early to hide their latency better. */
590 if (v3d_qpu_writes_tmu(inst
))
594 return baseline_score
;
598 qpu_magic_waddr_is_periph(enum v3d_qpu_waddr waddr
)
600 return (v3d_qpu_magic_waddr_is_tmu(waddr
) ||
601 v3d_qpu_magic_waddr_is_sfu(waddr
) ||
602 v3d_qpu_magic_waddr_is_tlb(waddr
) ||
603 v3d_qpu_magic_waddr_is_vpm(waddr
) ||
604 v3d_qpu_magic_waddr_is_tsy(waddr
));
608 qpu_accesses_peripheral(const struct v3d_qpu_instr
*inst
)
610 if (v3d_qpu_uses_vpm(inst
))
612 if (v3d_qpu_uses_sfu(inst
))
615 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
616 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
&&
617 inst
->alu
.add
.magic_write
&&
618 qpu_magic_waddr_is_periph(inst
->alu
.add
.waddr
)) {
622 if (inst
->alu
.add
.op
== V3D_QPU_A_TMUWT
)
625 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
&&
626 inst
->alu
.mul
.magic_write
&&
627 qpu_magic_waddr_is_periph(inst
->alu
.mul
.waddr
)) {
632 return (inst
->sig
.ldvpm
||
640 qpu_compatible_peripheral_access(const struct v3d_device_info
*devinfo
,
641 const struct v3d_qpu_instr
*a
,
642 const struct v3d_qpu_instr
*b
)
644 const bool a_uses_peripheral
= qpu_accesses_peripheral(a
);
645 const bool b_uses_peripheral
= qpu_accesses_peripheral(b
);
647 /* We can always do one peripheral access per instruction. */
648 if (!a_uses_peripheral
|| !b_uses_peripheral
)
651 if (devinfo
->ver
< 41)
654 /* V3D 4.1 and later allow TMU read along with a VPM read or write, and
655 * WRTMUC with a TMU magic register write (other than tmuc).
657 if ((a
->sig
.ldtmu
&& v3d_qpu_uses_vpm(b
)) ||
658 (b
->sig
.ldtmu
&& v3d_qpu_uses_vpm(a
))) {
662 if ((a
->sig
.wrtmuc
&& v3d_qpu_writes_tmu_not_tmuc(b
)) ||
663 (b
->sig
.wrtmuc
&& v3d_qpu_writes_tmu_not_tmuc(a
))) {
671 qpu_merge_inst(const struct v3d_device_info
*devinfo
,
672 struct v3d_qpu_instr
*result
,
673 const struct v3d_qpu_instr
*a
,
674 const struct v3d_qpu_instr
*b
)
676 if (a
->type
!= V3D_QPU_INSTR_TYPE_ALU
||
677 b
->type
!= V3D_QPU_INSTR_TYPE_ALU
) {
681 if (!qpu_compatible_peripheral_access(devinfo
, a
, b
))
684 struct v3d_qpu_instr merge
= *a
;
686 if (b
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
687 if (a
->alu
.add
.op
!= V3D_QPU_A_NOP
)
689 merge
.alu
.add
= b
->alu
.add
;
691 merge
.flags
.ac
= b
->flags
.ac
;
692 merge
.flags
.apf
= b
->flags
.apf
;
693 merge
.flags
.auf
= b
->flags
.auf
;
696 if (b
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
697 if (a
->alu
.mul
.op
!= V3D_QPU_M_NOP
)
699 merge
.alu
.mul
= b
->alu
.mul
;
701 merge
.flags
.mc
= b
->flags
.mc
;
702 merge
.flags
.mpf
= b
->flags
.mpf
;
703 merge
.flags
.muf
= b
->flags
.muf
;
706 if (v3d_qpu_uses_mux(b
, V3D_QPU_MUX_A
)) {
707 if (v3d_qpu_uses_mux(a
, V3D_QPU_MUX_A
) &&
708 a
->raddr_a
!= b
->raddr_a
) {
711 merge
.raddr_a
= b
->raddr_a
;
714 if (v3d_qpu_uses_mux(b
, V3D_QPU_MUX_B
)) {
715 if (v3d_qpu_uses_mux(a
, V3D_QPU_MUX_B
) &&
716 (a
->raddr_b
!= b
->raddr_b
||
717 a
->sig
.small_imm
!= b
->sig
.small_imm
)) {
720 merge
.raddr_b
= b
->raddr_b
;
723 merge
.sig
.thrsw
|= b
->sig
.thrsw
;
724 merge
.sig
.ldunif
|= b
->sig
.ldunif
;
725 merge
.sig
.ldunifrf
|= b
->sig
.ldunifrf
;
726 merge
.sig
.ldunifa
|= b
->sig
.ldunifa
;
727 merge
.sig
.ldunifarf
|= b
->sig
.ldunifarf
;
728 merge
.sig
.ldtmu
|= b
->sig
.ldtmu
;
729 merge
.sig
.ldvary
|= b
->sig
.ldvary
;
730 merge
.sig
.ldvpm
|= b
->sig
.ldvpm
;
731 merge
.sig
.small_imm
|= b
->sig
.small_imm
;
732 merge
.sig
.ldtlb
|= b
->sig
.ldtlb
;
733 merge
.sig
.ldtlbu
|= b
->sig
.ldtlbu
;
734 merge
.sig
.ucb
|= b
->sig
.ucb
;
735 merge
.sig
.rotate
|= b
->sig
.rotate
;
736 merge
.sig
.wrtmuc
|= b
->sig
.wrtmuc
;
738 if (v3d_qpu_sig_writes_address(devinfo
, &a
->sig
) &&
739 v3d_qpu_sig_writes_address(devinfo
, &b
->sig
))
741 merge
.sig_addr
|= b
->sig_addr
;
742 merge
.sig_magic
|= b
->sig_magic
;
745 bool ok
= v3d_qpu_instr_pack(devinfo
, &merge
, &packed
);
748 /* No modifying the real instructions on failure. */
749 assert(ok
|| (a
!= result
&& b
!= result
));
754 static struct schedule_node
*
755 choose_instruction_to_schedule(const struct v3d_device_info
*devinfo
,
756 struct choose_scoreboard
*scoreboard
,
757 struct schedule_node
*prev_inst
)
759 struct schedule_node
*chosen
= NULL
;
762 /* Don't pair up anything with a thread switch signal -- emit_thrsw()
763 * will handle pairing it along with filling the delay slots.
766 if (prev_inst
->inst
->qpu
.sig
.thrsw
)
770 list_for_each_entry(struct schedule_node
, n
, &scoreboard
->dag
->heads
,
772 const struct v3d_qpu_instr
*inst
= &n
->inst
->qpu
;
774 /* Don't choose the branch instruction until it's the last one
775 * left. We'll move it up to fit its delay slots after we
778 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
&&
779 !list_is_singular(&scoreboard
->dag
->heads
)) {
783 /* "An instruction must not read from a location in physical
784 * regfile A or B that was written to by the previous
787 if (reads_too_soon_after_write(scoreboard
, n
->inst
))
790 if (writes_too_soon_after_write(devinfo
, scoreboard
, n
->inst
))
793 /* "A scoreboard wait must not occur in the first two
794 * instructions of a fragment shader. This is either the
795 * explicit Wait for Scoreboard signal or an implicit wait
796 * with the first tile-buffer read or write instruction."
798 if (pixel_scoreboard_too_soon(scoreboard
, inst
))
801 /* ldunif and ldvary both write r5, but ldunif does so a tick
802 * sooner. If the ldvary's r5 wasn't used, then ldunif might
803 * otherwise get scheduled so ldunif and ldvary try to update
804 * r5 in the same tick.
806 * XXX perf: To get good pipelining of a sequence of varying
807 * loads, we need to figure out how to pair the ldvary signal
808 * up to the instruction before the last r5 user in the
809 * previous ldvary sequence. Currently, it usually pairs with
812 if ((inst
->sig
.ldunif
|| inst
->sig
.ldunifa
) &&
813 scoreboard
->tick
== scoreboard
->last_ldvary_tick
+ 1) {
817 /* If we're trying to pair with another instruction, check
818 * that they're compatible.
821 /* Don't pair up a thread switch signal -- we'll
822 * handle pairing it when we pick it on its own.
827 if (prev_inst
->inst
->uniform
!= -1 &&
828 n
->inst
->uniform
!= -1)
831 /* Don't merge in something that will lock the TLB.
832 * Hopwefully what we have in inst will release some
833 * other instructions, allowing us to delay the
834 * TLB-locking instruction until later.
836 if (!scoreboard
->tlb_locked
&& qpu_inst_is_tlb(inst
))
839 struct v3d_qpu_instr merged_inst
;
840 if (!qpu_merge_inst(devinfo
, &merged_inst
,
841 &prev_inst
->inst
->qpu
, inst
)) {
846 int prio
= get_instruction_priority(inst
);
848 /* Found a valid instruction. If nothing better comes along,
857 if (prio
> chosen_prio
) {
860 } else if (prio
< chosen_prio
) {
864 if (n
->delay
> chosen
->delay
) {
867 } else if (n
->delay
< chosen
->delay
) {
876 update_scoreboard_for_magic_waddr(struct choose_scoreboard
*scoreboard
,
877 enum v3d_qpu_waddr waddr
)
879 if (v3d_qpu_magic_waddr_is_sfu(waddr
))
880 scoreboard
->last_magic_sfu_write_tick
= scoreboard
->tick
;
884 update_scoreboard_for_sfu_stall_waddr(struct choose_scoreboard
*scoreboard
,
885 const struct v3d_qpu_instr
*inst
)
887 if (v3d_qpu_instr_is_sfu(inst
)) {
888 scoreboard
->last_stallable_sfu_reg
= inst
->alu
.add
.waddr
;
889 scoreboard
->last_stallable_sfu_tick
= scoreboard
->tick
;
894 update_scoreboard_for_chosen(struct choose_scoreboard
*scoreboard
,
895 const struct v3d_qpu_instr
*inst
)
897 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
)
900 assert(inst
->type
== V3D_QPU_INSTR_TYPE_ALU
);
902 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
903 if (inst
->alu
.add
.magic_write
) {
904 update_scoreboard_for_magic_waddr(scoreboard
,
905 inst
->alu
.add
.waddr
);
907 update_scoreboard_for_sfu_stall_waddr(scoreboard
,
912 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
913 if (inst
->alu
.mul
.magic_write
) {
914 update_scoreboard_for_magic_waddr(scoreboard
,
915 inst
->alu
.mul
.waddr
);
919 if (inst
->sig
.ldvary
)
920 scoreboard
->last_ldvary_tick
= scoreboard
->tick
;
922 if (qpu_inst_is_tlb(inst
))
923 scoreboard
->tlb_locked
= true;
927 dump_state(const struct v3d_device_info
*devinfo
, struct dag
*dag
)
929 list_for_each_entry(struct schedule_node
, n
, &dag
->heads
, dag
.link
) {
930 fprintf(stderr
, " t=%4d: ", n
->unblocked_time
);
931 v3d_qpu_dump(devinfo
, &n
->inst
->qpu
);
932 fprintf(stderr
, "\n");
934 util_dynarray_foreach(&n
->dag
.edges
, struct dag_edge
, edge
) {
935 struct schedule_node
*child
=
936 (struct schedule_node
*)edge
->child
;
940 fprintf(stderr
, " - ");
941 v3d_qpu_dump(devinfo
, &child
->inst
->qpu
);
942 fprintf(stderr
, " (%d parents, %c)\n",
943 child
->dag
.parent_count
,
944 edge
->data
? 'w' : 'r');
949 static uint32_t magic_waddr_latency(enum v3d_qpu_waddr waddr
,
950 const struct v3d_qpu_instr
*after
)
952 /* Apply some huge latency between texture fetch requests and getting
953 * their results back.
955 * FIXME: This is actually pretty bogus. If we do:
964 * we count that as worse than
973 * because we associate the first load_tmu0 with the *second* tmu0_s.
975 if (v3d_qpu_magic_waddr_is_tmu(waddr
) && v3d_qpu_waits_on_tmu(after
))
978 /* Assume that anything depending on us is consuming the SFU result. */
979 if (v3d_qpu_magic_waddr_is_sfu(waddr
))
986 instruction_latency(struct schedule_node
*before
, struct schedule_node
*after
)
988 const struct v3d_qpu_instr
*before_inst
= &before
->inst
->qpu
;
989 const struct v3d_qpu_instr
*after_inst
= &after
->inst
->qpu
;
990 uint32_t latency
= 1;
992 if (before_inst
->type
!= V3D_QPU_INSTR_TYPE_ALU
||
993 after_inst
->type
!= V3D_QPU_INSTR_TYPE_ALU
)
996 if (before_inst
->alu
.add
.magic_write
) {
997 latency
= MAX2(latency
,
998 magic_waddr_latency(before_inst
->alu
.add
.waddr
,
1002 if (before_inst
->alu
.mul
.magic_write
) {
1003 latency
= MAX2(latency
,
1004 magic_waddr_latency(before_inst
->alu
.mul
.waddr
,
1011 /** Recursive computation of the delay member of a node. */
1013 compute_delay(struct dag_node
*node
, void *state
)
1015 struct schedule_node
*n
= (struct schedule_node
*)node
;
1019 util_dynarray_foreach(&n
->dag
.edges
, struct dag_edge
, edge
) {
1020 struct schedule_node
*child
=
1021 (struct schedule_node
*)edge
->child
;
1023 n
->delay
= MAX2(n
->delay
, (child
->delay
+
1024 instruction_latency(n
, child
)));
1028 /* Removes a DAG head, but removing only the WAR edges. (dag_prune_head()
1029 * should be called on it later to finish pruning the other edges).
1032 pre_remove_head(struct dag
*dag
, struct schedule_node
*n
)
1034 list_delinit(&n
->dag
.link
);
1036 util_dynarray_foreach(&n
->dag
.edges
, struct dag_edge
, edge
) {
1038 dag_remove_edge(dag
, edge
);
1043 mark_instruction_scheduled(struct dag
*dag
,
1045 struct schedule_node
*node
)
1050 util_dynarray_foreach(&node
->dag
.edges
, struct dag_edge
, edge
) {
1051 struct schedule_node
*child
=
1052 (struct schedule_node
*)edge
->child
;
1057 uint32_t latency
= instruction_latency(node
, child
);
1059 child
->unblocked_time
= MAX2(child
->unblocked_time
,
1062 dag_prune_head(dag
, &node
->dag
);
1066 insert_scheduled_instruction(struct v3d_compile
*c
,
1067 struct qblock
*block
,
1068 struct choose_scoreboard
*scoreboard
,
1071 list_addtail(&inst
->link
, &block
->instructions
);
1073 update_scoreboard_for_chosen(scoreboard
, &inst
->qpu
);
1074 c
->qpu_inst_count
++;
1078 static struct qinst
*
1081 struct qreg undef
= vir_nop_reg();
1082 struct qinst
*qinst
= vir_add_inst(V3D_QPU_A_NOP
, undef
, undef
, undef
);
1088 emit_nop(struct v3d_compile
*c
, struct qblock
*block
,
1089 struct choose_scoreboard
*scoreboard
)
1091 insert_scheduled_instruction(c
, block
, scoreboard
, vir_nop());
1095 qpu_instruction_valid_in_thrend_slot(struct v3d_compile
*c
,
1096 const struct qinst
*qinst
, int slot
)
1098 const struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
1100 /* Only TLB Z writes are prohibited in the last slot, but we don't
1101 * have those flagged so prohibit all TLB ops for now.
1103 if (slot
== 2 && qpu_inst_is_tlb(inst
))
1106 if (slot
> 0 && qinst
->uniform
!= ~0)
1109 if (v3d_qpu_uses_vpm(inst
))
1112 if (inst
->sig
.ldvary
)
1115 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
1116 /* GFXH-1625: TMUWT not allowed in the final instruction. */
1117 if (slot
== 2 && inst
->alu
.add
.op
== V3D_QPU_A_TMUWT
)
1120 /* No writing physical registers at the end. */
1121 if (!inst
->alu
.add
.magic_write
||
1122 !inst
->alu
.mul
.magic_write
) {
1126 if (c
->devinfo
->ver
< 40 && inst
->alu
.add
.op
== V3D_QPU_A_SETMSF
)
1129 /* RF0-2 might be overwritten during the delay slots by
1130 * fragment shader setup.
1132 if (inst
->raddr_a
< 3 &&
1133 (inst
->alu
.add
.a
== V3D_QPU_MUX_A
||
1134 inst
->alu
.add
.b
== V3D_QPU_MUX_A
||
1135 inst
->alu
.mul
.a
== V3D_QPU_MUX_A
||
1136 inst
->alu
.mul
.b
== V3D_QPU_MUX_A
)) {
1140 if (inst
->raddr_b
< 3 &&
1141 !inst
->sig
.small_imm
&&
1142 (inst
->alu
.add
.a
== V3D_QPU_MUX_B
||
1143 inst
->alu
.add
.b
== V3D_QPU_MUX_B
||
1144 inst
->alu
.mul
.a
== V3D_QPU_MUX_B
||
1145 inst
->alu
.mul
.b
== V3D_QPU_MUX_B
)) {
1154 valid_thrsw_sequence(struct v3d_compile
*c
, struct choose_scoreboard
*scoreboard
,
1155 struct qinst
*qinst
, int instructions_in_sequence
,
1158 /* No emitting our thrsw while the previous thrsw hasn't happened yet. */
1159 if (scoreboard
->last_thrsw_tick
+ 3 >
1160 scoreboard
->tick
- instructions_in_sequence
) {
1164 for (int slot
= 0; slot
< instructions_in_sequence
; slot
++) {
1165 /* No scheduling SFU when the result would land in the other
1166 * thread. The simulator complains for safety, though it
1167 * would only occur for dead code in our case.
1170 qinst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
1171 (v3d_qpu_magic_waddr_is_sfu(qinst
->qpu
.alu
.add
.waddr
) ||
1172 v3d_qpu_magic_waddr_is_sfu(qinst
->qpu
.alu
.mul
.waddr
))) {
1176 if (slot
> 0 && qinst
->qpu
.sig
.ldvary
)
1180 !qpu_instruction_valid_in_thrend_slot(c
, qinst
, slot
)) {
1184 /* Note that the list is circular, so we can only do this up
1185 * to instructions_in_sequence.
1187 qinst
= (struct qinst
*)qinst
->link
.next
;
1194 * Emits a THRSW signal in the stream, trying to move it up to pair with
1195 * another instruction.
1198 emit_thrsw(struct v3d_compile
*c
,
1199 struct qblock
*block
,
1200 struct choose_scoreboard
*scoreboard
,
1206 /* There should be nothing in a thrsw inst being scheduled other than
1209 assert(inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
);
1210 assert(inst
->qpu
.alu
.add
.op
== V3D_QPU_A_NOP
);
1211 assert(inst
->qpu
.alu
.mul
.op
== V3D_QPU_M_NOP
);
1213 /* Find how far back into previous instructions we can put the THRSW. */
1214 int slots_filled
= 0;
1215 struct qinst
*merge_inst
= NULL
;
1216 vir_for_each_inst_rev(prev_inst
, block
) {
1217 struct v3d_qpu_sig sig
= prev_inst
->qpu
.sig
;
1219 uint32_t packed_sig
;
1221 if (!v3d_qpu_sig_pack(c
->devinfo
, &sig
, &packed_sig
))
1224 if (!valid_thrsw_sequence(c
, scoreboard
,
1225 prev_inst
, slots_filled
+ 1,
1230 merge_inst
= prev_inst
;
1231 if (++slots_filled
== 3)
1235 bool needs_free
= false;
1237 merge_inst
->qpu
.sig
.thrsw
= true;
1239 scoreboard
->last_thrsw_tick
= scoreboard
->tick
- slots_filled
;
1241 scoreboard
->last_thrsw_tick
= scoreboard
->tick
;
1242 insert_scheduled_instruction(c
, block
, scoreboard
, inst
);
1248 /* Insert any extra delay slot NOPs we need. */
1249 for (int i
= 0; i
< 3 - slots_filled
; i
++) {
1250 emit_nop(c
, block
, scoreboard
);
1254 /* If we're emitting the last THRSW (other than program end), then
1255 * signal that to the HW by emitting two THRSWs in a row.
1257 if (inst
->is_last_thrsw
) {
1258 struct qinst
*second_inst
=
1259 (struct qinst
*)merge_inst
->link
.next
;
1260 second_inst
->qpu
.sig
.thrsw
= true;
1263 /* If we put our THRSW into another instruction, free up the
1264 * instruction that didn't end up scheduled into the list.
1273 schedule_instructions(struct v3d_compile
*c
,
1274 struct choose_scoreboard
*scoreboard
,
1275 struct qblock
*block
,
1276 enum quniform_contents
*orig_uniform_contents
,
1277 uint32_t *orig_uniform_data
,
1278 uint32_t *next_uniform
)
1280 const struct v3d_device_info
*devinfo
= c
->devinfo
;
1283 while (!list_empty(&scoreboard
->dag
->heads
)) {
1284 struct schedule_node
*chosen
=
1285 choose_instruction_to_schedule(devinfo
,
1288 struct schedule_node
*merge
= NULL
;
1290 /* If there are no valid instructions to schedule, drop a NOP
1293 struct qinst
*qinst
= chosen
? chosen
->inst
: vir_nop();
1294 struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
1297 fprintf(stderr
, "t=%4d: current list:\n",
1299 dump_state(devinfo
, scoreboard
->dag
);
1300 fprintf(stderr
, "t=%4d: chose: ", time
);
1301 v3d_qpu_dump(devinfo
, inst
);
1302 fprintf(stderr
, "\n");
1305 /* We can't mark_instruction_scheduled() the chosen inst until
1306 * we're done identifying instructions to merge, so put the
1307 * merged instructions on a list for a moment.
1309 struct list_head merged_list
;
1310 list_inithead(&merged_list
);
1312 /* Schedule this instruction onto the QPU list. Also try to
1313 * find an instruction to pair with it.
1316 time
= MAX2(chosen
->unblocked_time
, time
);
1317 pre_remove_head(scoreboard
->dag
, chosen
);
1320 choose_instruction_to_schedule(devinfo
,
1323 time
= MAX2(merge
->unblocked_time
, time
);
1324 pre_remove_head(scoreboard
->dag
, chosen
);
1325 list_addtail(&merge
->link
, &merged_list
);
1326 (void)qpu_merge_inst(devinfo
, inst
,
1327 inst
, &merge
->inst
->qpu
);
1328 if (merge
->inst
->uniform
!= -1) {
1329 chosen
->inst
->uniform
=
1330 merge
->inst
->uniform
;
1334 fprintf(stderr
, "t=%4d: merging: ",
1336 v3d_qpu_dump(devinfo
, &merge
->inst
->qpu
);
1337 fprintf(stderr
, "\n");
1338 fprintf(stderr
, " result: ");
1339 v3d_qpu_dump(devinfo
, inst
);
1340 fprintf(stderr
, "\n");
1343 if (mux_read_stalls(scoreboard
, inst
))
1344 c
->qpu_inst_stalled_count
++;
1347 /* Update the uniform index for the rewritten location --
1348 * branch target updating will still need to change
1349 * c->uniform_data[] using this index.
1351 if (qinst
->uniform
!= -1) {
1352 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
)
1353 block
->branch_uniform
= *next_uniform
;
1355 c
->uniform_data
[*next_uniform
] =
1356 orig_uniform_data
[qinst
->uniform
];
1357 c
->uniform_contents
[*next_uniform
] =
1358 orig_uniform_contents
[qinst
->uniform
];
1359 qinst
->uniform
= *next_uniform
;
1364 fprintf(stderr
, "\n");
1367 /* Now that we've scheduled a new instruction, some of its
1368 * children can be promoted to the list of instructions ready to
1369 * be scheduled. Update the children's unblocked time for this
1370 * DAG edge as we do so.
1372 mark_instruction_scheduled(scoreboard
->dag
, time
, chosen
);
1373 list_for_each_entry(struct schedule_node
, merge
, &merged_list
,
1375 mark_instruction_scheduled(scoreboard
->dag
, time
, merge
);
1377 /* The merged VIR instruction doesn't get re-added to the
1378 * block, so free it now.
1383 if (inst
->sig
.thrsw
) {
1384 time
+= emit_thrsw(c
, block
, scoreboard
, qinst
, false);
1386 insert_scheduled_instruction(c
, block
,
1389 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
) {
1390 block
->branch_qpu_ip
= c
->qpu_inst_count
- 1;
1391 /* Fill the delay slots.
1393 * We should fill these with actual instructions,
1394 * instead, but that will probably need to be done
1395 * after this, once we know what the leading
1396 * instructions of the successors are (so we can
1397 * handle A/B register file write latency)
1399 for (int i
= 0; i
< 3; i
++)
1400 emit_nop(c
, block
, scoreboard
);
1409 qpu_schedule_instructions_block(struct v3d_compile
*c
,
1410 struct choose_scoreboard
*scoreboard
,
1411 struct qblock
*block
,
1412 enum quniform_contents
*orig_uniform_contents
,
1413 uint32_t *orig_uniform_data
,
1414 uint32_t *next_uniform
)
1416 void *mem_ctx
= ralloc_context(NULL
);
1417 scoreboard
->dag
= dag_create(mem_ctx
);
1418 struct list_head setup_list
;
1420 list_inithead(&setup_list
);
1422 /* Wrap each instruction in a scheduler structure. */
1423 while (!list_empty(&block
->instructions
)) {
1424 struct qinst
*qinst
= (struct qinst
*)block
->instructions
.next
;
1425 struct schedule_node
*n
=
1426 rzalloc(mem_ctx
, struct schedule_node
);
1428 dag_init_node(scoreboard
->dag
, &n
->dag
);
1431 list_del(&qinst
->link
);
1432 list_addtail(&n
->link
, &setup_list
);
1435 calculate_forward_deps(c
, scoreboard
->dag
, &setup_list
);
1436 calculate_reverse_deps(c
, scoreboard
->dag
, &setup_list
);
1438 dag_traverse_bottom_up(scoreboard
->dag
, compute_delay
, NULL
);
1440 uint32_t cycles
= schedule_instructions(c
, scoreboard
, block
,
1441 orig_uniform_contents
,
1445 ralloc_free(mem_ctx
);
1446 scoreboard
->dag
= NULL
;
1452 qpu_set_branch_targets(struct v3d_compile
*c
)
1454 vir_for_each_block(block
, c
) {
1455 /* The end block of the program has no branch. */
1456 if (!block
->successors
[0])
1459 /* If there was no branch instruction, then the successor
1460 * block must follow immediately after this one.
1462 if (block
->branch_qpu_ip
== ~0) {
1463 assert(block
->end_qpu_ip
+ 1 ==
1464 block
->successors
[0]->start_qpu_ip
);
1468 /* Walk back through the delay slots to find the branch
1471 struct list_head
*entry
= block
->instructions
.prev
;
1472 for (int i
= 0; i
< 3; i
++)
1473 entry
= entry
->prev
;
1474 struct qinst
*branch
= container_of(entry
, branch
, link
);
1475 assert(branch
->qpu
.type
== V3D_QPU_INSTR_TYPE_BRANCH
);
1477 /* Make sure that the if-we-don't-jump
1478 * successor was scheduled just after the
1481 assert(!block
->successors
[1] ||
1482 block
->successors
[1]->start_qpu_ip
==
1483 block
->branch_qpu_ip
+ 4);
1485 branch
->qpu
.branch
.offset
=
1486 ((block
->successors
[0]->start_qpu_ip
-
1487 (block
->branch_qpu_ip
+ 4)) *
1490 /* Set up the relative offset to jump in the
1493 * Use a temporary here, because
1494 * uniform_data[inst->uniform] may be shared
1495 * between multiple instructions.
1497 assert(c
->uniform_contents
[branch
->uniform
] == QUNIFORM_CONSTANT
);
1498 c
->uniform_data
[branch
->uniform
] =
1499 (block
->successors
[0]->start_uniform
-
1500 (block
->branch_uniform
+ 1)) * 4;
1505 v3d_qpu_schedule_instructions(struct v3d_compile
*c
)
1507 const struct v3d_device_info
*devinfo
= c
->devinfo
;
1508 struct qblock
*end_block
= list_last_entry(&c
->blocks
,
1509 struct qblock
, link
);
1511 /* We reorder the uniforms as we schedule instructions, so save the
1512 * old data off and replace it.
1514 uint32_t *uniform_data
= c
->uniform_data
;
1515 enum quniform_contents
*uniform_contents
= c
->uniform_contents
;
1516 c
->uniform_contents
= ralloc_array(c
, enum quniform_contents
,
1518 c
->uniform_data
= ralloc_array(c
, uint32_t, c
->num_uniforms
);
1519 c
->uniform_array_size
= c
->num_uniforms
;
1520 uint32_t next_uniform
= 0;
1522 struct choose_scoreboard scoreboard
;
1523 memset(&scoreboard
, 0, sizeof(scoreboard
));
1524 scoreboard
.last_ldvary_tick
= -10;
1525 scoreboard
.last_magic_sfu_write_tick
= -10;
1526 scoreboard
.last_uniforms_reset_tick
= -10;
1527 scoreboard
.last_thrsw_tick
= -10;
1528 scoreboard
.last_stallable_sfu_tick
= -10;
1531 fprintf(stderr
, "Pre-schedule instructions\n");
1532 vir_for_each_block(block
, c
) {
1533 fprintf(stderr
, "BLOCK %d\n", block
->index
);
1534 list_for_each_entry(struct qinst
, qinst
,
1535 &block
->instructions
, link
) {
1536 v3d_qpu_dump(devinfo
, &qinst
->qpu
);
1537 fprintf(stderr
, "\n");
1540 fprintf(stderr
, "\n");
1543 uint32_t cycles
= 0;
1544 vir_for_each_block(block
, c
) {
1545 block
->start_qpu_ip
= c
->qpu_inst_count
;
1546 block
->branch_qpu_ip
= ~0;
1547 block
->start_uniform
= next_uniform
;
1549 cycles
+= qpu_schedule_instructions_block(c
,
1556 block
->end_qpu_ip
= c
->qpu_inst_count
- 1;
1559 /* Emit the program-end THRSW instruction. */;
1560 struct qinst
*thrsw
= vir_nop();
1561 thrsw
->qpu
.sig
.thrsw
= true;
1562 emit_thrsw(c
, end_block
, &scoreboard
, thrsw
, true);
1564 qpu_set_branch_targets(c
);
1566 assert(next_uniform
== c
->num_uniforms
);