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v3d: Make sure we don't emit a thrsw before the last one finished.
[mesa.git] / src / broadcom / compiler / qpu_schedule.c
1 /*
2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2017 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 /**
26 * @file
27 *
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
32 *
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
35 */
36
37 #include "qpu/qpu_disasm.h"
38 #include "v3d_compiler.h"
39 #include "util/ralloc.h"
40
41 static bool debug;
42
43 struct schedule_node_child;
44
45 struct schedule_node {
46 struct list_head link;
47 struct qinst *inst;
48 struct schedule_node_child *children;
49 uint32_t child_count;
50 uint32_t child_array_size;
51 uint32_t parent_count;
52
53 /* Longest cycles + instruction_latency() of any parent of this node. */
54 uint32_t unblocked_time;
55
56 /**
57 * Minimum number of cycles from scheduling this instruction until the
58 * end of the program, based on the slowest dependency chain through
59 * the children.
60 */
61 uint32_t delay;
62
63 /**
64 * cycles between this instruction being scheduled and when its result
65 * can be consumed.
66 */
67 uint32_t latency;
68 };
69
70 struct schedule_node_child {
71 struct schedule_node *node;
72 bool write_after_read;
73 };
74
75 /* When walking the instructions in reverse, we need to swap before/after in
76 * add_dep().
77 */
78 enum direction { F, R };
79
80 struct schedule_state {
81 const struct v3d_device_info *devinfo;
82 struct schedule_node *last_r[6];
83 struct schedule_node *last_rf[64];
84 struct schedule_node *last_sf;
85 struct schedule_node *last_vpm_read;
86 struct schedule_node *last_tmu_write;
87 struct schedule_node *last_tmu_config;
88 struct schedule_node *last_tlb;
89 struct schedule_node *last_vpm;
90 struct schedule_node *last_unif;
91 struct schedule_node *last_rtop;
92 enum direction dir;
93 /* Estimated cycle when the current instruction would start. */
94 uint32_t time;
95 };
96
97 static void
98 add_dep(struct schedule_state *state,
99 struct schedule_node *before,
100 struct schedule_node *after,
101 bool write)
102 {
103 bool write_after_read = !write && state->dir == R;
104
105 if (!before || !after)
106 return;
107
108 assert(before != after);
109
110 if (state->dir == R) {
111 struct schedule_node *t = before;
112 before = after;
113 after = t;
114 }
115
116 for (int i = 0; i < before->child_count; i++) {
117 if (before->children[i].node == after &&
118 (before->children[i].write_after_read == write_after_read)) {
119 return;
120 }
121 }
122
123 if (before->child_array_size <= before->child_count) {
124 before->child_array_size = MAX2(before->child_array_size * 2, 16);
125 before->children = reralloc(before, before->children,
126 struct schedule_node_child,
127 before->child_array_size);
128 }
129
130 before->children[before->child_count].node = after;
131 before->children[before->child_count].write_after_read =
132 write_after_read;
133 before->child_count++;
134 after->parent_count++;
135 }
136
137 static void
138 add_read_dep(struct schedule_state *state,
139 struct schedule_node *before,
140 struct schedule_node *after)
141 {
142 add_dep(state, before, after, false);
143 }
144
145 static void
146 add_write_dep(struct schedule_state *state,
147 struct schedule_node **before,
148 struct schedule_node *after)
149 {
150 add_dep(state, *before, after, true);
151 *before = after;
152 }
153
154 static bool
155 qpu_inst_is_tlb(const struct v3d_qpu_instr *inst)
156 {
157 if (inst->type != V3D_QPU_INSTR_TYPE_ALU)
158 return false;
159
160 if (inst->alu.add.magic_write &&
161 (inst->alu.add.waddr == V3D_QPU_WADDR_TLB ||
162 inst->alu.add.waddr == V3D_QPU_WADDR_TLBU))
163 return true;
164
165 if (inst->alu.mul.magic_write &&
166 (inst->alu.mul.waddr == V3D_QPU_WADDR_TLB ||
167 inst->alu.mul.waddr == V3D_QPU_WADDR_TLBU))
168 return true;
169
170 return false;
171 }
172
173 static void
174 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
175 enum v3d_qpu_mux mux)
176 {
177 switch (mux) {
178 case V3D_QPU_MUX_A:
179 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n);
180 break;
181 case V3D_QPU_MUX_B:
182 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_b], n);
183 break;
184 default:
185 add_read_dep(state, state->last_r[mux - V3D_QPU_MUX_R0], n);
186 break;
187 }
188 }
189
190
191 static void
192 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
193 uint32_t waddr, bool magic)
194 {
195 if (!magic) {
196 add_write_dep(state, &state->last_rf[waddr], n);
197 } else if (v3d_qpu_magic_waddr_is_tmu(waddr)) {
198 add_write_dep(state, &state->last_tmu_write, n);
199 switch (waddr) {
200 case V3D_QPU_WADDR_TMUS:
201 case V3D_QPU_WADDR_TMUSCM:
202 case V3D_QPU_WADDR_TMUSF:
203 case V3D_QPU_WADDR_TMUSLOD:
204 add_write_dep(state, &state->last_tmu_config, n);
205 break;
206 default:
207 break;
208 }
209 } else if (v3d_qpu_magic_waddr_is_sfu(waddr)) {
210 /* Handled by v3d_qpu_writes_r4() check. */
211 } else {
212 switch (waddr) {
213 case V3D_QPU_WADDR_R0:
214 case V3D_QPU_WADDR_R1:
215 case V3D_QPU_WADDR_R2:
216 add_write_dep(state,
217 &state->last_r[waddr - V3D_QPU_WADDR_R0],
218 n);
219 break;
220 case V3D_QPU_WADDR_R3:
221 case V3D_QPU_WADDR_R4:
222 case V3D_QPU_WADDR_R5:
223 /* Handled by v3d_qpu_writes_r*() checks below. */
224 break;
225
226 case V3D_QPU_WADDR_VPM:
227 case V3D_QPU_WADDR_VPMU:
228 add_write_dep(state, &state->last_vpm, n);
229 break;
230
231 case V3D_QPU_WADDR_TLB:
232 case V3D_QPU_WADDR_TLBU:
233 add_write_dep(state, &state->last_tlb, n);
234 break;
235
236 case V3D_QPU_WADDR_NOP:
237 break;
238
239 default:
240 fprintf(stderr, "Unknown waddr %d\n", waddr);
241 abort();
242 }
243 }
244 }
245
246 static void
247 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
248 enum v3d_qpu_cond cond)
249 {
250 if (cond != V3D_QPU_COND_NONE)
251 add_read_dep(state, state->last_sf, n);
252 }
253
254 static void
255 process_pf_deps(struct schedule_state *state, struct schedule_node *n,
256 enum v3d_qpu_pf pf)
257 {
258 if (pf != V3D_QPU_PF_NONE)
259 add_write_dep(state, &state->last_sf, n);
260 }
261
262 static void
263 process_uf_deps(struct schedule_state *state, struct schedule_node *n,
264 enum v3d_qpu_uf uf)
265 {
266 if (uf != V3D_QPU_UF_NONE)
267 add_write_dep(state, &state->last_sf, n);
268 }
269
270 /**
271 * Common code for dependencies that need to be tracked both forward and
272 * backward.
273 *
274 * This is for things like "all reads of r4 have to happen between the r4
275 * writes that surround them".
276 */
277 static void
278 calculate_deps(struct schedule_state *state, struct schedule_node *n)
279 {
280 const struct v3d_device_info *devinfo = state->devinfo;
281 struct qinst *qinst = n->inst;
282 struct v3d_qpu_instr *inst = &qinst->qpu;
283
284 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
285 if (inst->branch.cond != V3D_QPU_BRANCH_COND_ALWAYS)
286 add_read_dep(state, state->last_sf, n);
287
288 /* XXX: BDI */
289 /* XXX: BDU */
290 /* XXX: ub */
291 /* XXX: raddr_a */
292
293 add_write_dep(state, &state->last_unif, n);
294 return;
295 }
296
297 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
298
299 /* XXX: LOAD_IMM */
300
301 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0)
302 process_mux_deps(state, n, inst->alu.add.a);
303 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1)
304 process_mux_deps(state, n, inst->alu.add.b);
305
306 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0)
307 process_mux_deps(state, n, inst->alu.mul.a);
308 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1)
309 process_mux_deps(state, n, inst->alu.mul.b);
310
311 switch (inst->alu.add.op) {
312 case V3D_QPU_A_VPMSETUP:
313 /* Could distinguish read/write by unpacking the uniform. */
314 add_write_dep(state, &state->last_vpm, n);
315 add_write_dep(state, &state->last_vpm_read, n);
316 break;
317
318 case V3D_QPU_A_STVPMV:
319 case V3D_QPU_A_STVPMD:
320 case V3D_QPU_A_STVPMP:
321 add_write_dep(state, &state->last_vpm, n);
322 break;
323
324 case V3D_QPU_A_VPMWT:
325 add_read_dep(state, state->last_vpm, n);
326 break;
327
328 case V3D_QPU_A_MSF:
329 add_read_dep(state, state->last_tlb, n);
330 break;
331
332 case V3D_QPU_A_SETMSF:
333 case V3D_QPU_A_SETREVF:
334 add_write_dep(state, &state->last_tlb, n);
335 break;
336
337 case V3D_QPU_A_FLAPUSH:
338 case V3D_QPU_A_FLBPUSH:
339 case V3D_QPU_A_VFLA:
340 case V3D_QPU_A_VFLNA:
341 case V3D_QPU_A_VFLB:
342 case V3D_QPU_A_VFLNB:
343 add_read_dep(state, state->last_sf, n);
344 break;
345
346 case V3D_QPU_A_FLPOP:
347 add_write_dep(state, &state->last_sf, n);
348 break;
349
350 default:
351 break;
352 }
353
354 switch (inst->alu.mul.op) {
355 case V3D_QPU_M_MULTOP:
356 case V3D_QPU_M_UMUL24:
357 /* MULTOP sets rtop, and UMUL24 implicitly reads rtop and
358 * resets it to 0. We could possibly reorder umul24s relative
359 * to each other, but for now just keep all the MUL parts in
360 * order.
361 */
362 add_write_dep(state, &state->last_rtop, n);
363 break;
364 default:
365 break;
366 }
367
368 if (inst->alu.add.op != V3D_QPU_A_NOP) {
369 process_waddr_deps(state, n, inst->alu.add.waddr,
370 inst->alu.add.magic_write);
371 }
372 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
373 process_waddr_deps(state, n, inst->alu.mul.waddr,
374 inst->alu.mul.magic_write);
375 }
376 if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) {
377 process_waddr_deps(state, n, inst->sig_addr,
378 inst->sig_magic);
379 }
380
381 if (v3d_qpu_writes_r3(devinfo, inst))
382 add_write_dep(state, &state->last_r[3], n);
383 if (v3d_qpu_writes_r4(devinfo, inst))
384 add_write_dep(state, &state->last_r[4], n);
385 if (v3d_qpu_writes_r5(devinfo, inst))
386 add_write_dep(state, &state->last_r[5], n);
387
388 if (inst->sig.thrsw) {
389 /* All accumulator contents and flags are undefined after the
390 * switch.
391 */
392 for (int i = 0; i < ARRAY_SIZE(state->last_r); i++)
393 add_write_dep(state, &state->last_r[i], n);
394 add_write_dep(state, &state->last_sf, n);
395
396 /* Scoreboard-locking operations have to stay after the last
397 * thread switch.
398 */
399 add_write_dep(state, &state->last_tlb, n);
400
401 add_write_dep(state, &state->last_tmu_write, n);
402 add_write_dep(state, &state->last_tmu_config, n);
403 }
404
405 if (v3d_qpu_waits_on_tmu(inst)) {
406 /* TMU loads are coming from a FIFO, so ordering is important.
407 */
408 add_write_dep(state, &state->last_tmu_write, n);
409 }
410
411 if (inst->sig.wrtmuc)
412 add_write_dep(state, &state->last_tmu_config, n);
413
414 if (inst->sig.ldtlb | inst->sig.ldtlbu)
415 add_read_dep(state, state->last_tlb, n);
416
417 if (inst->sig.ldvpm)
418 add_write_dep(state, &state->last_vpm_read, n);
419
420 /* inst->sig.ldunif or sideband uniform read */
421 if (qinst->uniform != ~0)
422 add_write_dep(state, &state->last_unif, n);
423
424 process_cond_deps(state, n, inst->flags.ac);
425 process_cond_deps(state, n, inst->flags.mc);
426 process_pf_deps(state, n, inst->flags.apf);
427 process_pf_deps(state, n, inst->flags.mpf);
428 process_uf_deps(state, n, inst->flags.auf);
429 process_uf_deps(state, n, inst->flags.muf);
430 }
431
432 static void
433 calculate_forward_deps(struct v3d_compile *c, struct list_head *schedule_list)
434 {
435 struct schedule_state state;
436
437 memset(&state, 0, sizeof(state));
438 state.devinfo = c->devinfo;
439 state.dir = F;
440
441 list_for_each_entry(struct schedule_node, node, schedule_list, link)
442 calculate_deps(&state, node);
443 }
444
445 static void
446 calculate_reverse_deps(struct v3d_compile *c, struct list_head *schedule_list)
447 {
448 struct list_head *node;
449 struct schedule_state state;
450
451 memset(&state, 0, sizeof(state));
452 state.devinfo = c->devinfo;
453 state.dir = R;
454
455 for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
456 calculate_deps(&state, (struct schedule_node *)node);
457 }
458 }
459
460 struct choose_scoreboard {
461 int tick;
462 int last_magic_sfu_write_tick;
463 int last_ldvary_tick;
464 int last_uniforms_reset_tick;
465 int last_thrsw_tick;
466 bool tlb_locked;
467 };
468
469 static bool
470 mux_reads_too_soon(struct choose_scoreboard *scoreboard,
471 const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux)
472 {
473 switch (mux) {
474 case V3D_QPU_MUX_R4:
475 if (scoreboard->tick - scoreboard->last_magic_sfu_write_tick <= 2)
476 return true;
477 break;
478
479 case V3D_QPU_MUX_R5:
480 if (scoreboard->tick - scoreboard->last_ldvary_tick <= 1)
481 return true;
482 break;
483 default:
484 break;
485 }
486
487 return false;
488 }
489
490 static bool
491 reads_too_soon_after_write(struct choose_scoreboard *scoreboard,
492 struct qinst *qinst)
493 {
494 const struct v3d_qpu_instr *inst = &qinst->qpu;
495
496 /* XXX: Branching off of raddr. */
497 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
498 return false;
499
500 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
501
502 if (inst->alu.add.op != V3D_QPU_A_NOP) {
503 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0 &&
504 mux_reads_too_soon(scoreboard, inst, inst->alu.add.a)) {
505 return true;
506 }
507 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1 &&
508 mux_reads_too_soon(scoreboard, inst, inst->alu.add.b)) {
509 return true;
510 }
511 }
512
513 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
514 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0 &&
515 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.a)) {
516 return true;
517 }
518 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1 &&
519 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.b)) {
520 return true;
521 }
522 }
523
524 /* XXX: imm */
525
526 return false;
527 }
528
529 static bool
530 writes_too_soon_after_write(const struct v3d_device_info *devinfo,
531 struct choose_scoreboard *scoreboard,
532 struct qinst *qinst)
533 {
534 const struct v3d_qpu_instr *inst = &qinst->qpu;
535
536 /* Don't schedule any other r4 write too soon after an SFU write.
537 * This would normally be prevented by dependency tracking, but might
538 * occur if a dead SFU computation makes it to scheduling.
539 */
540 if (scoreboard->tick - scoreboard->last_magic_sfu_write_tick < 2 &&
541 v3d_qpu_writes_r4(devinfo, inst))
542 return true;
543
544 return false;
545 }
546
547 static bool
548 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard,
549 const struct v3d_qpu_instr *inst)
550 {
551 return (scoreboard->tick == 0 && qpu_inst_is_tlb(inst));
552 }
553
554 static int
555 get_instruction_priority(const struct v3d_qpu_instr *inst)
556 {
557 uint32_t baseline_score;
558 uint32_t next_score = 0;
559
560 /* Schedule TLB operations as late as possible, to get more
561 * parallelism between shaders.
562 */
563 if (qpu_inst_is_tlb(inst))
564 return next_score;
565 next_score++;
566
567 /* Schedule texture read results collection late to hide latency. */
568 if (v3d_qpu_waits_on_tmu(inst))
569 return next_score;
570 next_score++;
571
572 /* Default score for things that aren't otherwise special. */
573 baseline_score = next_score;
574 next_score++;
575
576 /* Schedule texture read setup early to hide their latency better. */
577 if (v3d_qpu_writes_tmu(inst))
578 return next_score;
579 next_score++;
580
581 return baseline_score;
582 }
583
584 static bool
585 qpu_magic_waddr_is_periph(enum v3d_qpu_waddr waddr)
586 {
587 return (v3d_qpu_magic_waddr_is_tmu(waddr) ||
588 v3d_qpu_magic_waddr_is_sfu(waddr) ||
589 v3d_qpu_magic_waddr_is_tlb(waddr) ||
590 v3d_qpu_magic_waddr_is_vpm(waddr) ||
591 v3d_qpu_magic_waddr_is_tsy(waddr));
592 }
593
594 static bool
595 qpu_accesses_peripheral(const struct v3d_qpu_instr *inst)
596 {
597 if (v3d_qpu_uses_vpm(inst))
598 return true;
599 if (v3d_qpu_uses_sfu(inst))
600 return true;
601
602 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
603 if (inst->alu.add.op != V3D_QPU_A_NOP &&
604 inst->alu.add.magic_write &&
605 qpu_magic_waddr_is_periph(inst->alu.add.waddr)) {
606 return true;
607 }
608
609 if (inst->alu.add.op == V3D_QPU_A_TMUWT)
610 return true;
611
612 if (inst->alu.mul.op != V3D_QPU_M_NOP &&
613 inst->alu.mul.magic_write &&
614 qpu_magic_waddr_is_periph(inst->alu.mul.waddr)) {
615 return true;
616 }
617 }
618
619 return (inst->sig.ldvpm ||
620 inst->sig.ldtmu ||
621 inst->sig.ldtlb ||
622 inst->sig.ldtlbu ||
623 inst->sig.wrtmuc);
624 }
625
626 static bool
627 qpu_merge_inst(const struct v3d_device_info *devinfo,
628 struct v3d_qpu_instr *result,
629 const struct v3d_qpu_instr *a,
630 const struct v3d_qpu_instr *b)
631 {
632 if (a->type != V3D_QPU_INSTR_TYPE_ALU ||
633 b->type != V3D_QPU_INSTR_TYPE_ALU) {
634 return false;
635 }
636
637 /* Can't do more than one peripheral access in an instruction.
638 *
639 * XXX: V3D 4.1 allows TMU read along with a VPM read or write, and
640 * WRTMUC with a TMU magic register write (other than tmuc).
641 */
642 if (qpu_accesses_peripheral(a) && qpu_accesses_peripheral(b))
643 return false;
644
645 struct v3d_qpu_instr merge = *a;
646
647 if (b->alu.add.op != V3D_QPU_A_NOP) {
648 if (a->alu.add.op != V3D_QPU_A_NOP)
649 return false;
650 merge.alu.add = b->alu.add;
651
652 merge.flags.ac = b->flags.ac;
653 merge.flags.apf = b->flags.apf;
654 merge.flags.auf = b->flags.auf;
655 }
656
657 if (b->alu.mul.op != V3D_QPU_M_NOP) {
658 if (a->alu.mul.op != V3D_QPU_M_NOP)
659 return false;
660 merge.alu.mul = b->alu.mul;
661
662 merge.flags.mc = b->flags.mc;
663 merge.flags.mpf = b->flags.mpf;
664 merge.flags.muf = b->flags.muf;
665 }
666
667 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_A)) {
668 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_A) &&
669 a->raddr_a != b->raddr_a) {
670 return false;
671 }
672 merge.raddr_a = b->raddr_a;
673 }
674
675 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_B)) {
676 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_B) &&
677 (a->raddr_b != b->raddr_b ||
678 a->sig.small_imm != b->sig.small_imm)) {
679 return false;
680 }
681 merge.raddr_b = b->raddr_b;
682 }
683
684 merge.sig.thrsw |= b->sig.thrsw;
685 merge.sig.ldunif |= b->sig.ldunif;
686 merge.sig.ldunifrf |= b->sig.ldunifrf;
687 merge.sig.ldunifa |= b->sig.ldunifa;
688 merge.sig.ldunifarf |= b->sig.ldunifarf;
689 merge.sig.ldtmu |= b->sig.ldtmu;
690 merge.sig.ldvary |= b->sig.ldvary;
691 merge.sig.ldvpm |= b->sig.ldvpm;
692 merge.sig.small_imm |= b->sig.small_imm;
693 merge.sig.ldtlb |= b->sig.ldtlb;
694 merge.sig.ldtlbu |= b->sig.ldtlbu;
695 merge.sig.ucb |= b->sig.ucb;
696 merge.sig.rotate |= b->sig.rotate;
697 merge.sig.wrtmuc |= b->sig.wrtmuc;
698
699 if (v3d_qpu_sig_writes_address(devinfo, &a->sig) &&
700 v3d_qpu_sig_writes_address(devinfo, &b->sig))
701 return false;
702 merge.sig_addr |= b->sig_addr;
703 merge.sig_magic |= b->sig_magic;
704
705 uint64_t packed;
706 bool ok = v3d_qpu_instr_pack(devinfo, &merge, &packed);
707
708 *result = merge;
709 /* No modifying the real instructions on failure. */
710 assert(ok || (a != result && b != result));
711
712 return ok;
713 }
714
715 static struct schedule_node *
716 choose_instruction_to_schedule(const struct v3d_device_info *devinfo,
717 struct choose_scoreboard *scoreboard,
718 struct list_head *schedule_list,
719 struct schedule_node *prev_inst)
720 {
721 struct schedule_node *chosen = NULL;
722 int chosen_prio = 0;
723
724 /* Don't pair up anything with a thread switch signal -- emit_thrsw()
725 * will handle pairing it along with filling the delay slots.
726 */
727 if (prev_inst) {
728 if (prev_inst->inst->qpu.sig.thrsw)
729 return NULL;
730 }
731
732 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
733 const struct v3d_qpu_instr *inst = &n->inst->qpu;
734
735 /* Don't choose the branch instruction until it's the last one
736 * left. We'll move it up to fit its delay slots after we
737 * choose it.
738 */
739 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH &&
740 !list_is_singular(schedule_list)) {
741 continue;
742 }
743
744 /* "An instruction must not read from a location in physical
745 * regfile A or B that was written to by the previous
746 * instruction."
747 */
748 if (reads_too_soon_after_write(scoreboard, n->inst))
749 continue;
750
751 if (writes_too_soon_after_write(devinfo, scoreboard, n->inst))
752 continue;
753
754 /* "A scoreboard wait must not occur in the first two
755 * instructions of a fragment shader. This is either the
756 * explicit Wait for Scoreboard signal or an implicit wait
757 * with the first tile-buffer read or write instruction."
758 */
759 if (pixel_scoreboard_too_soon(scoreboard, inst))
760 continue;
761
762 /* ldunif and ldvary both write r5, but ldunif does so a tick
763 * sooner. If the ldvary's r5 wasn't used, then ldunif might
764 * otherwise get scheduled so ldunif and ldvary try to update
765 * r5 in the same tick.
766 */
767 if ((inst->sig.ldunif || inst->sig.ldunifa) &&
768 scoreboard->tick == scoreboard->last_ldvary_tick + 1) {
769 continue;
770 }
771
772 /* If we're trying to pair with another instruction, check
773 * that they're compatible.
774 */
775 if (prev_inst) {
776 /* Don't pair up a thread switch signal -- we'll
777 * handle pairing it when we pick it on its own.
778 */
779 if (inst->sig.thrsw)
780 continue;
781
782 if (prev_inst->inst->uniform != -1 &&
783 n->inst->uniform != -1)
784 continue;
785
786 /* Don't merge in something that will lock the TLB.
787 * Hopwefully what we have in inst will release some
788 * other instructions, allowing us to delay the
789 * TLB-locking instruction until later.
790 */
791 if (!scoreboard->tlb_locked && qpu_inst_is_tlb(inst))
792 continue;
793
794 struct v3d_qpu_instr merged_inst;
795 if (!qpu_merge_inst(devinfo, &merged_inst,
796 &prev_inst->inst->qpu, inst)) {
797 continue;
798 }
799 }
800
801 int prio = get_instruction_priority(inst);
802
803 /* Found a valid instruction. If nothing better comes along,
804 * this one works.
805 */
806 if (!chosen) {
807 chosen = n;
808 chosen_prio = prio;
809 continue;
810 }
811
812 if (prio > chosen_prio) {
813 chosen = n;
814 chosen_prio = prio;
815 } else if (prio < chosen_prio) {
816 continue;
817 }
818
819 if (n->delay > chosen->delay) {
820 chosen = n;
821 chosen_prio = prio;
822 } else if (n->delay < chosen->delay) {
823 continue;
824 }
825 }
826
827 return chosen;
828 }
829
830 static void
831 update_scoreboard_for_magic_waddr(struct choose_scoreboard *scoreboard,
832 enum v3d_qpu_waddr waddr)
833 {
834 if (v3d_qpu_magic_waddr_is_sfu(waddr))
835 scoreboard->last_magic_sfu_write_tick = scoreboard->tick;
836 }
837
838 static void
839 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
840 const struct v3d_qpu_instr *inst)
841 {
842 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
843 return;
844
845 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
846
847 if (inst->alu.add.op != V3D_QPU_A_NOP) {
848 if (inst->alu.add.magic_write) {
849 update_scoreboard_for_magic_waddr(scoreboard,
850 inst->alu.add.waddr);
851 }
852 }
853
854 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
855 if (inst->alu.mul.magic_write) {
856 update_scoreboard_for_magic_waddr(scoreboard,
857 inst->alu.mul.waddr);
858 }
859 }
860
861 if (inst->sig.ldvary)
862 scoreboard->last_ldvary_tick = scoreboard->tick;
863
864 if (qpu_inst_is_tlb(inst))
865 scoreboard->tlb_locked = true;
866 }
867
868 static void
869 dump_state(const struct v3d_device_info *devinfo,
870 struct list_head *schedule_list)
871 {
872 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
873 fprintf(stderr, " t=%4d: ", n->unblocked_time);
874 v3d_qpu_dump(devinfo, &n->inst->qpu);
875 fprintf(stderr, "\n");
876
877 for (int i = 0; i < n->child_count; i++) {
878 struct schedule_node *child = n->children[i].node;
879 if (!child)
880 continue;
881
882 fprintf(stderr, " - ");
883 v3d_qpu_dump(devinfo, &child->inst->qpu);
884 fprintf(stderr, " (%d parents, %c)\n",
885 child->parent_count,
886 n->children[i].write_after_read ? 'w' : 'r');
887 }
888 }
889 }
890
891 static uint32_t magic_waddr_latency(enum v3d_qpu_waddr waddr,
892 const struct v3d_qpu_instr *after)
893 {
894 /* Apply some huge latency between texture fetch requests and getting
895 * their results back.
896 *
897 * FIXME: This is actually pretty bogus. If we do:
898 *
899 * mov tmu0_s, a
900 * <a bit of math>
901 * mov tmu0_s, b
902 * load_tmu0
903 * <more math>
904 * load_tmu0
905 *
906 * we count that as worse than
907 *
908 * mov tmu0_s, a
909 * mov tmu0_s, b
910 * <lots of math>
911 * load_tmu0
912 * <more math>
913 * load_tmu0
914 *
915 * because we associate the first load_tmu0 with the *second* tmu0_s.
916 */
917 if (v3d_qpu_magic_waddr_is_tmu(waddr) && v3d_qpu_waits_on_tmu(after))
918 return 100;
919
920 /* Assume that anything depending on us is consuming the SFU result. */
921 if (v3d_qpu_magic_waddr_is_sfu(waddr))
922 return 3;
923
924 return 1;
925 }
926
927 static uint32_t
928 instruction_latency(struct schedule_node *before, struct schedule_node *after)
929 {
930 const struct v3d_qpu_instr *before_inst = &before->inst->qpu;
931 const struct v3d_qpu_instr *after_inst = &after->inst->qpu;
932 uint32_t latency = 1;
933
934 if (before_inst->type != V3D_QPU_INSTR_TYPE_ALU ||
935 after_inst->type != V3D_QPU_INSTR_TYPE_ALU)
936 return latency;
937
938 if (before_inst->alu.add.magic_write) {
939 latency = MAX2(latency,
940 magic_waddr_latency(before_inst->alu.add.waddr,
941 after_inst));
942 }
943
944 if (before_inst->alu.mul.magic_write) {
945 latency = MAX2(latency,
946 magic_waddr_latency(before_inst->alu.mul.waddr,
947 after_inst));
948 }
949
950 return latency;
951 }
952
953 /** Recursive computation of the delay member of a node. */
954 static void
955 compute_delay(struct schedule_node *n)
956 {
957 if (!n->child_count) {
958 n->delay = 1;
959 } else {
960 for (int i = 0; i < n->child_count; i++) {
961 if (!n->children[i].node->delay)
962 compute_delay(n->children[i].node);
963 n->delay = MAX2(n->delay,
964 n->children[i].node->delay +
965 instruction_latency(n, n->children[i].node));
966 }
967 }
968 }
969
970 static void
971 mark_instruction_scheduled(struct list_head *schedule_list,
972 uint32_t time,
973 struct schedule_node *node,
974 bool war_only)
975 {
976 if (!node)
977 return;
978
979 for (int i = node->child_count - 1; i >= 0; i--) {
980 struct schedule_node *child =
981 node->children[i].node;
982
983 if (!child)
984 continue;
985
986 if (war_only && !node->children[i].write_after_read)
987 continue;
988
989 /* If the requirement is only that the node not appear before
990 * the last read of its destination, then it can be scheduled
991 * immediately after (or paired with!) the thing reading the
992 * destination.
993 */
994 uint32_t latency = 0;
995 if (!war_only) {
996 latency = instruction_latency(node,
997 node->children[i].node);
998 }
999
1000 child->unblocked_time = MAX2(child->unblocked_time,
1001 time + latency);
1002 child->parent_count--;
1003 if (child->parent_count == 0)
1004 list_add(&child->link, schedule_list);
1005
1006 node->children[i].node = NULL;
1007 }
1008 }
1009
1010 static void
1011 insert_scheduled_instruction(struct v3d_compile *c,
1012 struct qblock *block,
1013 struct choose_scoreboard *scoreboard,
1014 struct qinst *inst)
1015 {
1016 list_addtail(&inst->link, &block->instructions);
1017
1018 update_scoreboard_for_chosen(scoreboard, &inst->qpu);
1019 c->qpu_inst_count++;
1020 scoreboard->tick++;
1021 }
1022
1023 static struct qinst *
1024 vir_nop()
1025 {
1026 struct qreg undef = { QFILE_NULL, 0 };
1027 struct qinst *qinst = vir_add_inst(V3D_QPU_A_NOP, undef, undef, undef);
1028
1029 return qinst;
1030 }
1031
1032 static void
1033 emit_nop(struct v3d_compile *c, struct qblock *block,
1034 struct choose_scoreboard *scoreboard)
1035 {
1036 insert_scheduled_instruction(c, block, scoreboard, vir_nop());
1037 }
1038
1039 static bool
1040 qpu_instruction_valid_in_thrend_slot(struct v3d_compile *c,
1041 const struct qinst *qinst, int slot)
1042 {
1043 const struct v3d_qpu_instr *inst = &qinst->qpu;
1044
1045 /* Only TLB Z writes are prohibited in the last slot, but we don't
1046 * have those flagged so prohibit all TLB ops for now.
1047 */
1048 if (slot == 2 && qpu_inst_is_tlb(inst))
1049 return false;
1050
1051 if (slot > 0 && qinst->uniform != ~0)
1052 return false;
1053
1054 if (v3d_qpu_uses_vpm(inst))
1055 return false;
1056
1057 if (inst->sig.ldvary)
1058 return false;
1059
1060 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
1061 /* GFXH-1625: TMUWT not allowed in the final instruction. */
1062 if (slot == 2 && inst->alu.add.op == V3D_QPU_A_TMUWT)
1063 return false;
1064
1065 /* No writing physical registers at the end. */
1066 if (!inst->alu.add.magic_write ||
1067 !inst->alu.mul.magic_write) {
1068 return false;
1069 }
1070
1071 if (c->devinfo->ver < 40 && inst->alu.add.op == V3D_QPU_A_SETMSF)
1072 return false;
1073
1074 /* RF0-2 might be overwritten during the delay slots by
1075 * fragment shader setup.
1076 */
1077 if (inst->raddr_a < 3 &&
1078 (inst->alu.add.a == V3D_QPU_MUX_A ||
1079 inst->alu.add.b == V3D_QPU_MUX_A ||
1080 inst->alu.mul.a == V3D_QPU_MUX_A ||
1081 inst->alu.mul.b == V3D_QPU_MUX_A)) {
1082 return false;
1083 }
1084
1085 if (inst->raddr_b < 3 &&
1086 !inst->sig.small_imm &&
1087 (inst->alu.add.a == V3D_QPU_MUX_B ||
1088 inst->alu.add.b == V3D_QPU_MUX_B ||
1089 inst->alu.mul.a == V3D_QPU_MUX_B ||
1090 inst->alu.mul.b == V3D_QPU_MUX_B)) {
1091 return false;
1092 }
1093 }
1094
1095 return true;
1096 }
1097
1098 static bool
1099 valid_thrsw_sequence(struct v3d_compile *c, struct choose_scoreboard *scoreboard,
1100 struct qinst *qinst, int instructions_in_sequence,
1101 bool is_thrend)
1102 {
1103 /* No emitting our thrsw while the previous thrsw hasn't happened yet. */
1104 if (scoreboard->last_thrsw_tick + 3 >
1105 scoreboard->tick - instructions_in_sequence) {
1106 return false;
1107 }
1108
1109 for (int slot = 0; slot < instructions_in_sequence; slot++) {
1110 /* No scheduling SFU when the result would land in the other
1111 * thread. The simulator complains for safety, though it
1112 * would only occur for dead code in our case.
1113 */
1114 if (slot > 0 &&
1115 qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
1116 (v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.add.waddr) ||
1117 v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.mul.waddr))) {
1118 return false;
1119 }
1120
1121 if (slot > 0 && qinst->qpu.sig.ldvary)
1122 return false;
1123
1124 if (is_thrend &&
1125 !qpu_instruction_valid_in_thrend_slot(c, qinst, slot)) {
1126 return false;
1127 }
1128
1129 /* Note that the list is circular, so we can only do this up
1130 * to instructions_in_sequence.
1131 */
1132 qinst = (struct qinst *)qinst->link.next;
1133 }
1134
1135 return true;
1136 }
1137
1138 /**
1139 * Emits a THRSW signal in the stream, trying to move it up to pair with
1140 * another instruction.
1141 */
1142 static int
1143 emit_thrsw(struct v3d_compile *c,
1144 struct qblock *block,
1145 struct choose_scoreboard *scoreboard,
1146 struct qinst *inst,
1147 bool is_thrend)
1148 {
1149 int time = 0;
1150
1151 /* There should be nothing in a thrsw inst being scheduled other than
1152 * the signal bits.
1153 */
1154 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);
1155 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP);
1156 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP);
1157
1158 /* Find how far back into previous instructions we can put the THRSW. */
1159 int slots_filled = 0;
1160 struct qinst *merge_inst = NULL;
1161 vir_for_each_inst_rev(prev_inst, block) {
1162 struct v3d_qpu_sig sig = prev_inst->qpu.sig;
1163 sig.thrsw = true;
1164 uint32_t packed_sig;
1165
1166 if (!v3d_qpu_sig_pack(c->devinfo, &sig, &packed_sig))
1167 break;
1168
1169 if (!valid_thrsw_sequence(c, scoreboard,
1170 prev_inst, slots_filled + 1,
1171 is_thrend)) {
1172 break;
1173 }
1174
1175 merge_inst = prev_inst;
1176 if (++slots_filled == 3)
1177 break;
1178 }
1179
1180 bool needs_free = false;
1181 if (merge_inst) {
1182 merge_inst->qpu.sig.thrsw = true;
1183 needs_free = true;
1184 scoreboard->last_thrsw_tick = scoreboard->tick - slots_filled;
1185 } else {
1186 scoreboard->last_thrsw_tick = scoreboard->tick;
1187 insert_scheduled_instruction(c, block, scoreboard, inst);
1188 time++;
1189 slots_filled++;
1190 merge_inst = inst;
1191 }
1192
1193 /* Insert any extra delay slot NOPs we need. */
1194 for (int i = 0; i < 3 - slots_filled; i++) {
1195 emit_nop(c, block, scoreboard);
1196 time++;
1197 }
1198
1199 /* If we're emitting the last THRSW (other than program end), then
1200 * signal that to the HW by emitting two THRSWs in a row.
1201 */
1202 if (inst->is_last_thrsw) {
1203 struct qinst *second_inst =
1204 (struct qinst *)merge_inst->link.next;
1205 second_inst->qpu.sig.thrsw = true;
1206 }
1207
1208 /* If we put our THRSW into another instruction, free up the
1209 * instruction that didn't end up scheduled into the list.
1210 */
1211 if (needs_free)
1212 free(inst);
1213
1214 return time;
1215 }
1216
1217 static uint32_t
1218 schedule_instructions(struct v3d_compile *c,
1219 struct choose_scoreboard *scoreboard,
1220 struct qblock *block,
1221 struct list_head *schedule_list,
1222 enum quniform_contents *orig_uniform_contents,
1223 uint32_t *orig_uniform_data,
1224 uint32_t *next_uniform)
1225 {
1226 const struct v3d_device_info *devinfo = c->devinfo;
1227 uint32_t time = 0;
1228
1229 if (debug) {
1230 fprintf(stderr, "initial deps:\n");
1231 dump_state(devinfo, schedule_list);
1232 fprintf(stderr, "\n");
1233 }
1234
1235 /* Remove non-DAG heads from the list. */
1236 list_for_each_entry_safe(struct schedule_node, n, schedule_list, link) {
1237 if (n->parent_count != 0)
1238 list_del(&n->link);
1239 }
1240
1241 while (!list_empty(schedule_list)) {
1242 struct schedule_node *chosen =
1243 choose_instruction_to_schedule(devinfo,
1244 scoreboard,
1245 schedule_list,
1246 NULL);
1247 struct schedule_node *merge = NULL;
1248
1249 /* If there are no valid instructions to schedule, drop a NOP
1250 * in.
1251 */
1252 struct qinst *qinst = chosen ? chosen->inst : vir_nop();
1253 struct v3d_qpu_instr *inst = &qinst->qpu;
1254
1255 if (debug) {
1256 fprintf(stderr, "t=%4d: current list:\n",
1257 time);
1258 dump_state(devinfo, schedule_list);
1259 fprintf(stderr, "t=%4d: chose: ", time);
1260 v3d_qpu_dump(devinfo, inst);
1261 fprintf(stderr, "\n");
1262 }
1263
1264 /* We can't mark_instruction_scheduled() the chosen inst until
1265 * we're done identifying instructions to merge, so put the
1266 * merged instructions on a list for a moment.
1267 */
1268 struct list_head merged_list;
1269 list_inithead(&merged_list);
1270
1271 /* Schedule this instruction onto the QPU list. Also try to
1272 * find an instruction to pair with it.
1273 */
1274 if (chosen) {
1275 time = MAX2(chosen->unblocked_time, time);
1276 list_del(&chosen->link);
1277 mark_instruction_scheduled(schedule_list, time,
1278 chosen, true);
1279
1280 while ((merge =
1281 choose_instruction_to_schedule(devinfo,
1282 scoreboard,
1283 schedule_list,
1284 chosen))) {
1285 time = MAX2(merge->unblocked_time, time);
1286 list_del(&merge->link);
1287 list_addtail(&merge->link, &merged_list);
1288 (void)qpu_merge_inst(devinfo, inst,
1289 inst, &merge->inst->qpu);
1290 if (merge->inst->uniform != -1) {
1291 chosen->inst->uniform =
1292 merge->inst->uniform;
1293 }
1294
1295 if (debug) {
1296 fprintf(stderr, "t=%4d: merging: ",
1297 time);
1298 v3d_qpu_dump(devinfo, &merge->inst->qpu);
1299 fprintf(stderr, "\n");
1300 fprintf(stderr, " result: ");
1301 v3d_qpu_dump(devinfo, inst);
1302 fprintf(stderr, "\n");
1303 }
1304 }
1305 }
1306
1307 /* Update the uniform index for the rewritten location --
1308 * branch target updating will still need to change
1309 * c->uniform_data[] using this index.
1310 */
1311 if (qinst->uniform != -1) {
1312 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
1313 block->branch_uniform = *next_uniform;
1314
1315 c->uniform_data[*next_uniform] =
1316 orig_uniform_data[qinst->uniform];
1317 c->uniform_contents[*next_uniform] =
1318 orig_uniform_contents[qinst->uniform];
1319 qinst->uniform = *next_uniform;
1320 (*next_uniform)++;
1321 }
1322
1323 if (debug) {
1324 fprintf(stderr, "\n");
1325 }
1326
1327 /* Now that we've scheduled a new instruction, some of its
1328 * children can be promoted to the list of instructions ready to
1329 * be scheduled. Update the children's unblocked time for this
1330 * DAG edge as we do so.
1331 */
1332 mark_instruction_scheduled(schedule_list, time, chosen, false);
1333 list_for_each_entry(struct schedule_node, merge, &merged_list,
1334 link) {
1335 mark_instruction_scheduled(schedule_list, time, merge,
1336 false);
1337
1338 /* The merged VIR instruction doesn't get re-added to the
1339 * block, so free it now.
1340 */
1341 free(merge->inst);
1342 }
1343
1344 if (inst->sig.thrsw) {
1345 time += emit_thrsw(c, block, scoreboard, qinst, false);
1346 } else {
1347 insert_scheduled_instruction(c, block,
1348 scoreboard, qinst);
1349
1350 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
1351 block->branch_qpu_ip = c->qpu_inst_count - 1;
1352 /* Fill the delay slots.
1353 *
1354 * We should fill these with actual instructions,
1355 * instead, but that will probably need to be done
1356 * after this, once we know what the leading
1357 * instructions of the successors are (so we can
1358 * handle A/B register file write latency)
1359 */
1360 for (int i = 0; i < 3; i++)
1361 emit_nop(c, block, scoreboard);
1362 }
1363 }
1364 }
1365
1366 return time;
1367 }
1368
1369 static uint32_t
1370 qpu_schedule_instructions_block(struct v3d_compile *c,
1371 struct choose_scoreboard *scoreboard,
1372 struct qblock *block,
1373 enum quniform_contents *orig_uniform_contents,
1374 uint32_t *orig_uniform_data,
1375 uint32_t *next_uniform)
1376 {
1377 void *mem_ctx = ralloc_context(NULL);
1378 struct list_head schedule_list;
1379
1380 list_inithead(&schedule_list);
1381
1382 /* Wrap each instruction in a scheduler structure. */
1383 while (!list_empty(&block->instructions)) {
1384 struct qinst *qinst = (struct qinst *)block->instructions.next;
1385 struct schedule_node *n =
1386 rzalloc(mem_ctx, struct schedule_node);
1387
1388 n->inst = qinst;
1389
1390 list_del(&qinst->link);
1391 list_addtail(&n->link, &schedule_list);
1392 }
1393
1394 calculate_forward_deps(c, &schedule_list);
1395 calculate_reverse_deps(c, &schedule_list);
1396
1397 list_for_each_entry(struct schedule_node, n, &schedule_list, link) {
1398 compute_delay(n);
1399 }
1400
1401 uint32_t cycles = schedule_instructions(c, scoreboard, block,
1402 &schedule_list,
1403 orig_uniform_contents,
1404 orig_uniform_data,
1405 next_uniform);
1406
1407 ralloc_free(mem_ctx);
1408
1409 return cycles;
1410 }
1411
1412 static void
1413 qpu_set_branch_targets(struct v3d_compile *c)
1414 {
1415 vir_for_each_block(block, c) {
1416 /* The end block of the program has no branch. */
1417 if (!block->successors[0])
1418 continue;
1419
1420 /* If there was no branch instruction, then the successor
1421 * block must follow immediately after this one.
1422 */
1423 if (block->branch_qpu_ip == ~0) {
1424 assert(block->end_qpu_ip + 1 ==
1425 block->successors[0]->start_qpu_ip);
1426 continue;
1427 }
1428
1429 /* Walk back through the delay slots to find the branch
1430 * instr.
1431 */
1432 struct list_head *entry = block->instructions.prev;
1433 for (int i = 0; i < 3; i++)
1434 entry = entry->prev;
1435 struct qinst *branch = container_of(entry, branch, link);
1436 assert(branch->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH);
1437
1438 /* Make sure that the if-we-don't-jump
1439 * successor was scheduled just after the
1440 * delay slots.
1441 */
1442 assert(!block->successors[1] ||
1443 block->successors[1]->start_qpu_ip ==
1444 block->branch_qpu_ip + 4);
1445
1446 branch->qpu.branch.offset =
1447 ((block->successors[0]->start_qpu_ip -
1448 (block->branch_qpu_ip + 4)) *
1449 sizeof(uint64_t));
1450
1451 /* Set up the relative offset to jump in the
1452 * uniform stream.
1453 *
1454 * Use a temporary here, because
1455 * uniform_data[inst->uniform] may be shared
1456 * between multiple instructions.
1457 */
1458 assert(c->uniform_contents[branch->uniform] == QUNIFORM_CONSTANT);
1459 c->uniform_data[branch->uniform] =
1460 (block->successors[0]->start_uniform -
1461 (block->branch_uniform + 1)) * 4;
1462 }
1463 }
1464
1465 uint32_t
1466 v3d_qpu_schedule_instructions(struct v3d_compile *c)
1467 {
1468 const struct v3d_device_info *devinfo = c->devinfo;
1469 struct qblock *end_block = list_last_entry(&c->blocks,
1470 struct qblock, link);
1471
1472 /* We reorder the uniforms as we schedule instructions, so save the
1473 * old data off and replace it.
1474 */
1475 uint32_t *uniform_data = c->uniform_data;
1476 enum quniform_contents *uniform_contents = c->uniform_contents;
1477 c->uniform_contents = ralloc_array(c, enum quniform_contents,
1478 c->num_uniforms);
1479 c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
1480 c->uniform_array_size = c->num_uniforms;
1481 uint32_t next_uniform = 0;
1482
1483 struct choose_scoreboard scoreboard;
1484 memset(&scoreboard, 0, sizeof(scoreboard));
1485 scoreboard.last_ldvary_tick = -10;
1486 scoreboard.last_magic_sfu_write_tick = -10;
1487 scoreboard.last_uniforms_reset_tick = -10;
1488 scoreboard.last_thrsw_tick = -10;
1489
1490 if (debug) {
1491 fprintf(stderr, "Pre-schedule instructions\n");
1492 vir_for_each_block(block, c) {
1493 fprintf(stderr, "BLOCK %d\n", block->index);
1494 list_for_each_entry(struct qinst, qinst,
1495 &block->instructions, link) {
1496 v3d_qpu_dump(devinfo, &qinst->qpu);
1497 fprintf(stderr, "\n");
1498 }
1499 }
1500 fprintf(stderr, "\n");
1501 }
1502
1503 uint32_t cycles = 0;
1504 vir_for_each_block(block, c) {
1505 block->start_qpu_ip = c->qpu_inst_count;
1506 block->branch_qpu_ip = ~0;
1507 block->start_uniform = next_uniform;
1508
1509 cycles += qpu_schedule_instructions_block(c,
1510 &scoreboard,
1511 block,
1512 uniform_contents,
1513 uniform_data,
1514 &next_uniform);
1515
1516 block->end_qpu_ip = c->qpu_inst_count - 1;
1517 }
1518
1519 /* Emit the program-end THRSW instruction. */;
1520 struct qinst *thrsw = vir_nop();
1521 thrsw->qpu.sig.thrsw = true;
1522 emit_thrsw(c, end_block, &scoreboard, thrsw, true);
1523
1524 qpu_set_branch_targets(c);
1525
1526 assert(next_uniform == c->num_uniforms);
1527
1528 return cycles;
1529 }