2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2017 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
37 #include "qpu/qpu_disasm.h"
38 #include "v3d_compiler.h"
39 #include "util/ralloc.h"
43 struct schedule_node_child
;
45 struct schedule_node
{
46 struct list_head link
;
48 struct schedule_node_child
*children
;
50 uint32_t child_array_size
;
51 uint32_t parent_count
;
53 /* Longest cycles + instruction_latency() of any parent of this node. */
54 uint32_t unblocked_time
;
57 * Minimum number of cycles from scheduling this instruction until the
58 * end of the program, based on the slowest dependency chain through
64 * cycles between this instruction being scheduled and when its result
70 struct schedule_node_child
{
71 struct schedule_node
*node
;
72 bool write_after_read
;
75 /* When walking the instructions in reverse, we need to swap before/after in
78 enum direction
{ F
, R
};
80 struct schedule_state
{
81 struct schedule_node
*last_r
[6];
82 struct schedule_node
*last_rf
[64];
83 struct schedule_node
*last_sf
;
84 struct schedule_node
*last_vpm_read
;
85 struct schedule_node
*last_tmu_write
;
86 struct schedule_node
*last_tlb
;
87 struct schedule_node
*last_vpm
;
88 struct schedule_node
*last_unif
;
89 struct schedule_node
*last_rtop
;
91 /* Estimated cycle when the current instruction would start. */
96 add_dep(struct schedule_state
*state
,
97 struct schedule_node
*before
,
98 struct schedule_node
*after
,
101 bool write_after_read
= !write
&& state
->dir
== R
;
103 if (!before
|| !after
)
106 assert(before
!= after
);
108 if (state
->dir
== R
) {
109 struct schedule_node
*t
= before
;
114 for (int i
= 0; i
< before
->child_count
; i
++) {
115 if (before
->children
[i
].node
== after
&&
116 (before
->children
[i
].write_after_read
== write_after_read
)) {
121 if (before
->child_array_size
<= before
->child_count
) {
122 before
->child_array_size
= MAX2(before
->child_array_size
* 2, 16);
123 before
->children
= reralloc(before
, before
->children
,
124 struct schedule_node_child
,
125 before
->child_array_size
);
128 before
->children
[before
->child_count
].node
= after
;
129 before
->children
[before
->child_count
].write_after_read
=
131 before
->child_count
++;
132 after
->parent_count
++;
136 add_read_dep(struct schedule_state
*state
,
137 struct schedule_node
*before
,
138 struct schedule_node
*after
)
140 add_dep(state
, before
, after
, false);
144 add_write_dep(struct schedule_state
*state
,
145 struct schedule_node
**before
,
146 struct schedule_node
*after
)
148 add_dep(state
, *before
, after
, true);
153 qpu_inst_is_tlb(const struct v3d_qpu_instr
*inst
)
155 if (inst
->type
!= V3D_QPU_INSTR_TYPE_ALU
)
158 if (inst
->alu
.add
.magic_write
&&
159 (inst
->alu
.add
.waddr
== V3D_QPU_WADDR_TLB
||
160 inst
->alu
.add
.waddr
== V3D_QPU_WADDR_TLBU
))
163 if (inst
->alu
.mul
.magic_write
&&
164 (inst
->alu
.mul
.waddr
== V3D_QPU_WADDR_TLB
||
165 inst
->alu
.mul
.waddr
== V3D_QPU_WADDR_TLBU
))
172 process_mux_deps(struct schedule_state
*state
, struct schedule_node
*n
,
173 enum v3d_qpu_mux mux
)
177 add_read_dep(state
, state
->last_rf
[n
->inst
->qpu
.raddr_a
], n
);
180 add_read_dep(state
, state
->last_rf
[n
->inst
->qpu
.raddr_b
], n
);
183 add_read_dep(state
, state
->last_r
[mux
- V3D_QPU_MUX_R0
], n
);
190 process_waddr_deps(struct schedule_state
*state
, struct schedule_node
*n
,
191 uint32_t waddr
, bool magic
)
194 add_write_dep(state
, &state
->last_rf
[waddr
], n
);
195 } else if (v3d_qpu_magic_waddr_is_tmu(waddr
)) {
196 add_write_dep(state
, &state
->last_tmu_write
, n
);
197 } else if (v3d_qpu_magic_waddr_is_sfu(waddr
)) {
198 /* Handled by v3d_qpu_writes_r4() check. */
201 case V3D_QPU_WADDR_R0
:
202 case V3D_QPU_WADDR_R1
:
203 case V3D_QPU_WADDR_R2
:
205 &state
->last_r
[waddr
- V3D_QPU_WADDR_R0
],
208 case V3D_QPU_WADDR_R3
:
209 case V3D_QPU_WADDR_R4
:
210 case V3D_QPU_WADDR_R5
:
211 /* Handled by v3d_qpu_writes_r*() checks below. */
214 case V3D_QPU_WADDR_VPM
:
215 case V3D_QPU_WADDR_VPMU
:
216 add_write_dep(state
, &state
->last_vpm
, n
);
219 case V3D_QPU_WADDR_TLB
:
220 case V3D_QPU_WADDR_TLBU
:
221 add_write_dep(state
, &state
->last_tlb
, n
);
224 case V3D_QPU_WADDR_NOP
:
228 fprintf(stderr
, "Unknown waddr %d\n", waddr
);
235 process_cond_deps(struct schedule_state
*state
, struct schedule_node
*n
,
236 enum v3d_qpu_cond cond
)
238 if (cond
!= V3D_QPU_COND_NONE
)
239 add_read_dep(state
, state
->last_sf
, n
);
243 process_pf_deps(struct schedule_state
*state
, struct schedule_node
*n
,
246 if (pf
!= V3D_QPU_PF_NONE
)
247 add_write_dep(state
, &state
->last_sf
, n
);
251 process_uf_deps(struct schedule_state
*state
, struct schedule_node
*n
,
254 if (uf
!= V3D_QPU_UF_NONE
)
255 add_write_dep(state
, &state
->last_sf
, n
);
259 * Common code for dependencies that need to be tracked both forward and
262 * This is for things like "all reads of r4 have to happen between the r4
263 * writes that surround them".
266 calculate_deps(struct schedule_state
*state
, struct schedule_node
*n
)
268 struct qinst
*qinst
= n
->inst
;
269 struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
271 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
) {
272 if (inst
->branch
.cond
!= V3D_QPU_BRANCH_COND_ALWAYS
)
273 add_read_dep(state
, state
->last_sf
, n
);
280 add_write_dep(state
, &state
->last_unif
, n
);
284 assert(inst
->type
== V3D_QPU_INSTR_TYPE_ALU
);
288 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 0)
289 process_mux_deps(state
, n
, inst
->alu
.add
.a
);
290 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 1)
291 process_mux_deps(state
, n
, inst
->alu
.add
.b
);
293 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 0)
294 process_mux_deps(state
, n
, inst
->alu
.mul
.a
);
295 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 1)
296 process_mux_deps(state
, n
, inst
->alu
.mul
.b
);
298 switch (inst
->alu
.add
.op
) {
299 case V3D_QPU_A_VPMSETUP
:
300 /* Could distinguish read/write by unpacking the uniform. */
301 add_write_dep(state
, &state
->last_vpm
, n
);
302 add_write_dep(state
, &state
->last_vpm_read
, n
);
305 case V3D_QPU_A_STVPMV
:
306 case V3D_QPU_A_STVPMD
:
307 case V3D_QPU_A_STVPMP
:
308 add_write_dep(state
, &state
->last_vpm
, n
);
312 add_read_dep(state
, state
->last_tlb
, n
);
315 case V3D_QPU_A_SETMSF
:
316 case V3D_QPU_A_SETREVF
:
317 add_write_dep(state
, &state
->last_tlb
, n
);
320 case V3D_QPU_A_FLAPUSH
:
321 case V3D_QPU_A_FLBPUSH
:
323 case V3D_QPU_A_VFLNA
:
325 case V3D_QPU_A_VFLNB
:
326 add_read_dep(state
, state
->last_sf
, n
);
329 case V3D_QPU_A_FLBPOP
:
330 add_write_dep(state
, &state
->last_sf
, n
);
337 switch (inst
->alu
.mul
.op
) {
338 case V3D_QPU_M_MULTOP
:
339 case V3D_QPU_M_UMUL24
:
340 /* MULTOP sets rtop, and UMUL24 implicitly reads rtop and
341 * resets it to 0. We could possibly reorder umul24s relative
342 * to each other, but for now just keep all the MUL parts in
345 add_write_dep(state
, &state
->last_rtop
, n
);
351 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
352 process_waddr_deps(state
, n
, inst
->alu
.add
.waddr
,
353 inst
->alu
.add
.magic_write
);
355 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
356 process_waddr_deps(state
, n
, inst
->alu
.mul
.waddr
,
357 inst
->alu
.mul
.magic_write
);
360 if (v3d_qpu_writes_r3(inst
))
361 add_write_dep(state
, &state
->last_r
[3], n
);
362 if (v3d_qpu_writes_r4(inst
))
363 add_write_dep(state
, &state
->last_r
[4], n
);
364 if (v3d_qpu_writes_r5(inst
))
365 add_write_dep(state
, &state
->last_r
[5], n
);
367 if (inst
->sig
.thrsw
) {
368 /* All accumulator contents and flags are undefined after the
371 for (int i
= 0; i
< ARRAY_SIZE(state
->last_r
); i
++)
372 add_write_dep(state
, &state
->last_r
[i
], n
);
373 add_write_dep(state
, &state
->last_sf
, n
);
375 /* Scoreboard-locking operations have to stay after the last
378 add_write_dep(state
, &state
->last_tlb
, n
);
380 add_write_dep(state
, &state
->last_tmu_write
, n
);
383 if (inst
->sig
.ldtmu
) {
384 /* TMU loads are coming from a FIFO, so ordering is important.
386 add_write_dep(state
, &state
->last_tmu_write
, n
);
389 if (inst
->sig
.ldtlb
| inst
->sig
.ldtlbu
)
390 add_read_dep(state
, state
->last_tlb
, n
);
393 add_write_dep(state
, &state
->last_vpm_read
, n
);
395 /* inst->sig.ldunif or sideband uniform read */
396 if (qinst
->uniform
!= ~0)
397 add_write_dep(state
, &state
->last_unif
, n
);
399 process_cond_deps(state
, n
, inst
->flags
.ac
);
400 process_cond_deps(state
, n
, inst
->flags
.mc
);
401 process_pf_deps(state
, n
, inst
->flags
.apf
);
402 process_pf_deps(state
, n
, inst
->flags
.mpf
);
403 process_uf_deps(state
, n
, inst
->flags
.auf
);
404 process_uf_deps(state
, n
, inst
->flags
.muf
);
408 calculate_forward_deps(struct v3d_compile
*c
, struct list_head
*schedule_list
)
410 struct schedule_state state
;
412 memset(&state
, 0, sizeof(state
));
415 list_for_each_entry(struct schedule_node
, node
, schedule_list
, link
)
416 calculate_deps(&state
, node
);
420 calculate_reverse_deps(struct v3d_compile
*c
, struct list_head
*schedule_list
)
422 struct list_head
*node
;
423 struct schedule_state state
;
425 memset(&state
, 0, sizeof(state
));
428 for (node
= schedule_list
->prev
; schedule_list
!= node
; node
= node
->prev
) {
429 calculate_deps(&state
, (struct schedule_node
*)node
);
433 struct choose_scoreboard
{
435 int last_sfu_write_tick
;
436 int last_ldvary_tick
;
437 int last_uniforms_reset_tick
;
438 uint32_t last_waddr_add
, last_waddr_mul
;
443 mux_reads_too_soon(struct choose_scoreboard
*scoreboard
,
444 const struct v3d_qpu_instr
*inst
, enum v3d_qpu_mux mux
)
448 if (scoreboard
->last_waddr_add
== inst
->raddr_a
||
449 scoreboard
->last_waddr_mul
== inst
->raddr_a
) {
455 if (scoreboard
->last_waddr_add
== inst
->raddr_b
||
456 scoreboard
->last_waddr_mul
== inst
->raddr_b
) {
462 if (scoreboard
->tick
- scoreboard
->last_sfu_write_tick
<= 2)
467 if (scoreboard
->tick
- scoreboard
->last_ldvary_tick
<= 1)
478 reads_too_soon_after_write(struct choose_scoreboard
*scoreboard
,
481 const struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
483 /* XXX: Branching off of raddr. */
484 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
)
487 assert(inst
->type
== V3D_QPU_INSTR_TYPE_ALU
);
489 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
490 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 0 &&
491 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.add
.a
)) {
494 if (v3d_qpu_add_op_num_src(inst
->alu
.add
.op
) > 1 &&
495 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.add
.b
)) {
500 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
501 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 0 &&
502 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.mul
.a
)) {
505 if (v3d_qpu_mul_op_num_src(inst
->alu
.mul
.op
) > 1 &&
506 mux_reads_too_soon(scoreboard
, inst
, inst
->alu
.mul
.b
)) {
517 writes_too_soon_after_write(struct choose_scoreboard
*scoreboard
,
520 const struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
522 /* Don't schedule any other r4 write too soon after an SFU write.
523 * This would normally be prevented by dependency tracking, but might
524 * occur if a dead SFU computation makes it to scheduling.
526 if (scoreboard
->tick
- scoreboard
->last_sfu_write_tick
< 2 &&
527 v3d_qpu_writes_r4(inst
))
534 pixel_scoreboard_too_soon(struct choose_scoreboard
*scoreboard
,
535 const struct v3d_qpu_instr
*inst
)
537 return (scoreboard
->tick
== 0 && qpu_inst_is_tlb(inst
));
541 get_instruction_priority(const struct v3d_qpu_instr
*inst
)
543 uint32_t baseline_score
;
544 uint32_t next_score
= 0;
546 /* Schedule TLB operations as late as possible, to get more
547 * parallelism between shaders.
549 if (qpu_inst_is_tlb(inst
))
553 /* Schedule texture read results collection late to hide latency. */
558 /* Default score for things that aren't otherwise special. */
559 baseline_score
= next_score
;
562 /* Schedule texture read setup early to hide their latency better. */
563 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
&&
564 ((inst
->alu
.add
.magic_write
&&
565 v3d_qpu_magic_waddr_is_tmu(inst
->alu
.add
.waddr
)) ||
566 (inst
->alu
.mul
.magic_write
&&
567 v3d_qpu_magic_waddr_is_tmu(inst
->alu
.mul
.waddr
)))) {
572 return baseline_score
;
576 qpu_magic_waddr_is_periph(enum v3d_qpu_waddr waddr
)
578 return (v3d_qpu_magic_waddr_is_tmu(waddr
) ||
579 v3d_qpu_magic_waddr_is_sfu(waddr
) ||
580 v3d_qpu_magic_waddr_is_tlb(waddr
) ||
581 v3d_qpu_magic_waddr_is_vpm(waddr
) ||
582 v3d_qpu_magic_waddr_is_tsy(waddr
));
586 qpu_accesses_peripheral(const struct v3d_qpu_instr
*inst
)
588 if (inst
->type
== V3D_QPU_INSTR_TYPE_ALU
) {
589 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
&&
590 inst
->alu
.add
.magic_write
&&
591 qpu_magic_waddr_is_periph(inst
->alu
.add
.waddr
)) {
595 if (inst
->alu
.add
.op
== V3D_QPU_A_VPMSETUP
)
598 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
&&
599 inst
->alu
.mul
.magic_write
&&
600 qpu_magic_waddr_is_periph(inst
->alu
.mul
.waddr
)) {
605 return (inst
->sig
.ldvpm
||
612 qpu_merge_inst(const struct v3d_device_info
*devinfo
,
613 struct v3d_qpu_instr
*result
,
614 const struct v3d_qpu_instr
*a
,
615 const struct v3d_qpu_instr
*b
)
617 if (a
->type
!= V3D_QPU_INSTR_TYPE_ALU
||
618 b
->type
!= V3D_QPU_INSTR_TYPE_ALU
) {
622 /* Can't do more than one peripheral access in an instruction. */
623 if (qpu_accesses_peripheral(a
) && qpu_accesses_peripheral(b
))
626 struct v3d_qpu_instr merge
= *a
;
628 if (b
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
629 if (a
->alu
.add
.op
!= V3D_QPU_A_NOP
)
631 merge
.alu
.add
= b
->alu
.add
;
633 merge
.flags
.ac
= b
->flags
.ac
;
634 merge
.flags
.apf
= b
->flags
.apf
;
635 merge
.flags
.auf
= b
->flags
.auf
;
638 if (b
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
639 if (a
->alu
.mul
.op
!= V3D_QPU_M_NOP
)
641 merge
.alu
.mul
= b
->alu
.mul
;
643 merge
.flags
.mc
= b
->flags
.mc
;
644 merge
.flags
.mpf
= b
->flags
.mpf
;
645 merge
.flags
.muf
= b
->flags
.muf
;
648 if (v3d_qpu_uses_mux(b
, V3D_QPU_MUX_A
)) {
649 if (v3d_qpu_uses_mux(a
, V3D_QPU_MUX_A
) &&
650 a
->raddr_a
!= b
->raddr_a
) {
653 merge
.raddr_a
= b
->raddr_a
;
656 if (v3d_qpu_uses_mux(b
, V3D_QPU_MUX_B
)) {
657 if (v3d_qpu_uses_mux(a
, V3D_QPU_MUX_B
) &&
658 a
->raddr_b
!= b
->raddr_b
) {
661 merge
.raddr_b
= b
->raddr_b
;
664 merge
.sig
.thrsw
|= b
->sig
.thrsw
;
665 merge
.sig
.ldunif
|= b
->sig
.ldunif
;
666 merge
.sig
.ldtmu
|= b
->sig
.ldtmu
;
667 merge
.sig
.ldvary
|= b
->sig
.ldvary
;
668 merge
.sig
.ldvpm
|= b
->sig
.ldvpm
;
669 merge
.sig
.small_imm
|= b
->sig
.small_imm
;
670 merge
.sig
.ldtlb
|= b
->sig
.ldtlb
;
671 merge
.sig
.ldtlbu
|= b
->sig
.ldtlbu
;
672 merge
.sig
.ucb
|= b
->sig
.ucb
;
673 merge
.sig
.rotate
|= b
->sig
.rotate
;
674 merge
.sig
.wrtmuc
|= b
->sig
.wrtmuc
;
677 bool ok
= v3d_qpu_instr_pack(devinfo
, &merge
, &packed
);
680 /* No modifying the real instructions on failure. */
681 assert(ok
|| (a
!= result
&& b
!= result
));
686 static struct schedule_node
*
687 choose_instruction_to_schedule(const struct v3d_device_info
*devinfo
,
688 struct choose_scoreboard
*scoreboard
,
689 struct list_head
*schedule_list
,
690 struct schedule_node
*prev_inst
)
692 struct schedule_node
*chosen
= NULL
;
695 /* Don't pair up anything with a thread switch signal -- emit_thrsw()
696 * will handle pairing it along with filling the delay slots.
699 if (prev_inst
->inst
->qpu
.sig
.thrsw
)
703 list_for_each_entry(struct schedule_node
, n
, schedule_list
, link
) {
704 const struct v3d_qpu_instr
*inst
= &n
->inst
->qpu
;
706 /* Don't choose the branch instruction until it's the last one
707 * left. We'll move it up to fit its delay slots after we
710 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
&&
711 !list_is_singular(schedule_list
)) {
715 /* "An instruction must not read from a location in physical
716 * regfile A or B that was written to by the previous
719 if (reads_too_soon_after_write(scoreboard
, n
->inst
))
722 if (writes_too_soon_after_write(scoreboard
, n
->inst
))
725 /* "A scoreboard wait must not occur in the first two
726 * instructions of a fragment shader. This is either the
727 * explicit Wait for Scoreboard signal or an implicit wait
728 * with the first tile-buffer read or write instruction."
730 if (pixel_scoreboard_too_soon(scoreboard
, inst
))
733 /* ldunif and ldvary both write r5, but ldunif does so a tick
734 * sooner. If the ldvary's r5 wasn't used, then ldunif might
735 * otherwise get scheduled so ldunif and ldvary try to update
736 * r5 in the same tick.
738 if (inst
->sig
.ldunif
&&
739 scoreboard
->tick
== scoreboard
->last_ldvary_tick
+ 1) {
743 /* If we're trying to pair with another instruction, check
744 * that they're compatible.
747 /* Don't pair up a thread switch signal -- we'll
748 * handle pairing it when we pick it on its own.
753 if (prev_inst
->inst
->uniform
!= -1 &&
754 n
->inst
->uniform
!= -1)
757 /* Don't merge in something that will lock the TLB.
758 * Hopwefully what we have in inst will release some
759 * other instructions, allowing us to delay the
760 * TLB-locking instruction until later.
762 if (!scoreboard
->tlb_locked
&& qpu_inst_is_tlb(inst
))
765 struct v3d_qpu_instr merged_inst
;
766 if (!qpu_merge_inst(devinfo
, &merged_inst
,
767 &prev_inst
->inst
->qpu
, inst
)) {
772 int prio
= get_instruction_priority(inst
);
774 /* Found a valid instruction. If nothing better comes along,
783 if (prio
> chosen_prio
) {
786 } else if (prio
< chosen_prio
) {
790 if (n
->delay
> chosen
->delay
) {
793 } else if (n
->delay
< chosen
->delay
) {
802 update_scoreboard_for_magic_waddr(struct choose_scoreboard
*scoreboard
,
803 enum v3d_qpu_waddr waddr
)
805 if (v3d_qpu_magic_waddr_is_sfu(waddr
))
806 scoreboard
->last_sfu_write_tick
= scoreboard
->tick
;
810 update_scoreboard_for_chosen(struct choose_scoreboard
*scoreboard
,
811 const struct v3d_qpu_instr
*inst
)
813 scoreboard
->last_waddr_add
= ~0;
814 scoreboard
->last_waddr_mul
= ~0;
816 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
)
819 assert(inst
->type
== V3D_QPU_INSTR_TYPE_ALU
);
821 if (inst
->alu
.add
.op
!= V3D_QPU_A_NOP
) {
822 if (inst
->alu
.add
.magic_write
) {
823 update_scoreboard_for_magic_waddr(scoreboard
,
824 inst
->alu
.add
.waddr
);
826 scoreboard
->last_waddr_add
= inst
->alu
.add
.waddr
;
830 if (inst
->alu
.mul
.op
!= V3D_QPU_M_NOP
) {
831 if (inst
->alu
.mul
.magic_write
) {
832 update_scoreboard_for_magic_waddr(scoreboard
,
833 inst
->alu
.mul
.waddr
);
835 scoreboard
->last_waddr_mul
= inst
->alu
.mul
.waddr
;
839 if (inst
->sig
.ldvary
)
840 scoreboard
->last_ldvary_tick
= scoreboard
->tick
;
842 if (qpu_inst_is_tlb(inst
))
843 scoreboard
->tlb_locked
= true;
847 dump_state(const struct v3d_device_info
*devinfo
,
848 struct list_head
*schedule_list
)
850 list_for_each_entry(struct schedule_node
, n
, schedule_list
, link
) {
851 fprintf(stderr
, " t=%4d: ", n
->unblocked_time
);
852 v3d_qpu_dump(devinfo
, &n
->inst
->qpu
);
853 fprintf(stderr
, "\n");
855 for (int i
= 0; i
< n
->child_count
; i
++) {
856 struct schedule_node
*child
= n
->children
[i
].node
;
860 fprintf(stderr
, " - ");
861 v3d_qpu_dump(devinfo
, &child
->inst
->qpu
);
862 fprintf(stderr
, " (%d parents, %c)\n",
864 n
->children
[i
].write_after_read
? 'w' : 'r');
869 static uint32_t magic_waddr_latency(enum v3d_qpu_waddr waddr
,
870 const struct v3d_qpu_instr
*after
)
872 /* Apply some huge latency between texture fetch requests and getting
873 * their results back.
875 * FIXME: This is actually pretty bogus. If we do:
884 * we count that as worse than
893 * because we associate the first load_tmu0 with the *second* tmu0_s.
895 if (v3d_qpu_magic_waddr_is_tmu(waddr
) && after
->sig
.ldtmu
)
898 /* Assume that anything depending on us is consuming the SFU result. */
899 if (v3d_qpu_magic_waddr_is_sfu(waddr
))
906 instruction_latency(struct schedule_node
*before
, struct schedule_node
*after
)
908 const struct v3d_qpu_instr
*before_inst
= &before
->inst
->qpu
;
909 const struct v3d_qpu_instr
*after_inst
= &after
->inst
->qpu
;
910 uint32_t latency
= 1;
912 if (before_inst
->type
!= V3D_QPU_INSTR_TYPE_ALU
||
913 after_inst
->type
!= V3D_QPU_INSTR_TYPE_ALU
)
916 if (before_inst
->alu
.add
.magic_write
) {
917 latency
= MAX2(latency
,
918 magic_waddr_latency(before_inst
->alu
.add
.waddr
,
922 if (before_inst
->alu
.mul
.magic_write
) {
923 latency
= MAX2(latency
,
924 magic_waddr_latency(before_inst
->alu
.mul
.waddr
,
931 /** Recursive computation of the delay member of a node. */
933 compute_delay(struct schedule_node
*n
)
935 if (!n
->child_count
) {
938 for (int i
= 0; i
< n
->child_count
; i
++) {
939 if (!n
->children
[i
].node
->delay
)
940 compute_delay(n
->children
[i
].node
);
941 n
->delay
= MAX2(n
->delay
,
942 n
->children
[i
].node
->delay
+
943 instruction_latency(n
, n
->children
[i
].node
));
949 mark_instruction_scheduled(struct list_head
*schedule_list
,
951 struct schedule_node
*node
,
957 for (int i
= node
->child_count
- 1; i
>= 0; i
--) {
958 struct schedule_node
*child
=
959 node
->children
[i
].node
;
964 if (war_only
&& !node
->children
[i
].write_after_read
)
967 /* If the requirement is only that the node not appear before
968 * the last read of its destination, then it can be scheduled
969 * immediately after (or paired with!) the thing reading the
972 uint32_t latency
= 0;
974 latency
= instruction_latency(node
,
975 node
->children
[i
].node
);
978 child
->unblocked_time
= MAX2(child
->unblocked_time
,
980 child
->parent_count
--;
981 if (child
->parent_count
== 0)
982 list_add(&child
->link
, schedule_list
);
984 node
->children
[i
].node
= NULL
;
988 static struct qinst
*
991 struct qreg undef
= { QFILE_NULL
, 0 };
992 struct qinst
*qinst
= vir_add_inst(V3D_QPU_A_NOP
, undef
, undef
, undef
);
998 static struct qinst
*
999 nop_after(struct qinst
*inst
)
1001 struct qinst
*q
= vir_nop();
1003 list_add(&q
->link
, &inst
->link
);
1009 * Emits a THRSW/LTHRSW signal in the stream, trying to move it up to pair
1010 * with another instruction.
1013 emit_thrsw(struct v3d_compile
*c
,
1014 struct choose_scoreboard
*scoreboard
,
1015 const struct v3d_qpu_instr
*inst
)
1017 /* There should be nothing in a thrsw inst being scheduled other than
1020 assert(inst
->type
== V3D_QPU_INSTR_TYPE_ALU
);
1021 assert(inst
->alu
.add
.op
== V3D_QPU_A_NOP
);
1022 assert(inst
->alu
.mul
.op
== V3D_QPU_M_NOP
);
1024 /* Try to find an earlier scheduled instruction that we can merge the
1027 int thrsw_ip
= c
->qpu_inst_count
;
1028 for (int i
= 1; i
<= MIN2(c
->qpu_inst_count
, 3); i
++) {
1029 uint64_t prev_instr
= c
->qpu_insts
[c
->qpu_inst_count
- i
];
1030 uint32_t prev_sig
= QPU_GET_FIELD(prev_instr
, QPU_SIG
);
1032 if (prev_sig
== QPU_SIG_NONE
)
1033 thrsw_ip
= c
->qpu_inst_count
- i
;
1036 if (thrsw_ip
!= c
->qpu_inst_count
) {
1037 /* Merge the thrsw into the existing instruction. */
1038 c
->qpu_insts
[thrsw_ip
] =
1039 QPU_UPDATE_FIELD(c
->qpu_insts
[thrsw_ip
], sig
, QPU_SIG
);
1041 qpu_serialize_one_inst(c
, inst
);
1042 update_scoreboard_for_chosen(scoreboard
, inst
);
1045 /* Fill the delay slots. */
1046 while (c
->qpu_inst_count
< thrsw_ip
+ 3) {
1047 update_scoreboard_for_chosen(scoreboard
, v3d_qpu_nop());
1048 qpu_serialize_one_inst(c
, v3d_qpu_nop());
1054 schedule_instructions(struct v3d_compile
*c
,
1055 struct choose_scoreboard
*scoreboard
,
1056 struct qblock
*block
,
1057 struct list_head
*schedule_list
,
1058 enum quniform_contents
*orig_uniform_contents
,
1059 uint32_t *orig_uniform_data
,
1060 uint32_t *next_uniform
)
1062 const struct v3d_device_info
*devinfo
= c
->devinfo
;
1066 fprintf(stderr
, "initial deps:\n");
1067 dump_state(devinfo
, schedule_list
);
1068 fprintf(stderr
, "\n");
1071 /* Remove non-DAG heads from the list. */
1072 list_for_each_entry_safe(struct schedule_node
, n
, schedule_list
, link
) {
1073 if (n
->parent_count
!= 0)
1077 while (!list_empty(schedule_list
)) {
1078 struct schedule_node
*chosen
=
1079 choose_instruction_to_schedule(devinfo
,
1083 struct schedule_node
*merge
= NULL
;
1085 /* If there are no valid instructions to schedule, drop a NOP
1088 struct qinst
*qinst
= chosen
? chosen
->inst
: vir_nop();
1089 struct v3d_qpu_instr
*inst
= &qinst
->qpu
;
1092 fprintf(stderr
, "t=%4d: current list:\n",
1094 dump_state(devinfo
, schedule_list
);
1095 fprintf(stderr
, "t=%4d: chose: ", time
);
1096 v3d_qpu_dump(devinfo
, inst
);
1097 fprintf(stderr
, "\n");
1100 /* Schedule this instruction onto the QPU list. Also try to
1101 * find an instruction to pair with it.
1104 time
= MAX2(chosen
->unblocked_time
, time
);
1105 list_del(&chosen
->link
);
1106 mark_instruction_scheduled(schedule_list
, time
,
1109 merge
= choose_instruction_to_schedule(devinfo
,
1114 time
= MAX2(merge
->unblocked_time
, time
);
1115 list_del(&merge
->link
);
1116 (void)qpu_merge_inst(devinfo
, inst
,
1117 inst
, &merge
->inst
->qpu
);
1118 if (merge
->inst
->uniform
!= -1) {
1119 chosen
->inst
->uniform
=
1120 merge
->inst
->uniform
;
1124 fprintf(stderr
, "t=%4d: merging: ",
1126 v3d_qpu_dump(devinfo
, &merge
->inst
->qpu
);
1127 fprintf(stderr
, "\n");
1128 fprintf(stderr
, " result: ");
1129 v3d_qpu_dump(devinfo
, inst
);
1130 fprintf(stderr
, "\n");
1135 /* Update the uniform index for the rewritten location --
1136 * branch target updating will still need to change
1137 * c->uniform_data[] using this index.
1139 if (qinst
->uniform
!= -1) {
1140 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
)
1141 block
->branch_uniform
= *next_uniform
;
1143 c
->uniform_data
[*next_uniform
] =
1144 orig_uniform_data
[qinst
->uniform
];
1145 c
->uniform_contents
[*next_uniform
] =
1146 orig_uniform_contents
[qinst
->uniform
];
1147 qinst
->uniform
= *next_uniform
;
1152 fprintf(stderr
, "\n");
1155 /* Now that we've scheduled a new instruction, some of its
1156 * children can be promoted to the list of instructions ready to
1157 * be scheduled. Update the children's unblocked time for this
1158 * DAG edge as we do so.
1160 mark_instruction_scheduled(schedule_list
, time
, chosen
, false);
1163 mark_instruction_scheduled(schedule_list
, time
, merge
,
1166 /* The merged VIR instruction doesn't get re-added to the
1167 * block, so free it now.
1172 if (0 && inst
->sig
.thrsw
) {
1173 /* XXX emit_thrsw(c, scoreboard, qinst); */
1175 c
->qpu_inst_count
++;
1176 list_addtail(&qinst
->link
, &block
->instructions
);
1177 update_scoreboard_for_chosen(scoreboard
, inst
);
1183 if (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
||
1184 inst
->sig
.thrsw
/* XXX */) {
1185 block
->branch_qpu_ip
= c
->qpu_inst_count
- 1;
1186 /* Fill the delay slots.
1188 * We should fill these with actual instructions,
1189 * instead, but that will probably need to be done
1190 * after this, once we know what the leading
1191 * instructions of the successors are (so we can
1192 * handle A/B register file write latency)
1194 /* XXX: scoreboard */
1195 int slots
= (inst
->type
== V3D_QPU_INSTR_TYPE_BRANCH
?
1197 for (int i
= 0; i
< slots
; i
++) {
1198 struct qinst
*nop
= vir_nop();
1199 list_addtail(&nop
->link
, &block
->instructions
);
1201 update_scoreboard_for_chosen(scoreboard
,
1203 c
->qpu_inst_count
++;
1214 qpu_schedule_instructions_block(struct v3d_compile
*c
,
1215 struct choose_scoreboard
*scoreboard
,
1216 struct qblock
*block
,
1217 enum quniform_contents
*orig_uniform_contents
,
1218 uint32_t *orig_uniform_data
,
1219 uint32_t *next_uniform
)
1221 void *mem_ctx
= ralloc_context(NULL
);
1222 struct list_head schedule_list
;
1224 list_inithead(&schedule_list
);
1226 /* Wrap each instruction in a scheduler structure. */
1227 while (!list_empty(&block
->instructions
)) {
1228 struct qinst
*qinst
= (struct qinst
*)block
->instructions
.next
;
1229 struct schedule_node
*n
=
1230 rzalloc(mem_ctx
, struct schedule_node
);
1234 list_del(&qinst
->link
);
1235 list_addtail(&n
->link
, &schedule_list
);
1238 calculate_forward_deps(c
, &schedule_list
);
1239 calculate_reverse_deps(c
, &schedule_list
);
1241 list_for_each_entry(struct schedule_node
, n
, &schedule_list
, link
) {
1245 uint32_t cycles
= schedule_instructions(c
, scoreboard
, block
,
1247 orig_uniform_contents
,
1251 ralloc_free(mem_ctx
);
1257 qpu_set_branch_targets(struct v3d_compile
*c
)
1259 vir_for_each_block(block
, c
) {
1260 /* The end block of the program has no branch. */
1261 if (!block
->successors
[0])
1264 /* If there was no branch instruction, then the successor
1265 * block must follow immediately after this one.
1267 if (block
->branch_qpu_ip
== ~0) {
1268 assert(block
->end_qpu_ip
+ 1 ==
1269 block
->successors
[0]->start_qpu_ip
);
1273 /* Walk back through the delay slots to find the branch
1276 struct list_head
*entry
= block
->instructions
.prev
;
1277 for (int i
= 0; i
< 3; i
++)
1278 entry
= entry
->prev
;
1279 struct qinst
*branch
= container_of(entry
, branch
, link
);
1280 assert(branch
->qpu
.type
== V3D_QPU_INSTR_TYPE_BRANCH
);
1282 /* Make sure that the if-we-don't-jump
1283 * successor was scheduled just after the
1286 assert(!block
->successors
[1] ||
1287 block
->successors
[1]->start_qpu_ip
==
1288 block
->branch_qpu_ip
+ 4);
1290 branch
->qpu
.branch
.offset
=
1291 ((block
->successors
[0]->start_qpu_ip
-
1292 (block
->branch_qpu_ip
+ 4)) *
1295 /* Set up the relative offset to jump in the
1298 * Use a temporary here, because
1299 * uniform_data[inst->uniform] may be shared
1300 * between multiple instructions.
1302 assert(c
->uniform_contents
[branch
->uniform
] == QUNIFORM_CONSTANT
);
1303 c
->uniform_data
[branch
->uniform
] =
1304 (block
->successors
[0]->start_uniform
-
1305 (block
->branch_uniform
+ 1)) * 4;
1310 v3d_qpu_schedule_instructions(struct v3d_compile
*c
)
1312 const struct v3d_device_info
*devinfo
= c
->devinfo
;
1314 /* We reorder the uniforms as we schedule instructions, so save the
1315 * old data off and replace it.
1317 uint32_t *uniform_data
= c
->uniform_data
;
1318 enum quniform_contents
*uniform_contents
= c
->uniform_contents
;
1319 c
->uniform_contents
= ralloc_array(c
, enum quniform_contents
,
1321 c
->uniform_data
= ralloc_array(c
, uint32_t, c
->num_uniforms
);
1322 c
->uniform_array_size
= c
->num_uniforms
;
1323 uint32_t next_uniform
= 0;
1325 struct choose_scoreboard scoreboard
;
1326 memset(&scoreboard
, 0, sizeof(scoreboard
));
1327 scoreboard
.last_waddr_add
= ~0;
1328 scoreboard
.last_waddr_mul
= ~0;
1329 scoreboard
.last_ldvary_tick
= -10;
1330 scoreboard
.last_sfu_write_tick
= -10;
1331 scoreboard
.last_uniforms_reset_tick
= -10;
1334 fprintf(stderr
, "Pre-schedule instructions\n");
1335 vir_for_each_block(block
, c
) {
1336 fprintf(stderr
, "BLOCK %d\n", block
->index
);
1337 list_for_each_entry(struct qinst
, qinst
,
1338 &block
->instructions
, link
) {
1339 v3d_qpu_dump(devinfo
, &qinst
->qpu
);
1340 fprintf(stderr
, "\n");
1343 fprintf(stderr
, "\n");
1346 uint32_t cycles
= 0;
1347 vir_for_each_block(block
, c
) {
1348 block
->start_qpu_ip
= c
->qpu_inst_count
;
1349 block
->branch_qpu_ip
= ~0;
1350 block
->start_uniform
= next_uniform
;
1352 cycles
+= qpu_schedule_instructions_block(c
,
1359 block
->end_qpu_ip
= c
->qpu_inst_count
- 1;
1362 qpu_set_branch_targets(c
);
1364 assert(next_uniform
== c
->num_uniforms
);