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v3d: Switch to using the new SFU instructions on V3D 4.x.
[mesa.git] / src / broadcom / compiler / qpu_schedule.c
1 /*
2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014-2017 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 /**
26 * @file
27 *
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
32 *
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
35 */
36
37 #include "qpu/qpu_disasm.h"
38 #include "v3d_compiler.h"
39 #include "util/ralloc.h"
40
41 static bool debug;
42
43 struct schedule_node_child;
44
45 struct schedule_node {
46 struct list_head link;
47 struct qinst *inst;
48 struct schedule_node_child *children;
49 uint32_t child_count;
50 uint32_t child_array_size;
51 uint32_t parent_count;
52
53 /* Longest cycles + instruction_latency() of any parent of this node. */
54 uint32_t unblocked_time;
55
56 /**
57 * Minimum number of cycles from scheduling this instruction until the
58 * end of the program, based on the slowest dependency chain through
59 * the children.
60 */
61 uint32_t delay;
62
63 /**
64 * cycles between this instruction being scheduled and when its result
65 * can be consumed.
66 */
67 uint32_t latency;
68 };
69
70 struct schedule_node_child {
71 struct schedule_node *node;
72 bool write_after_read;
73 };
74
75 /* When walking the instructions in reverse, we need to swap before/after in
76 * add_dep().
77 */
78 enum direction { F, R };
79
80 struct schedule_state {
81 const struct v3d_device_info *devinfo;
82 struct schedule_node *last_r[6];
83 struct schedule_node *last_rf[64];
84 struct schedule_node *last_sf;
85 struct schedule_node *last_vpm_read;
86 struct schedule_node *last_tmu_write;
87 struct schedule_node *last_tmu_config;
88 struct schedule_node *last_tlb;
89 struct schedule_node *last_vpm;
90 struct schedule_node *last_unif;
91 struct schedule_node *last_rtop;
92 enum direction dir;
93 /* Estimated cycle when the current instruction would start. */
94 uint32_t time;
95 };
96
97 static void
98 add_dep(struct schedule_state *state,
99 struct schedule_node *before,
100 struct schedule_node *after,
101 bool write)
102 {
103 bool write_after_read = !write && state->dir == R;
104
105 if (!before || !after)
106 return;
107
108 assert(before != after);
109
110 if (state->dir == R) {
111 struct schedule_node *t = before;
112 before = after;
113 after = t;
114 }
115
116 for (int i = 0; i < before->child_count; i++) {
117 if (before->children[i].node == after &&
118 (before->children[i].write_after_read == write_after_read)) {
119 return;
120 }
121 }
122
123 if (before->child_array_size <= before->child_count) {
124 before->child_array_size = MAX2(before->child_array_size * 2, 16);
125 before->children = reralloc(before, before->children,
126 struct schedule_node_child,
127 before->child_array_size);
128 }
129
130 before->children[before->child_count].node = after;
131 before->children[before->child_count].write_after_read =
132 write_after_read;
133 before->child_count++;
134 after->parent_count++;
135 }
136
137 static void
138 add_read_dep(struct schedule_state *state,
139 struct schedule_node *before,
140 struct schedule_node *after)
141 {
142 add_dep(state, before, after, false);
143 }
144
145 static void
146 add_write_dep(struct schedule_state *state,
147 struct schedule_node **before,
148 struct schedule_node *after)
149 {
150 add_dep(state, *before, after, true);
151 *before = after;
152 }
153
154 static bool
155 qpu_inst_is_tlb(const struct v3d_qpu_instr *inst)
156 {
157 if (inst->type != V3D_QPU_INSTR_TYPE_ALU)
158 return false;
159
160 if (inst->alu.add.magic_write &&
161 (inst->alu.add.waddr == V3D_QPU_WADDR_TLB ||
162 inst->alu.add.waddr == V3D_QPU_WADDR_TLBU))
163 return true;
164
165 if (inst->alu.mul.magic_write &&
166 (inst->alu.mul.waddr == V3D_QPU_WADDR_TLB ||
167 inst->alu.mul.waddr == V3D_QPU_WADDR_TLBU))
168 return true;
169
170 return false;
171 }
172
173 static void
174 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
175 enum v3d_qpu_mux mux)
176 {
177 switch (mux) {
178 case V3D_QPU_MUX_A:
179 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_a], n);
180 break;
181 case V3D_QPU_MUX_B:
182 add_read_dep(state, state->last_rf[n->inst->qpu.raddr_b], n);
183 break;
184 default:
185 add_read_dep(state, state->last_r[mux - V3D_QPU_MUX_R0], n);
186 break;
187 }
188 }
189
190
191 static void
192 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
193 uint32_t waddr, bool magic)
194 {
195 if (!magic) {
196 add_write_dep(state, &state->last_rf[waddr], n);
197 } else if (v3d_qpu_magic_waddr_is_tmu(waddr)) {
198 add_write_dep(state, &state->last_tmu_write, n);
199 switch (waddr) {
200 case V3D_QPU_WADDR_TMUS:
201 case V3D_QPU_WADDR_TMUSCM:
202 case V3D_QPU_WADDR_TMUSF:
203 case V3D_QPU_WADDR_TMUSLOD:
204 add_write_dep(state, &state->last_tmu_config, n);
205 break;
206 default:
207 break;
208 }
209 } else if (v3d_qpu_magic_waddr_is_sfu(waddr)) {
210 /* Handled by v3d_qpu_writes_r4() check. */
211 } else {
212 switch (waddr) {
213 case V3D_QPU_WADDR_R0:
214 case V3D_QPU_WADDR_R1:
215 case V3D_QPU_WADDR_R2:
216 add_write_dep(state,
217 &state->last_r[waddr - V3D_QPU_WADDR_R0],
218 n);
219 break;
220 case V3D_QPU_WADDR_R3:
221 case V3D_QPU_WADDR_R4:
222 case V3D_QPU_WADDR_R5:
223 /* Handled by v3d_qpu_writes_r*() checks below. */
224 break;
225
226 case V3D_QPU_WADDR_VPM:
227 case V3D_QPU_WADDR_VPMU:
228 add_write_dep(state, &state->last_vpm, n);
229 break;
230
231 case V3D_QPU_WADDR_TLB:
232 case V3D_QPU_WADDR_TLBU:
233 add_write_dep(state, &state->last_tlb, n);
234 break;
235
236 case V3D_QPU_WADDR_NOP:
237 break;
238
239 default:
240 fprintf(stderr, "Unknown waddr %d\n", waddr);
241 abort();
242 }
243 }
244 }
245
246 static void
247 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
248 enum v3d_qpu_cond cond)
249 {
250 if (cond != V3D_QPU_COND_NONE)
251 add_read_dep(state, state->last_sf, n);
252 }
253
254 static void
255 process_pf_deps(struct schedule_state *state, struct schedule_node *n,
256 enum v3d_qpu_pf pf)
257 {
258 if (pf != V3D_QPU_PF_NONE)
259 add_write_dep(state, &state->last_sf, n);
260 }
261
262 static void
263 process_uf_deps(struct schedule_state *state, struct schedule_node *n,
264 enum v3d_qpu_uf uf)
265 {
266 if (uf != V3D_QPU_UF_NONE)
267 add_write_dep(state, &state->last_sf, n);
268 }
269
270 /**
271 * Common code for dependencies that need to be tracked both forward and
272 * backward.
273 *
274 * This is for things like "all reads of r4 have to happen between the r4
275 * writes that surround them".
276 */
277 static void
278 calculate_deps(struct schedule_state *state, struct schedule_node *n)
279 {
280 const struct v3d_device_info *devinfo = state->devinfo;
281 struct qinst *qinst = n->inst;
282 struct v3d_qpu_instr *inst = &qinst->qpu;
283
284 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
285 if (inst->branch.cond != V3D_QPU_BRANCH_COND_ALWAYS)
286 add_read_dep(state, state->last_sf, n);
287
288 /* XXX: BDI */
289 /* XXX: BDU */
290 /* XXX: ub */
291 /* XXX: raddr_a */
292
293 add_write_dep(state, &state->last_unif, n);
294 return;
295 }
296
297 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
298
299 /* XXX: LOAD_IMM */
300
301 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0)
302 process_mux_deps(state, n, inst->alu.add.a);
303 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1)
304 process_mux_deps(state, n, inst->alu.add.b);
305
306 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0)
307 process_mux_deps(state, n, inst->alu.mul.a);
308 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1)
309 process_mux_deps(state, n, inst->alu.mul.b);
310
311 switch (inst->alu.add.op) {
312 case V3D_QPU_A_VPMSETUP:
313 /* Could distinguish read/write by unpacking the uniform. */
314 add_write_dep(state, &state->last_vpm, n);
315 add_write_dep(state, &state->last_vpm_read, n);
316 break;
317
318 case V3D_QPU_A_STVPMV:
319 case V3D_QPU_A_STVPMD:
320 case V3D_QPU_A_STVPMP:
321 add_write_dep(state, &state->last_vpm, n);
322 break;
323
324 case V3D_QPU_A_VPMWT:
325 add_read_dep(state, state->last_vpm, n);
326 break;
327
328 case V3D_QPU_A_MSF:
329 add_read_dep(state, state->last_tlb, n);
330 break;
331
332 case V3D_QPU_A_SETMSF:
333 case V3D_QPU_A_SETREVF:
334 add_write_dep(state, &state->last_tlb, n);
335 break;
336
337 case V3D_QPU_A_FLAPUSH:
338 case V3D_QPU_A_FLBPUSH:
339 case V3D_QPU_A_VFLA:
340 case V3D_QPU_A_VFLNA:
341 case V3D_QPU_A_VFLB:
342 case V3D_QPU_A_VFLNB:
343 add_read_dep(state, state->last_sf, n);
344 break;
345
346 case V3D_QPU_A_FLPOP:
347 add_write_dep(state, &state->last_sf, n);
348 break;
349
350 default:
351 break;
352 }
353
354 switch (inst->alu.mul.op) {
355 case V3D_QPU_M_MULTOP:
356 case V3D_QPU_M_UMUL24:
357 /* MULTOP sets rtop, and UMUL24 implicitly reads rtop and
358 * resets it to 0. We could possibly reorder umul24s relative
359 * to each other, but for now just keep all the MUL parts in
360 * order.
361 */
362 add_write_dep(state, &state->last_rtop, n);
363 break;
364 default:
365 break;
366 }
367
368 if (inst->alu.add.op != V3D_QPU_A_NOP) {
369 process_waddr_deps(state, n, inst->alu.add.waddr,
370 inst->alu.add.magic_write);
371 }
372 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
373 process_waddr_deps(state, n, inst->alu.mul.waddr,
374 inst->alu.mul.magic_write);
375 }
376 if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) {
377 process_waddr_deps(state, n, inst->sig_addr,
378 inst->sig_magic);
379 }
380
381 if (v3d_qpu_writes_r3(devinfo, inst))
382 add_write_dep(state, &state->last_r[3], n);
383 if (v3d_qpu_writes_r4(devinfo, inst))
384 add_write_dep(state, &state->last_r[4], n);
385 if (v3d_qpu_writes_r5(devinfo, inst))
386 add_write_dep(state, &state->last_r[5], n);
387
388 if (inst->sig.thrsw) {
389 /* All accumulator contents and flags are undefined after the
390 * switch.
391 */
392 for (int i = 0; i < ARRAY_SIZE(state->last_r); i++)
393 add_write_dep(state, &state->last_r[i], n);
394 add_write_dep(state, &state->last_sf, n);
395
396 /* Scoreboard-locking operations have to stay after the last
397 * thread switch.
398 */
399 add_write_dep(state, &state->last_tlb, n);
400
401 add_write_dep(state, &state->last_tmu_write, n);
402 add_write_dep(state, &state->last_tmu_config, n);
403 }
404
405 if (inst->sig.ldtmu) {
406 /* TMU loads are coming from a FIFO, so ordering is important.
407 */
408 add_write_dep(state, &state->last_tmu_write, n);
409 }
410
411 if (inst->sig.wrtmuc)
412 add_write_dep(state, &state->last_tmu_config, n);
413
414 if (inst->sig.ldtlb | inst->sig.ldtlbu)
415 add_read_dep(state, state->last_tlb, n);
416
417 if (inst->sig.ldvpm)
418 add_write_dep(state, &state->last_vpm_read, n);
419
420 /* inst->sig.ldunif or sideband uniform read */
421 if (qinst->uniform != ~0)
422 add_write_dep(state, &state->last_unif, n);
423
424 process_cond_deps(state, n, inst->flags.ac);
425 process_cond_deps(state, n, inst->flags.mc);
426 process_pf_deps(state, n, inst->flags.apf);
427 process_pf_deps(state, n, inst->flags.mpf);
428 process_uf_deps(state, n, inst->flags.auf);
429 process_uf_deps(state, n, inst->flags.muf);
430 }
431
432 static void
433 calculate_forward_deps(struct v3d_compile *c, struct list_head *schedule_list)
434 {
435 struct schedule_state state;
436
437 memset(&state, 0, sizeof(state));
438 state.devinfo = c->devinfo;
439 state.dir = F;
440
441 list_for_each_entry(struct schedule_node, node, schedule_list, link)
442 calculate_deps(&state, node);
443 }
444
445 static void
446 calculate_reverse_deps(struct v3d_compile *c, struct list_head *schedule_list)
447 {
448 struct list_head *node;
449 struct schedule_state state;
450
451 memset(&state, 0, sizeof(state));
452 state.devinfo = c->devinfo;
453 state.dir = R;
454
455 for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
456 calculate_deps(&state, (struct schedule_node *)node);
457 }
458 }
459
460 struct choose_scoreboard {
461 int tick;
462 int last_magic_sfu_write_tick;
463 int last_ldvary_tick;
464 int last_uniforms_reset_tick;
465 bool tlb_locked;
466 };
467
468 static bool
469 mux_reads_too_soon(struct choose_scoreboard *scoreboard,
470 const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux)
471 {
472 switch (mux) {
473 case V3D_QPU_MUX_R4:
474 if (scoreboard->tick - scoreboard->last_magic_sfu_write_tick <= 2)
475 return true;
476 break;
477
478 case V3D_QPU_MUX_R5:
479 if (scoreboard->tick - scoreboard->last_ldvary_tick <= 1)
480 return true;
481 break;
482 default:
483 break;
484 }
485
486 return false;
487 }
488
489 static bool
490 reads_too_soon_after_write(struct choose_scoreboard *scoreboard,
491 struct qinst *qinst)
492 {
493 const struct v3d_qpu_instr *inst = &qinst->qpu;
494
495 /* XXX: Branching off of raddr. */
496 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
497 return false;
498
499 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
500
501 if (inst->alu.add.op != V3D_QPU_A_NOP) {
502 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0 &&
503 mux_reads_too_soon(scoreboard, inst, inst->alu.add.a)) {
504 return true;
505 }
506 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1 &&
507 mux_reads_too_soon(scoreboard, inst, inst->alu.add.b)) {
508 return true;
509 }
510 }
511
512 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
513 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 0 &&
514 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.a)) {
515 return true;
516 }
517 if (v3d_qpu_mul_op_num_src(inst->alu.mul.op) > 1 &&
518 mux_reads_too_soon(scoreboard, inst, inst->alu.mul.b)) {
519 return true;
520 }
521 }
522
523 /* XXX: imm */
524
525 return false;
526 }
527
528 static bool
529 writes_too_soon_after_write(const struct v3d_device_info *devinfo,
530 struct choose_scoreboard *scoreboard,
531 struct qinst *qinst)
532 {
533 const struct v3d_qpu_instr *inst = &qinst->qpu;
534
535 /* Don't schedule any other r4 write too soon after an SFU write.
536 * This would normally be prevented by dependency tracking, but might
537 * occur if a dead SFU computation makes it to scheduling.
538 */
539 if (scoreboard->tick - scoreboard->last_magic_sfu_write_tick < 2 &&
540 v3d_qpu_writes_r4(devinfo, inst))
541 return true;
542
543 return false;
544 }
545
546 static bool
547 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard,
548 const struct v3d_qpu_instr *inst)
549 {
550 return (scoreboard->tick == 0 && qpu_inst_is_tlb(inst));
551 }
552
553 static int
554 get_instruction_priority(const struct v3d_qpu_instr *inst)
555 {
556 uint32_t baseline_score;
557 uint32_t next_score = 0;
558
559 /* Schedule TLB operations as late as possible, to get more
560 * parallelism between shaders.
561 */
562 if (qpu_inst_is_tlb(inst))
563 return next_score;
564 next_score++;
565
566 /* Schedule texture read results collection late to hide latency. */
567 if (inst->sig.ldtmu)
568 return next_score;
569 next_score++;
570
571 /* Default score for things that aren't otherwise special. */
572 baseline_score = next_score;
573 next_score++;
574
575 /* Schedule texture read setup early to hide their latency better. */
576 if (v3d_qpu_writes_tmu(inst))
577 return next_score;
578 next_score++;
579
580 return baseline_score;
581 }
582
583 static bool
584 qpu_magic_waddr_is_periph(enum v3d_qpu_waddr waddr)
585 {
586 return (v3d_qpu_magic_waddr_is_tmu(waddr) ||
587 v3d_qpu_magic_waddr_is_sfu(waddr) ||
588 v3d_qpu_magic_waddr_is_tlb(waddr) ||
589 v3d_qpu_magic_waddr_is_vpm(waddr) ||
590 v3d_qpu_magic_waddr_is_tsy(waddr));
591 }
592
593 static bool
594 qpu_accesses_peripheral(const struct v3d_qpu_instr *inst)
595 {
596 if (v3d_qpu_uses_vpm(inst))
597 return true;
598 if (v3d_qpu_uses_sfu(inst))
599 return true;
600
601 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
602 if (inst->alu.add.op != V3D_QPU_A_NOP &&
603 inst->alu.add.magic_write &&
604 qpu_magic_waddr_is_periph(inst->alu.add.waddr)) {
605 return true;
606 }
607
608 if (inst->alu.mul.op != V3D_QPU_M_NOP &&
609 inst->alu.mul.magic_write &&
610 qpu_magic_waddr_is_periph(inst->alu.mul.waddr)) {
611 return true;
612 }
613 }
614
615 return (inst->sig.ldvpm ||
616 inst->sig.ldtmu ||
617 inst->sig.ldtlb ||
618 inst->sig.ldtlbu ||
619 inst->sig.wrtmuc);
620 }
621
622 static bool
623 qpu_merge_inst(const struct v3d_device_info *devinfo,
624 struct v3d_qpu_instr *result,
625 const struct v3d_qpu_instr *a,
626 const struct v3d_qpu_instr *b)
627 {
628 if (a->type != V3D_QPU_INSTR_TYPE_ALU ||
629 b->type != V3D_QPU_INSTR_TYPE_ALU) {
630 return false;
631 }
632
633 /* Can't do more than one peripheral access in an instruction.
634 *
635 * XXX: V3D 4.1 allows TMU read along with a VPM read or write, and
636 * WRTMUC with a TMU magic register write (other than tmuc).
637 */
638 if (qpu_accesses_peripheral(a) && qpu_accesses_peripheral(b))
639 return false;
640
641 struct v3d_qpu_instr merge = *a;
642
643 if (b->alu.add.op != V3D_QPU_A_NOP) {
644 if (a->alu.add.op != V3D_QPU_A_NOP)
645 return false;
646 merge.alu.add = b->alu.add;
647
648 merge.flags.ac = b->flags.ac;
649 merge.flags.apf = b->flags.apf;
650 merge.flags.auf = b->flags.auf;
651 }
652
653 if (b->alu.mul.op != V3D_QPU_M_NOP) {
654 if (a->alu.mul.op != V3D_QPU_M_NOP)
655 return false;
656 merge.alu.mul = b->alu.mul;
657
658 merge.flags.mc = b->flags.mc;
659 merge.flags.mpf = b->flags.mpf;
660 merge.flags.muf = b->flags.muf;
661 }
662
663 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_A)) {
664 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_A) &&
665 a->raddr_a != b->raddr_a) {
666 return false;
667 }
668 merge.raddr_a = b->raddr_a;
669 }
670
671 if (v3d_qpu_uses_mux(b, V3D_QPU_MUX_B)) {
672 if (v3d_qpu_uses_mux(a, V3D_QPU_MUX_B) &&
673 a->raddr_b != b->raddr_b) {
674 return false;
675 }
676 merge.raddr_b = b->raddr_b;
677 }
678
679 merge.sig.thrsw |= b->sig.thrsw;
680 merge.sig.ldunif |= b->sig.ldunif;
681 merge.sig.ldunifrf |= b->sig.ldunifrf;
682 merge.sig.ldunifa |= b->sig.ldunifa;
683 merge.sig.ldunifarf |= b->sig.ldunifarf;
684 merge.sig.ldtmu |= b->sig.ldtmu;
685 merge.sig.ldvary |= b->sig.ldvary;
686 merge.sig.ldvpm |= b->sig.ldvpm;
687 merge.sig.small_imm |= b->sig.small_imm;
688 merge.sig.ldtlb |= b->sig.ldtlb;
689 merge.sig.ldtlbu |= b->sig.ldtlbu;
690 merge.sig.ucb |= b->sig.ucb;
691 merge.sig.rotate |= b->sig.rotate;
692 merge.sig.wrtmuc |= b->sig.wrtmuc;
693
694 if (v3d_qpu_sig_writes_address(devinfo, &a->sig) &&
695 v3d_qpu_sig_writes_address(devinfo, &b->sig))
696 return false;
697 merge.sig_addr |= b->sig_addr;
698 merge.sig_magic |= b->sig_magic;
699
700 uint64_t packed;
701 bool ok = v3d_qpu_instr_pack(devinfo, &merge, &packed);
702
703 *result = merge;
704 /* No modifying the real instructions on failure. */
705 assert(ok || (a != result && b != result));
706
707 return ok;
708 }
709
710 static struct schedule_node *
711 choose_instruction_to_schedule(const struct v3d_device_info *devinfo,
712 struct choose_scoreboard *scoreboard,
713 struct list_head *schedule_list,
714 struct schedule_node *prev_inst)
715 {
716 struct schedule_node *chosen = NULL;
717 int chosen_prio = 0;
718
719 /* Don't pair up anything with a thread switch signal -- emit_thrsw()
720 * will handle pairing it along with filling the delay slots.
721 */
722 if (prev_inst) {
723 if (prev_inst->inst->qpu.sig.thrsw)
724 return NULL;
725 }
726
727 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
728 const struct v3d_qpu_instr *inst = &n->inst->qpu;
729
730 /* Don't choose the branch instruction until it's the last one
731 * left. We'll move it up to fit its delay slots after we
732 * choose it.
733 */
734 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH &&
735 !list_is_singular(schedule_list)) {
736 continue;
737 }
738
739 /* "An instruction must not read from a location in physical
740 * regfile A or B that was written to by the previous
741 * instruction."
742 */
743 if (reads_too_soon_after_write(scoreboard, n->inst))
744 continue;
745
746 if (writes_too_soon_after_write(devinfo, scoreboard, n->inst))
747 continue;
748
749 /* "A scoreboard wait must not occur in the first two
750 * instructions of a fragment shader. This is either the
751 * explicit Wait for Scoreboard signal or an implicit wait
752 * with the first tile-buffer read or write instruction."
753 */
754 if (pixel_scoreboard_too_soon(scoreboard, inst))
755 continue;
756
757 /* ldunif and ldvary both write r5, but ldunif does so a tick
758 * sooner. If the ldvary's r5 wasn't used, then ldunif might
759 * otherwise get scheduled so ldunif and ldvary try to update
760 * r5 in the same tick.
761 */
762 if ((inst->sig.ldunif || inst->sig.ldunifa) &&
763 scoreboard->tick == scoreboard->last_ldvary_tick + 1) {
764 continue;
765 }
766
767 /* If we're trying to pair with another instruction, check
768 * that they're compatible.
769 */
770 if (prev_inst) {
771 /* Don't pair up a thread switch signal -- we'll
772 * handle pairing it when we pick it on its own.
773 */
774 if (inst->sig.thrsw)
775 continue;
776
777 if (prev_inst->inst->uniform != -1 &&
778 n->inst->uniform != -1)
779 continue;
780
781 /* Don't merge in something that will lock the TLB.
782 * Hopwefully what we have in inst will release some
783 * other instructions, allowing us to delay the
784 * TLB-locking instruction until later.
785 */
786 if (!scoreboard->tlb_locked && qpu_inst_is_tlb(inst))
787 continue;
788
789 struct v3d_qpu_instr merged_inst;
790 if (!qpu_merge_inst(devinfo, &merged_inst,
791 &prev_inst->inst->qpu, inst)) {
792 continue;
793 }
794 }
795
796 int prio = get_instruction_priority(inst);
797
798 /* Found a valid instruction. If nothing better comes along,
799 * this one works.
800 */
801 if (!chosen) {
802 chosen = n;
803 chosen_prio = prio;
804 continue;
805 }
806
807 if (prio > chosen_prio) {
808 chosen = n;
809 chosen_prio = prio;
810 } else if (prio < chosen_prio) {
811 continue;
812 }
813
814 if (n->delay > chosen->delay) {
815 chosen = n;
816 chosen_prio = prio;
817 } else if (n->delay < chosen->delay) {
818 continue;
819 }
820 }
821
822 return chosen;
823 }
824
825 static void
826 update_scoreboard_for_magic_waddr(struct choose_scoreboard *scoreboard,
827 enum v3d_qpu_waddr waddr)
828 {
829 if (v3d_qpu_magic_waddr_is_sfu(waddr))
830 scoreboard->last_magic_sfu_write_tick = scoreboard->tick;
831 }
832
833 static void
834 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
835 const struct v3d_qpu_instr *inst)
836 {
837 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
838 return;
839
840 assert(inst->type == V3D_QPU_INSTR_TYPE_ALU);
841
842 if (inst->alu.add.op != V3D_QPU_A_NOP) {
843 if (inst->alu.add.magic_write) {
844 update_scoreboard_for_magic_waddr(scoreboard,
845 inst->alu.add.waddr);
846 }
847 }
848
849 if (inst->alu.mul.op != V3D_QPU_M_NOP) {
850 if (inst->alu.mul.magic_write) {
851 update_scoreboard_for_magic_waddr(scoreboard,
852 inst->alu.mul.waddr);
853 }
854 }
855
856 if (inst->sig.ldvary)
857 scoreboard->last_ldvary_tick = scoreboard->tick;
858
859 if (qpu_inst_is_tlb(inst))
860 scoreboard->tlb_locked = true;
861 }
862
863 static void
864 dump_state(const struct v3d_device_info *devinfo,
865 struct list_head *schedule_list)
866 {
867 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
868 fprintf(stderr, " t=%4d: ", n->unblocked_time);
869 v3d_qpu_dump(devinfo, &n->inst->qpu);
870 fprintf(stderr, "\n");
871
872 for (int i = 0; i < n->child_count; i++) {
873 struct schedule_node *child = n->children[i].node;
874 if (!child)
875 continue;
876
877 fprintf(stderr, " - ");
878 v3d_qpu_dump(devinfo, &child->inst->qpu);
879 fprintf(stderr, " (%d parents, %c)\n",
880 child->parent_count,
881 n->children[i].write_after_read ? 'w' : 'r');
882 }
883 }
884 }
885
886 static uint32_t magic_waddr_latency(enum v3d_qpu_waddr waddr,
887 const struct v3d_qpu_instr *after)
888 {
889 /* Apply some huge latency between texture fetch requests and getting
890 * their results back.
891 *
892 * FIXME: This is actually pretty bogus. If we do:
893 *
894 * mov tmu0_s, a
895 * <a bit of math>
896 * mov tmu0_s, b
897 * load_tmu0
898 * <more math>
899 * load_tmu0
900 *
901 * we count that as worse than
902 *
903 * mov tmu0_s, a
904 * mov tmu0_s, b
905 * <lots of math>
906 * load_tmu0
907 * <more math>
908 * load_tmu0
909 *
910 * because we associate the first load_tmu0 with the *second* tmu0_s.
911 */
912 if (v3d_qpu_magic_waddr_is_tmu(waddr) && after->sig.ldtmu)
913 return 100;
914
915 /* Assume that anything depending on us is consuming the SFU result. */
916 if (v3d_qpu_magic_waddr_is_sfu(waddr))
917 return 3;
918
919 return 1;
920 }
921
922 static uint32_t
923 instruction_latency(struct schedule_node *before, struct schedule_node *after)
924 {
925 const struct v3d_qpu_instr *before_inst = &before->inst->qpu;
926 const struct v3d_qpu_instr *after_inst = &after->inst->qpu;
927 uint32_t latency = 1;
928
929 if (before_inst->type != V3D_QPU_INSTR_TYPE_ALU ||
930 after_inst->type != V3D_QPU_INSTR_TYPE_ALU)
931 return latency;
932
933 if (before_inst->alu.add.magic_write) {
934 latency = MAX2(latency,
935 magic_waddr_latency(before_inst->alu.add.waddr,
936 after_inst));
937 }
938
939 if (before_inst->alu.mul.magic_write) {
940 latency = MAX2(latency,
941 magic_waddr_latency(before_inst->alu.mul.waddr,
942 after_inst));
943 }
944
945 return latency;
946 }
947
948 /** Recursive computation of the delay member of a node. */
949 static void
950 compute_delay(struct schedule_node *n)
951 {
952 if (!n->child_count) {
953 n->delay = 1;
954 } else {
955 for (int i = 0; i < n->child_count; i++) {
956 if (!n->children[i].node->delay)
957 compute_delay(n->children[i].node);
958 n->delay = MAX2(n->delay,
959 n->children[i].node->delay +
960 instruction_latency(n, n->children[i].node));
961 }
962 }
963 }
964
965 static void
966 mark_instruction_scheduled(struct list_head *schedule_list,
967 uint32_t time,
968 struct schedule_node *node,
969 bool war_only)
970 {
971 if (!node)
972 return;
973
974 for (int i = node->child_count - 1; i >= 0; i--) {
975 struct schedule_node *child =
976 node->children[i].node;
977
978 if (!child)
979 continue;
980
981 if (war_only && !node->children[i].write_after_read)
982 continue;
983
984 /* If the requirement is only that the node not appear before
985 * the last read of its destination, then it can be scheduled
986 * immediately after (or paired with!) the thing reading the
987 * destination.
988 */
989 uint32_t latency = 0;
990 if (!war_only) {
991 latency = instruction_latency(node,
992 node->children[i].node);
993 }
994
995 child->unblocked_time = MAX2(child->unblocked_time,
996 time + latency);
997 child->parent_count--;
998 if (child->parent_count == 0)
999 list_add(&child->link, schedule_list);
1000
1001 node->children[i].node = NULL;
1002 }
1003 }
1004
1005 static void
1006 insert_scheduled_instruction(struct v3d_compile *c,
1007 struct qblock *block,
1008 struct choose_scoreboard *scoreboard,
1009 struct qinst *inst)
1010 {
1011 list_addtail(&inst->link, &block->instructions);
1012
1013 update_scoreboard_for_chosen(scoreboard, &inst->qpu);
1014 c->qpu_inst_count++;
1015 scoreboard->tick++;
1016 }
1017
1018 static struct qinst *
1019 vir_nop()
1020 {
1021 struct qreg undef = { QFILE_NULL, 0 };
1022 struct qinst *qinst = vir_add_inst(V3D_QPU_A_NOP, undef, undef, undef);
1023
1024 return qinst;
1025 }
1026
1027 static void
1028 emit_nop(struct v3d_compile *c, struct qblock *block,
1029 struct choose_scoreboard *scoreboard)
1030 {
1031 insert_scheduled_instruction(c, block, scoreboard, vir_nop());
1032 }
1033
1034 static bool
1035 qpu_instruction_valid_in_thrend_slot(struct v3d_compile *c,
1036 const struct qinst *qinst, int slot)
1037 {
1038 const struct v3d_qpu_instr *inst = &qinst->qpu;
1039
1040 /* Only TLB Z writes are prohibited in the last slot, but we don't
1041 * have those flagged so prohibit all TLB ops for now.
1042 */
1043 if (slot == 2 && qpu_inst_is_tlb(inst))
1044 return false;
1045
1046 if (slot > 0 && qinst->uniform != ~0)
1047 return false;
1048
1049 if (v3d_qpu_uses_vpm(inst))
1050 return false;
1051
1052 if (inst->sig.ldvary)
1053 return false;
1054
1055 if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
1056 /* GFXH-1625: TMUWT not allowed in the final instruction. */
1057 if (slot == 2 && inst->alu.add.op == V3D_QPU_A_TMUWT)
1058 return false;
1059
1060 /* No writing physical registers at the end. */
1061 if (!inst->alu.add.magic_write ||
1062 !inst->alu.mul.magic_write) {
1063 return false;
1064 }
1065
1066 if (c->devinfo->ver < 40 && inst->alu.add.op == V3D_QPU_A_SETMSF)
1067 return false;
1068
1069 /* RF0-2 might be overwritten during the delay slots by
1070 * fragment shader setup.
1071 */
1072 if (inst->raddr_a < 3 &&
1073 (inst->alu.add.a == V3D_QPU_MUX_A ||
1074 inst->alu.add.b == V3D_QPU_MUX_A ||
1075 inst->alu.mul.a == V3D_QPU_MUX_A ||
1076 inst->alu.mul.b == V3D_QPU_MUX_A)) {
1077 return false;
1078 }
1079
1080 if (inst->raddr_b < 3 &&
1081 !inst->sig.small_imm &&
1082 (inst->alu.add.a == V3D_QPU_MUX_B ||
1083 inst->alu.add.b == V3D_QPU_MUX_B ||
1084 inst->alu.mul.a == V3D_QPU_MUX_B ||
1085 inst->alu.mul.b == V3D_QPU_MUX_B)) {
1086 return false;
1087 }
1088 }
1089
1090 return true;
1091 }
1092
1093 static bool
1094 valid_thrsw_sequence(struct v3d_compile *c,
1095 struct qinst *qinst, int instructions_in_sequence,
1096 bool is_thrend)
1097 {
1098 for (int slot = 0; slot < instructions_in_sequence; slot++) {
1099 /* No scheduling SFU when the result would land in the other
1100 * thread. The simulator complains for safety, though it
1101 * would only occur for dead code in our case.
1102 */
1103 if (slot > 0 &&
1104 qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU &&
1105 (v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.add.waddr) ||
1106 v3d_qpu_magic_waddr_is_sfu(qinst->qpu.alu.mul.waddr))) {
1107 return false;
1108 }
1109
1110 if (slot > 0 && qinst->qpu.sig.ldvary)
1111 return false;
1112
1113 if (is_thrend &&
1114 !qpu_instruction_valid_in_thrend_slot(c, qinst, slot)) {
1115 return false;
1116 }
1117
1118 /* Note that the list is circular, so we can only do this up
1119 * to instructions_in_sequence.
1120 */
1121 qinst = (struct qinst *)qinst->link.next;
1122 }
1123
1124 return true;
1125 }
1126
1127 /**
1128 * Emits a THRSW signal in the stream, trying to move it up to pair with
1129 * another instruction.
1130 */
1131 static int
1132 emit_thrsw(struct v3d_compile *c,
1133 struct qblock *block,
1134 struct choose_scoreboard *scoreboard,
1135 struct qinst *inst,
1136 bool is_thrend)
1137 {
1138 int time = 0;
1139
1140 /* There should be nothing in a thrsw inst being scheduled other than
1141 * the signal bits.
1142 */
1143 assert(inst->qpu.type == V3D_QPU_INSTR_TYPE_ALU);
1144 assert(inst->qpu.alu.add.op == V3D_QPU_A_NOP);
1145 assert(inst->qpu.alu.mul.op == V3D_QPU_M_NOP);
1146
1147 /* Find how far back into previous instructions we can put the THRSW. */
1148 int slots_filled = 0;
1149 struct qinst *merge_inst = NULL;
1150 vir_for_each_inst_rev(prev_inst, block) {
1151 struct v3d_qpu_sig sig = prev_inst->qpu.sig;
1152 sig.thrsw = true;
1153 uint32_t packed_sig;
1154
1155 if (!v3d_qpu_sig_pack(c->devinfo, &sig, &packed_sig))
1156 break;
1157
1158 if (!valid_thrsw_sequence(c, prev_inst, slots_filled + 1,
1159 is_thrend)) {
1160 break;
1161 }
1162
1163 merge_inst = prev_inst;
1164 if (++slots_filled == 3)
1165 break;
1166 }
1167
1168 bool needs_free = false;
1169 if (merge_inst) {
1170 merge_inst->qpu.sig.thrsw = true;
1171 needs_free = true;
1172 } else {
1173 insert_scheduled_instruction(c, block, scoreboard, inst);
1174 time++;
1175 slots_filled++;
1176 merge_inst = inst;
1177 }
1178
1179 /* Insert any extra delay slot NOPs we need. */
1180 for (int i = 0; i < 3 - slots_filled; i++) {
1181 emit_nop(c, block, scoreboard);
1182 time++;
1183 }
1184
1185 /* If we're emitting the last THRSW (other than program end), then
1186 * signal that to the HW by emitting two THRSWs in a row.
1187 */
1188 if (inst->is_last_thrsw) {
1189 struct qinst *second_inst =
1190 (struct qinst *)merge_inst->link.next;
1191 second_inst->qpu.sig.thrsw = true;
1192 }
1193
1194 /* If we put our THRSW into another instruction, free up the
1195 * instruction that didn't end up scheduled into the list.
1196 */
1197 if (needs_free)
1198 free(inst);
1199
1200 return time;
1201 }
1202
1203 static uint32_t
1204 schedule_instructions(struct v3d_compile *c,
1205 struct choose_scoreboard *scoreboard,
1206 struct qblock *block,
1207 struct list_head *schedule_list,
1208 enum quniform_contents *orig_uniform_contents,
1209 uint32_t *orig_uniform_data,
1210 uint32_t *next_uniform)
1211 {
1212 const struct v3d_device_info *devinfo = c->devinfo;
1213 uint32_t time = 0;
1214
1215 if (debug) {
1216 fprintf(stderr, "initial deps:\n");
1217 dump_state(devinfo, schedule_list);
1218 fprintf(stderr, "\n");
1219 }
1220
1221 /* Remove non-DAG heads from the list. */
1222 list_for_each_entry_safe(struct schedule_node, n, schedule_list, link) {
1223 if (n->parent_count != 0)
1224 list_del(&n->link);
1225 }
1226
1227 while (!list_empty(schedule_list)) {
1228 struct schedule_node *chosen =
1229 choose_instruction_to_schedule(devinfo,
1230 scoreboard,
1231 schedule_list,
1232 NULL);
1233 struct schedule_node *merge = NULL;
1234
1235 /* If there are no valid instructions to schedule, drop a NOP
1236 * in.
1237 */
1238 struct qinst *qinst = chosen ? chosen->inst : vir_nop();
1239 struct v3d_qpu_instr *inst = &qinst->qpu;
1240
1241 if (debug) {
1242 fprintf(stderr, "t=%4d: current list:\n",
1243 time);
1244 dump_state(devinfo, schedule_list);
1245 fprintf(stderr, "t=%4d: chose: ", time);
1246 v3d_qpu_dump(devinfo, inst);
1247 fprintf(stderr, "\n");
1248 }
1249
1250 /* We can't mark_instruction_scheduled() the chosen inst until
1251 * we're done identifying instructions to merge, so put the
1252 * merged instructions on a list for a moment.
1253 */
1254 struct list_head merged_list;
1255 list_inithead(&merged_list);
1256
1257 /* Schedule this instruction onto the QPU list. Also try to
1258 * find an instruction to pair with it.
1259 */
1260 if (chosen) {
1261 time = MAX2(chosen->unblocked_time, time);
1262 list_del(&chosen->link);
1263 mark_instruction_scheduled(schedule_list, time,
1264 chosen, true);
1265
1266 while ((merge =
1267 choose_instruction_to_schedule(devinfo,
1268 scoreboard,
1269 schedule_list,
1270 chosen))) {
1271 time = MAX2(merge->unblocked_time, time);
1272 list_del(&merge->link);
1273 list_addtail(&merge->link, &merged_list);
1274 (void)qpu_merge_inst(devinfo, inst,
1275 inst, &merge->inst->qpu);
1276 if (merge->inst->uniform != -1) {
1277 chosen->inst->uniform =
1278 merge->inst->uniform;
1279 }
1280
1281 if (debug) {
1282 fprintf(stderr, "t=%4d: merging: ",
1283 time);
1284 v3d_qpu_dump(devinfo, &merge->inst->qpu);
1285 fprintf(stderr, "\n");
1286 fprintf(stderr, " result: ");
1287 v3d_qpu_dump(devinfo, inst);
1288 fprintf(stderr, "\n");
1289 }
1290 }
1291 }
1292
1293 /* Update the uniform index for the rewritten location --
1294 * branch target updating will still need to change
1295 * c->uniform_data[] using this index.
1296 */
1297 if (qinst->uniform != -1) {
1298 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH)
1299 block->branch_uniform = *next_uniform;
1300
1301 c->uniform_data[*next_uniform] =
1302 orig_uniform_data[qinst->uniform];
1303 c->uniform_contents[*next_uniform] =
1304 orig_uniform_contents[qinst->uniform];
1305 qinst->uniform = *next_uniform;
1306 (*next_uniform)++;
1307 }
1308
1309 if (debug) {
1310 fprintf(stderr, "\n");
1311 }
1312
1313 /* Now that we've scheduled a new instruction, some of its
1314 * children can be promoted to the list of instructions ready to
1315 * be scheduled. Update the children's unblocked time for this
1316 * DAG edge as we do so.
1317 */
1318 mark_instruction_scheduled(schedule_list, time, chosen, false);
1319 list_for_each_entry(struct schedule_node, merge, &merged_list,
1320 link) {
1321 mark_instruction_scheduled(schedule_list, time, merge,
1322 false);
1323
1324 /* The merged VIR instruction doesn't get re-added to the
1325 * block, so free it now.
1326 */
1327 free(merge->inst);
1328 }
1329
1330 if (inst->sig.thrsw) {
1331 time += emit_thrsw(c, block, scoreboard, qinst, false);
1332 } else {
1333 insert_scheduled_instruction(c, block,
1334 scoreboard, qinst);
1335
1336 if (inst->type == V3D_QPU_INSTR_TYPE_BRANCH) {
1337 block->branch_qpu_ip = c->qpu_inst_count - 1;
1338 /* Fill the delay slots.
1339 *
1340 * We should fill these with actual instructions,
1341 * instead, but that will probably need to be done
1342 * after this, once we know what the leading
1343 * instructions of the successors are (so we can
1344 * handle A/B register file write latency)
1345 */
1346 for (int i = 0; i < 3; i++)
1347 emit_nop(c, block, scoreboard);
1348 }
1349 }
1350 }
1351
1352 return time;
1353 }
1354
1355 static uint32_t
1356 qpu_schedule_instructions_block(struct v3d_compile *c,
1357 struct choose_scoreboard *scoreboard,
1358 struct qblock *block,
1359 enum quniform_contents *orig_uniform_contents,
1360 uint32_t *orig_uniform_data,
1361 uint32_t *next_uniform)
1362 {
1363 void *mem_ctx = ralloc_context(NULL);
1364 struct list_head schedule_list;
1365
1366 list_inithead(&schedule_list);
1367
1368 /* Wrap each instruction in a scheduler structure. */
1369 while (!list_empty(&block->instructions)) {
1370 struct qinst *qinst = (struct qinst *)block->instructions.next;
1371 struct schedule_node *n =
1372 rzalloc(mem_ctx, struct schedule_node);
1373
1374 n->inst = qinst;
1375
1376 list_del(&qinst->link);
1377 list_addtail(&n->link, &schedule_list);
1378 }
1379
1380 calculate_forward_deps(c, &schedule_list);
1381 calculate_reverse_deps(c, &schedule_list);
1382
1383 list_for_each_entry(struct schedule_node, n, &schedule_list, link) {
1384 compute_delay(n);
1385 }
1386
1387 uint32_t cycles = schedule_instructions(c, scoreboard, block,
1388 &schedule_list,
1389 orig_uniform_contents,
1390 orig_uniform_data,
1391 next_uniform);
1392
1393 ralloc_free(mem_ctx);
1394
1395 return cycles;
1396 }
1397
1398 static void
1399 qpu_set_branch_targets(struct v3d_compile *c)
1400 {
1401 vir_for_each_block(block, c) {
1402 /* The end block of the program has no branch. */
1403 if (!block->successors[0])
1404 continue;
1405
1406 /* If there was no branch instruction, then the successor
1407 * block must follow immediately after this one.
1408 */
1409 if (block->branch_qpu_ip == ~0) {
1410 assert(block->end_qpu_ip + 1 ==
1411 block->successors[0]->start_qpu_ip);
1412 continue;
1413 }
1414
1415 /* Walk back through the delay slots to find the branch
1416 * instr.
1417 */
1418 struct list_head *entry = block->instructions.prev;
1419 for (int i = 0; i < 3; i++)
1420 entry = entry->prev;
1421 struct qinst *branch = container_of(entry, branch, link);
1422 assert(branch->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH);
1423
1424 /* Make sure that the if-we-don't-jump
1425 * successor was scheduled just after the
1426 * delay slots.
1427 */
1428 assert(!block->successors[1] ||
1429 block->successors[1]->start_qpu_ip ==
1430 block->branch_qpu_ip + 4);
1431
1432 branch->qpu.branch.offset =
1433 ((block->successors[0]->start_qpu_ip -
1434 (block->branch_qpu_ip + 4)) *
1435 sizeof(uint64_t));
1436
1437 /* Set up the relative offset to jump in the
1438 * uniform stream.
1439 *
1440 * Use a temporary here, because
1441 * uniform_data[inst->uniform] may be shared
1442 * between multiple instructions.
1443 */
1444 assert(c->uniform_contents[branch->uniform] == QUNIFORM_CONSTANT);
1445 c->uniform_data[branch->uniform] =
1446 (block->successors[0]->start_uniform -
1447 (block->branch_uniform + 1)) * 4;
1448 }
1449 }
1450
1451 uint32_t
1452 v3d_qpu_schedule_instructions(struct v3d_compile *c)
1453 {
1454 const struct v3d_device_info *devinfo = c->devinfo;
1455 struct qblock *end_block = list_last_entry(&c->blocks,
1456 struct qblock, link);
1457
1458 /* We reorder the uniforms as we schedule instructions, so save the
1459 * old data off and replace it.
1460 */
1461 uint32_t *uniform_data = c->uniform_data;
1462 enum quniform_contents *uniform_contents = c->uniform_contents;
1463 c->uniform_contents = ralloc_array(c, enum quniform_contents,
1464 c->num_uniforms);
1465 c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
1466 c->uniform_array_size = c->num_uniforms;
1467 uint32_t next_uniform = 0;
1468
1469 struct choose_scoreboard scoreboard;
1470 memset(&scoreboard, 0, sizeof(scoreboard));
1471 scoreboard.last_ldvary_tick = -10;
1472 scoreboard.last_magic_sfu_write_tick = -10;
1473 scoreboard.last_uniforms_reset_tick = -10;
1474
1475 if (debug) {
1476 fprintf(stderr, "Pre-schedule instructions\n");
1477 vir_for_each_block(block, c) {
1478 fprintf(stderr, "BLOCK %d\n", block->index);
1479 list_for_each_entry(struct qinst, qinst,
1480 &block->instructions, link) {
1481 v3d_qpu_dump(devinfo, &qinst->qpu);
1482 fprintf(stderr, "\n");
1483 }
1484 }
1485 fprintf(stderr, "\n");
1486 }
1487
1488 uint32_t cycles = 0;
1489 vir_for_each_block(block, c) {
1490 block->start_qpu_ip = c->qpu_inst_count;
1491 block->branch_qpu_ip = ~0;
1492 block->start_uniform = next_uniform;
1493
1494 cycles += qpu_schedule_instructions_block(c,
1495 &scoreboard,
1496 block,
1497 uniform_contents,
1498 uniform_data,
1499 &next_uniform);
1500
1501 block->end_qpu_ip = c->qpu_inst_count - 1;
1502 }
1503
1504 /* Emit the program-end THRSW instruction. */;
1505 struct qinst *thrsw = vir_nop();
1506 thrsw->qpu.sig.thrsw = true;
1507 emit_thrsw(c, end_block, &scoreboard, thrsw, true);
1508
1509 qpu_set_branch_targets(c);
1510
1511 assert(next_uniform == c->num_uniforms);
1512
1513 return cycles;
1514 }