src/broadcom/compiler/v3d40_tex.c

   1 /*
   2  * Copyright © 2016-2018 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "v3d_compiler.h"
  25
  26 /* We don't do any address packing. */
  27 #define __gen_user_data void
  28 #define __gen_address_type uint32_t
  29 #define __gen_address_offset(reloc) (*reloc)
  30 #define __gen_emit_reloc(cl, reloc)
  31 #include "cle/v3d_packet_v41_pack.h"
  32
  33 static void
  34 vir_TMU_WRITE(struct v3d_compile *c, enum v3d_qpu_waddr waddr, struct qreg val,
  35               int *tmu_writes)
  36 {
  37         /* XXX perf: We should figure out how to merge ALU operations
  38          * producing the val with this MOV, when possible.
  39          */
  40         vir_MOV_dest(c, vir_reg(QFILE_MAGIC, waddr), val);
  41
  42         (*tmu_writes)++;
  43 }
  44
  45 static void
  46 vir_WRTMUC(struct v3d_compile *c, enum quniform_contents contents, uint32_t data)
  47 {
  48         struct qinst *inst = vir_NOP(c);
  49         inst->qpu.sig.wrtmuc = true;
  50         inst->uniform = vir_get_uniform_index(c, contents, data);
  51 }
  52
  53 static const struct V3D41_TMU_CONFIG_PARAMETER_1 p1_unpacked_default = {
  54         .per_pixel_mask_enable = true,
  55 };
  56
  57 static const struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked_default = {
  58         .op = V3D_TMU_OP_REGULAR,
  59 };
  60
  61 void
  62 v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
  63 {
  64         unsigned unit = instr->texture_index;
  65         int tmu_writes = 0;
  66
  67         struct V3D41_TMU_CONFIG_PARAMETER_0 p0_unpacked = {
  68         };
  69
  70         assert(instr->op != nir_texop_lod || c->devinfo->ver >= 42);
  71
  72         struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked = {
  73                 .op = V3D_TMU_OP_REGULAR,
  74
  75                 .gather_mode = instr->op == nir_texop_tg4,
  76                 .gather_component = instr->component,
  77
  78                 .coefficient_mode = instr->op == nir_texop_txd,
  79
  80                 .disable_autolod = instr->op == nir_texop_tg4
  81         };
  82
  83         int non_array_components =
  84            instr->op != nir_texop_lod ?
  85            instr->coord_components - instr->is_array :
  86            instr->coord_components;
  87
  88         struct qreg s;
  89
  90         for (unsigned i = 0; i < instr->num_srcs; i++) {
  91                 switch (instr->src[i].src_type) {
  92                 case nir_tex_src_coord:
  93                         /* S triggers the lookup, so save it for the end. */
  94                         s = ntq_get_src(c, instr->src[i].src, 0);
  95
  96                         if (non_array_components > 1) {
  97                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUT,
  98                                               ntq_get_src(c, instr->src[i].src,
  99                                                           1), &tmu_writes);
 100                         }
 101                         if (non_array_components > 2) {
 102                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUR,
 103                                               ntq_get_src(c, instr->src[i].src,
 104                                                           2), &tmu_writes);
 105                         }
 106
 107                         if (instr->is_array) {
 108                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUI,
 109                                               ntq_get_src(c, instr->src[i].src,
 110                                                           instr->coord_components - 1),
 111                                               &tmu_writes);
 112                         }
 113                         break;
 114
 115                 case nir_tex_src_bias:
 116                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUB,
 117                                       ntq_get_src(c, instr->src[i].src, 0),
 118                                       &tmu_writes);
 119                         break;
 120
 121                 case nir_tex_src_lod:
 122                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUB,
 123                                       ntq_get_src(c, instr->src[i].src, 0),
 124                                       &tmu_writes);
 125
 126                         if (instr->op != nir_texop_txf)
 127                                 p2_unpacked.disable_autolod = true;
 128                         break;
 129
 130                 case nir_tex_src_comparator:
 131                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUDREF,
 132                                       ntq_get_src(c, instr->src[i].src, 0),
 133                                       &tmu_writes);
 134                         break;
 135
 136                 case nir_tex_src_offset: {
 137                         if (nir_src_is_const(instr->src[i].src)) {
 138                                 p2_unpacked.offset_s = nir_src_comp_as_int(instr->src[i].src, 0);
 139                                 if (non_array_components >= 2)
 140                                         p2_unpacked.offset_t =
 141                                                 nir_src_comp_as_int(instr->src[i].src, 1);
 142                                 if (non_array_components >= 3)
 143                                         p2_unpacked.offset_r =
 144                                                 nir_src_comp_as_int(instr->src[i].src, 2);
 145                         } else {
 146                                 struct qreg mask = vir_uniform_ui(c, 0xf);
 147                                 struct qreg x, y, offset;
 148
 149                                 x = vir_AND(c, ntq_get_src(c, instr->src[i].src,
 150                                                            0), mask);
 151                                 y = vir_AND(c, ntq_get_src(c, instr->src[i].src,
 152                                                            1), mask);
 153                                 offset = vir_OR(c, x,
 154                                                 vir_SHL(c, y,
 155                                                         vir_uniform_ui(c, 4)));
 156
 157                                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUOFF,
 158                                               offset, &tmu_writes);
 159                         }
 160                         break;
 161                 }
 162
 163                 default:
 164                         unreachable("unknown texture source");
 165                 }
 166         }
 167
 168         /* Limit the number of channels returned to both how many the NIR
 169          * instruction writes and how many the instruction could produce.
 170          */
 171         assert(instr->dest.is_ssa);
 172         p0_unpacked.return_words_of_texture_data =
 173                 nir_ssa_def_components_read(&instr->dest.ssa);
 174
 175         assert(p0_unpacked.return_words_of_texture_data != 0);
 176
 177         uint32_t p0_packed;
 178         V3D41_TMU_CONFIG_PARAMETER_0_pack(NULL,
 179                                           (uint8_t *)&p0_packed,
 180                                           &p0_unpacked);
 181
 182         uint32_t p2_packed;
 183         V3D41_TMU_CONFIG_PARAMETER_2_pack(NULL,
 184                                           (uint8_t *)&p2_packed,
 185                                           &p2_unpacked);
 186
 187         /* We manually set the LOD Query bit (see
 188          * V3D42_TMU_CONFIG_PARAMETER_2) as right now is the only V42 specific
 189          * feature over V41 we are using
 190          */
 191         if (instr->op == nir_texop_lod)
 192            p2_packed |= 1UL << 24;
 193
 194         /* Load unit number into the high bits of the texture address field,
 195          * which will be be used by the driver to decide which texture to put
 196          * in the actual address field.
 197          */
 198         p0_packed |= unit << 24;
 199
 200         vir_WRTMUC(c, QUNIFORM_TMU_CONFIG_P0, p0_packed);
 201
 202         /* Even if the texture operation doesn't need a sampler by
 203          * itself, we still need to add the sampler configuration
 204          * parameter if the output is 32 bit
 205          */
 206         bool output_type_32_bit = (c->key->tex[unit].return_size == 32 &&
 207                                    !instr->is_shadow);
 208
 209         /*
 210          * p1 is optional, but we can skip it only if p2 can be skipped too
 211          */
 212         bool needs_p2_config =
 213                 (instr->op == nir_texop_lod ||
 214                  memcmp(&p2_unpacked, &p2_unpacked_default, sizeof(p2_unpacked)) != 0);
 215
 216         if (output_type_32_bit ||
 217             nir_tex_instr_need_sampler(instr)) {
 218                 struct V3D41_TMU_CONFIG_PARAMETER_1 p1_unpacked = {
 219                         .output_type_32_bit = output_type_32_bit,
 220
 221                         .unnormalized_coordinates = (instr->sampler_dim ==
 222                                                      GLSL_SAMPLER_DIM_RECT),
 223                 };
 224
 225                 /* Word enables can't ask for more channels than the
 226                  * output type could provide (2 for f16, 4 for
 227                  * 32-bit).
 228                  */
 229                 assert(!p1_unpacked.output_type_32_bit ||
 230                        p0_unpacked.return_words_of_texture_data < (1 << 4));
 231                 assert(p1_unpacked.output_type_32_bit ||
 232                        p0_unpacked.return_words_of_texture_data < (1 << 2));
 233
 234                 uint32_t p1_packed;
 235                 V3D41_TMU_CONFIG_PARAMETER_1_pack(NULL,
 236                                                   (uint8_t *)&p1_packed,
 237                                                   &p1_unpacked);
 238
 239                 /* Load unit number into the high bits of the sampler
 240                  * address field, which will be be used by the driver
 241                  * to decide which sampler to put in the actual
 242                  * address field.
 243                  */
 244                 p1_packed |= unit << 24;
 245
 246                 vir_WRTMUC(c, QUNIFORM_TMU_CONFIG_P1, p1_packed);
 247         } else if (needs_p2_config) {
 248                 /* Configuration parameters need to be set up in
 249                  * order, and if P2 is needed, you need to set up P1
 250                  * too even if sampler info is not needed by the
 251                  * texture operation. But we can set up default info,
 252                  * and avoid asking the driver for the sampler state
 253                  * address
 254                  */
 255                 uint32_t p1_packed_default;
 256                 V3D41_TMU_CONFIG_PARAMETER_1_pack(NULL,
 257                                                   (uint8_t *)&p1_packed_default,
 258                                                   &p1_unpacked_default);
 259                 vir_WRTMUC(c, QUNIFORM_CONSTANT, p1_packed_default);
 260         }
 261
 262         if (needs_p2_config)
 263                 vir_WRTMUC(c, QUNIFORM_CONSTANT, p2_packed);
 264
 265         if (instr->op == nir_texop_txf) {
 266                 assert(instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE);
 267                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSF, s, &tmu_writes);
 268         } else if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
 269                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSCM, s, &tmu_writes);
 270         } else {
 271                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUS, s, &tmu_writes);
 272         }
 273
 274         vir_emit_thrsw(c);
 275
 276         /* The input FIFO has 16 slots across all threads, so make sure we
 277          * don't overfill our allocation.
 278          */
 279         while (tmu_writes > 16 / c->threads)
 280                 c->threads /= 2;
 281
 282         for (int i = 0; i < 4; i++) {
 283                 if (p0_unpacked.return_words_of_texture_data & (1 << i))
 284                         ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
 285         }
 286 }
 287
 288 static uint32_t
 289 v3d40_image_load_store_tmu_op(nir_intrinsic_instr *instr)
 290 {
 291         switch (instr->intrinsic) {
 292         case nir_intrinsic_image_load:
 293         case nir_intrinsic_image_store:
 294                 return V3D_TMU_OP_REGULAR;
 295         case nir_intrinsic_image_atomic_add:
 296                 return v3d_get_op_for_atomic_add(instr, 3);
 297         case nir_intrinsic_image_atomic_imin:
 298                 return V3D_TMU_OP_WRITE_SMIN;
 299         case nir_intrinsic_image_atomic_umin:
 300                 return V3D_TMU_OP_WRITE_UMIN_FULL_L1_CLEAR;
 301         case nir_intrinsic_image_atomic_imax:
 302                 return V3D_TMU_OP_WRITE_SMAX;
 303         case nir_intrinsic_image_atomic_umax:
 304                 return V3D_TMU_OP_WRITE_UMAX;
 305         case nir_intrinsic_image_atomic_and:
 306                 return V3D_TMU_OP_WRITE_AND_READ_INC;
 307         case nir_intrinsic_image_atomic_or:
 308                 return V3D_TMU_OP_WRITE_OR_READ_DEC;
 309         case nir_intrinsic_image_atomic_xor:
 310                 return V3D_TMU_OP_WRITE_XOR_READ_NOT;
 311         case nir_intrinsic_image_atomic_exchange:
 312                 return V3D_TMU_OP_WRITE_XCHG_READ_FLUSH;
 313         case nir_intrinsic_image_atomic_comp_swap:
 314                 return V3D_TMU_OP_WRITE_CMPXCHG_READ_FLUSH;
 315         default:
 316                 unreachable("unknown image intrinsic");
 317         };
 318 }
 319
 320 void
 321 v3d40_vir_emit_image_load_store(struct v3d_compile *c,
 322                                 nir_intrinsic_instr *instr)
 323 {
 324         unsigned format = nir_intrinsic_format(instr);
 325         unsigned unit = nir_src_as_uint(instr->src[0]);
 326         int tmu_writes = 0;
 327
 328         struct V3D41_TMU_CONFIG_PARAMETER_0 p0_unpacked = {
 329         };
 330
 331         struct V3D41_TMU_CONFIG_PARAMETER_1 p1_unpacked = {
 332                 .per_pixel_mask_enable = true,
 333                 .output_type_32_bit = v3d_gl_format_is_return_32(format),
 334         };
 335
 336         struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked = { 0 };
 337
 338         p2_unpacked.op = v3d40_image_load_store_tmu_op(instr);
 339
 340         /* If we were able to replace atomic_add for an inc/dec, then we
 341          * need/can to do things slightly different, like not loading the
 342          * amount to add/sub, as that is implicit.
 343          */
 344         bool atomic_add_replaced = (instr->intrinsic == nir_intrinsic_image_atomic_add &&
 345                                     (p2_unpacked.op == V3D_TMU_OP_WRITE_AND_READ_INC ||
 346                                      p2_unpacked.op == V3D_TMU_OP_WRITE_OR_READ_DEC));
 347
 348         bool is_1d = false;
 349         switch (nir_intrinsic_image_dim(instr)) {
 350         case GLSL_SAMPLER_DIM_1D:
 351                 is_1d = true;
 352                 break;
 353         case GLSL_SAMPLER_DIM_BUF:
 354                 break;
 355         case GLSL_SAMPLER_DIM_2D:
 356         case GLSL_SAMPLER_DIM_RECT:
 357                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUT,
 358                               ntq_get_src(c, instr->src[1], 1), &tmu_writes);
 359                 break;
 360         case GLSL_SAMPLER_DIM_3D:
 361         case GLSL_SAMPLER_DIM_CUBE:
 362                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUT,
 363                               ntq_get_src(c, instr->src[1], 1), &tmu_writes);
 364                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUR,
 365                               ntq_get_src(c, instr->src[1], 2), &tmu_writes);
 366                 break;
 367         default:
 368                 unreachable("bad image sampler dim");
 369         }
 370
 371         if (nir_intrinsic_image_array(instr)) {
 372                 vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUI,
 373                               ntq_get_src(c, instr->src[1],
 374                                           is_1d ? 1 : 2), &tmu_writes);
 375         }
 376
 377         /* Limit the number of channels returned to both how many the NIR
 378          * instruction writes and how many the instruction could produce.
 379          */
 380         uint32_t instr_return_channels = nir_intrinsic_dest_components(instr);
 381         if (!p1_unpacked.output_type_32_bit)
 382                 instr_return_channels = (instr_return_channels + 1) / 2;
 383
 384         p0_unpacked.return_words_of_texture_data =
 385                 (1 << instr_return_channels) - 1;
 386
 387         uint32_t p0_packed;
 388         V3D41_TMU_CONFIG_PARAMETER_0_pack(NULL,
 389                                           (uint8_t *)&p0_packed,
 390                                           &p0_unpacked);
 391
 392         uint32_t p1_packed;
 393         V3D41_TMU_CONFIG_PARAMETER_1_pack(NULL,
 394                                           (uint8_t *)&p1_packed,
 395                                           &p1_unpacked);
 396
 397         uint32_t p2_packed;
 398         V3D41_TMU_CONFIG_PARAMETER_2_pack(NULL,
 399                                           (uint8_t *)&p2_packed,
 400                                           &p2_unpacked);
 401
 402         /* Load unit number into the high bits of the texture or sampler
 403          * address field, which will be be used by the driver to decide which
 404          * texture to put in the actual address field.
 405          */
 406         p0_packed |= unit << 24;
 407
 408         vir_WRTMUC(c, QUNIFORM_IMAGE_TMU_CONFIG_P0, p0_packed);
 409         if (memcmp(&p1_unpacked, &p1_unpacked_default, sizeof(p1_unpacked)) != 0)
 410                 vir_WRTMUC(c, QUNIFORM_CONSTANT, p1_packed);
 411         if (memcmp(&p2_unpacked, &p2_unpacked_default, sizeof(p2_unpacked)) != 0)
 412                 vir_WRTMUC(c, QUNIFORM_CONSTANT, p2_packed);
 413
 414         /* Emit the data writes for atomics or image store. */
 415         if (instr->intrinsic != nir_intrinsic_image_load &&
 416             !atomic_add_replaced) {
 417                 /* Vector for stores, or first atomic argument */
 418                 struct qreg src[4];
 419                 for (int i = 0; i < nir_intrinsic_src_components(instr, 3); i++) {
 420                         src[i] = ntq_get_src(c, instr->src[3], i);
 421                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUD, src[i],
 422                                       &tmu_writes);
 423                 }
 424
 425                 /* Second atomic argument */
 426                 if (instr->intrinsic ==
 427                     nir_intrinsic_image_atomic_comp_swap) {
 428                         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUD,
 429                                       ntq_get_src(c, instr->src[4], 0),
 430                                       &tmu_writes);
 431                 }
 432         }
 433
 434         if (vir_in_nonuniform_control_flow(c) &&
 435             instr->intrinsic != nir_intrinsic_image_load) {
 436            vir_set_pf(vir_MOV_dest(c, vir_nop_reg(), c->execute),
 437                       V3D_QPU_PF_PUSHZ);
 438         }
 439
 440         vir_TMU_WRITE(c, V3D_QPU_WADDR_TMUSF, ntq_get_src(c, instr->src[1], 0),
 441                       &tmu_writes);
 442
 443         if (vir_in_nonuniform_control_flow(c) &&
 444             instr->intrinsic != nir_intrinsic_image_load) {
 445            struct qinst *last_inst= (struct  qinst *)c->cur_block->instructions.prev;
 446            vir_set_cond(last_inst, V3D_QPU_COND_IFA);
 447         }
 448
 449         vir_emit_thrsw(c);
 450
 451         /* The input FIFO has 16 slots across all threads, so make sure we
 452          * don't overfill our allocation.
 453          */
 454         while (tmu_writes > 16 / c->threads)
 455                 c->threads /= 2;
 456
 457         for (int i = 0; i < 4; i++) {
 458                 if (p0_unpacked.return_words_of_texture_data & (1 << i))
 459                         ntq_store_dest(c, &instr->dest, i, vir_LDTMU(c));
 460         }
 461
 462         if (nir_intrinsic_dest_components(instr) == 0)
 463                 vir_TMUWT(c);
 464
 465         if (instr->intrinsic != nir_intrinsic_image_load)
 466                 c->tmu_dirty_rcl = true;
 467 }