2 * Copyright © 2016-2018 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "v3d_compiler.h"
26 /* We don't do any address packing. */
27 #define __gen_user_data void
28 #define __gen_address_type uint32_t
29 #define __gen_address_offset(reloc) (*reloc)
30 #define __gen_emit_reloc(cl, reloc)
31 #include "cle/v3d_packet_v41_pack.h"
34 vir_TMU_WRITE(struct v3d_compile
*c
, enum v3d_qpu_waddr waddr
, struct qreg val
,
37 /* XXX perf: We should figure out how to merge ALU operations
38 * producing the val with this MOV, when possible.
40 vir_MOV_dest(c
, vir_reg(QFILE_MAGIC
, waddr
), val
);
46 vir_WRTMUC(struct v3d_compile
*c
, enum quniform_contents contents
, uint32_t data
)
48 struct qinst
*inst
= vir_NOP(c
);
49 inst
->qpu
.sig
.wrtmuc
= true;
50 inst
->has_implicit_uniform
= true;
51 inst
->src
[0] = vir_uniform(c
, contents
, data
);
55 v3d40_vir_emit_tex(struct v3d_compile
*c
, nir_tex_instr
*instr
)
57 unsigned unit
= instr
->texture_index
;
59 static const struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked_default
= {
60 .op
= V3D_TMU_OP_REGULAR
,
63 struct V3D41_TMU_CONFIG_PARAMETER_0 p0_unpacked
= {
66 struct V3D41_TMU_CONFIG_PARAMETER_1 p1_unpacked
= {
67 .output_type_32_bit
= (c
->key
->tex
[unit
].return_size
== 32 &&
70 .unnormalized_coordinates
= (instr
->sampler_dim
==
71 GLSL_SAMPLER_DIM_RECT
),
74 struct V3D41_TMU_CONFIG_PARAMETER_2 p2_unpacked
= {
75 .op
= V3D_TMU_OP_REGULAR
,
77 .gather_mode
= instr
->op
== nir_texop_tg4
,
78 .gather_component
= instr
->component
,
80 .coefficient_mode
= instr
->op
== nir_texop_txd
,
83 int non_array_components
= instr
->coord_components
- instr
->is_array
;
86 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
87 switch (instr
->src
[i
].src_type
) {
88 case nir_tex_src_coord
:
89 /* S triggers the lookup, so save it for the end. */
90 s
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
92 if (non_array_components
> 1) {
93 vir_TMU_WRITE(c
, V3D_QPU_WADDR_TMUT
,
94 ntq_get_src(c
, instr
->src
[i
].src
,
97 if (non_array_components
> 2) {
98 vir_TMU_WRITE(c
, V3D_QPU_WADDR_TMUR
,
99 ntq_get_src(c
, instr
->src
[i
].src
,
103 if (instr
->is_array
) {
104 vir_TMU_WRITE(c
, V3D_QPU_WADDR_TMUI
,
105 ntq_get_src(c
, instr
->src
[i
].src
,
106 instr
->coord_components
- 1),
111 case nir_tex_src_bias
:
112 vir_TMU_WRITE(c
, V3D_QPU_WADDR_TMUB
,
113 ntq_get_src(c
, instr
->src
[i
].src
, 0),
117 case nir_tex_src_lod
:
118 vir_TMU_WRITE(c
, V3D_QPU_WADDR_TMUB
,
119 ntq_get_src(c
, instr
->src
[i
].src
, 0),
122 if (instr
->op
!= nir_texop_txf
&&
123 instr
->op
!= nir_texop_tg4
) {
124 p2_unpacked
.disable_autolod
= true;
128 case nir_tex_src_comparator
:
129 vir_TMU_WRITE(c
, V3D_QPU_WADDR_TMUDREF
,
130 ntq_get_src(c
, instr
->src
[i
].src
, 0),
134 case nir_tex_src_offset
: {
135 nir_const_value
*offset
=
136 nir_src_as_const_value(instr
->src
[i
].src
);
138 p2_unpacked
.offset_s
= offset
->i32
[0];
139 if (instr
->coord_components
>= 2)
140 p2_unpacked
.offset_t
= offset
->i32
[1];
141 if (instr
->coord_components
>= 3)
142 p2_unpacked
.offset_r
= offset
->i32
[2];
147 unreachable("unknown texture source");
151 /* Limit the number of channels returned to both how many the NIR
152 * instruction writes and how many the instruction could produce.
154 * XXX perf: Can we also limit to the number of channels that are
155 * actually read by the users of this NIR dest, so that we don't need
156 * to emit unused LDTMUs?
158 uint32_t instr_return_channels
= nir_tex_instr_dest_size(instr
);
159 if (!p1_unpacked
.output_type_32_bit
)
160 instr_return_channels
= (instr_return_channels
+ 1) / 2;
162 p0_unpacked
.return_words_of_texture_data
=
163 (1 << MIN2(instr_return_channels
,
164 c
->key
->tex
[unit
].return_channels
)) - 1;
166 /* Word enables can't ask for more channels than the output type could
167 * provide (2 for f16, 4 for 32-bit).
169 assert(!p1_unpacked
.output_type_32_bit
||
170 p0_unpacked
.return_words_of_texture_data
< (1 << 4));
171 assert(p1_unpacked
.output_type_32_bit
||
172 p0_unpacked
.return_words_of_texture_data
< (1 << 2));
175 V3D41_TMU_CONFIG_PARAMETER_0_pack(NULL
,
176 (uint8_t *)&p0_packed
,
180 V3D41_TMU_CONFIG_PARAMETER_1_pack(NULL
,
181 (uint8_t *)&p1_packed
,
185 V3D41_TMU_CONFIG_PARAMETER_2_pack(NULL
,
186 (uint8_t *)&p2_packed
,
189 /* Load unit number into the high bits of the texture or sampler
190 * address field, which will be be used by the driver to decide which
191 * texture to put in the actual address field.
193 p0_packed
|= unit
<< 24;
194 p1_packed
|= unit
<< 24;
196 vir_WRTMUC(c
, QUNIFORM_TMU_CONFIG_P0
, p0_packed
);
197 /* XXX perf: Can we skip p1 setup for txf ops? */
198 vir_WRTMUC(c
, QUNIFORM_TMU_CONFIG_P1
, p1_packed
);
199 if (memcmp(&p2_unpacked
, &p2_unpacked_default
, sizeof(p2_unpacked
)) != 0)
200 vir_WRTMUC(c
, QUNIFORM_CONSTANT
, p2_packed
);
202 if (instr
->op
== nir_texop_txf
) {
203 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_CUBE
);
204 vir_TMU_WRITE(c
, V3D_QPU_WADDR_TMUSF
, s
, &tmu_writes
);
205 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
206 vir_TMU_WRITE(c
, V3D_QPU_WADDR_TMUSCM
, s
, &tmu_writes
);
208 vir_TMU_WRITE(c
, V3D_QPU_WADDR_TMUS
, s
, &tmu_writes
);
213 /* The input FIFO has 16 slots across all threads, so make sure we
214 * don't overfill our allocation.
216 while (tmu_writes
> 16 / c
->threads
)
219 struct qreg return_values
[4];
220 for (int i
= 0; i
< 4; i
++) {
221 /* Swizzling .zw of an RG texture should give undefined
222 * results, not crash the compiler.
224 if (p0_unpacked
.return_words_of_texture_data
& (1 << i
))
225 return_values
[i
] = vir_LDTMU(c
);
227 return_values
[i
] = c
->undef
;
230 for (int i
= 0; i
< nir_tex_instr_dest_size(instr
); i
++) {
233 if (!p1_unpacked
.output_type_32_bit
) {
234 STATIC_ASSERT(PIPE_SWIZZLE_X
== 0);
235 chan
= return_values
[i
/ 2];
237 /* XXX perf: We should move this unpacking into NIR.
238 * That would give us exposure of these types to NIR
239 * optimization, so that (for example) a repacking of
240 * half-float samples to the half-float render target
241 * could be eliminated.
243 if (nir_alu_type_get_base_type(instr
->dest_type
) ==
245 enum v3d_qpu_input_unpack unpack
;
247 unpack
= V3D_QPU_UNPACK_H
;
249 unpack
= V3D_QPU_UNPACK_L
;
251 chan
= vir_FMOV(c
, chan
);
252 vir_set_unpack(c
->defs
[chan
.index
], 0, unpack
);
254 /* If we're unpacking the low field, shift it
255 * up to the top first.
258 chan
= vir_SHL(c
, chan
,
259 vir_uniform_ui(c
, 16));
262 /* Do proper sign extension to a 32-bit int. */
263 if (nir_alu_type_get_base_type(instr
->dest_type
) ==
265 chan
= vir_ASR(c
, chan
,
266 vir_uniform_ui(c
, 16));
268 chan
= vir_SHR(c
, chan
,
269 vir_uniform_ui(c
, 16));
273 chan
= vir_MOV(c
, return_values
[i
]);
275 ntq_store_dest(c
, &instr
->dest
, i
, chan
);