src/broadcom/compiler/v3d_compiler.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef V3D_COMPILER_H
  25 #define V3D_COMPILER_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "common/v3d_debug.h"
  36 #include "common/v3d_device_info.h"
  37 #include "common/v3d_limits.h"
  38 #include "compiler/nir/nir.h"
  39 #include "util/list.h"
  40 #include "util/u_math.h"
  41
  42 #include "qpu/qpu_instr.h"
  43 #include "pipe/p_state.h"
  44
  45 struct nir_builder;
  46
  47 struct v3d_fs_inputs {
  48         /**
  49          * Array of the meanings of the VPM inputs this shader needs.
  50          *
  51          * It doesn't include those that aren't part of the VPM, like
  52          * point/line coordinates.
  53          */
  54         struct v3d_varying_slot *input_slots;
  55         uint32_t num_inputs;
  56 };
  57
  58 enum qfile {
  59         /** An unused source or destination register. */
  60         QFILE_NULL,
  61
  62         /** A physical register, such as the W coordinate payload. */
  63         QFILE_REG,
  64         /** One of the regsiters for fixed function interactions. */
  65         QFILE_MAGIC,
  66
  67         /**
  68          *  A virtual register, that will be allocated to actual accumulator
  69          * or physical registers later.
  70          */
  71         QFILE_TEMP,
  72         QFILE_UNIF,
  73         QFILE_TLB,
  74         QFILE_TLBU,
  75
  76         /**
  77          * VPM reads use this with an index value to say what part of the VPM
  78          * is being read.
  79          */
  80         QFILE_VPM,
  81
  82         /**
  83          * Stores an immediate value in the index field that will be used
  84          * directly by qpu_load_imm().
  85          */
  86         QFILE_LOAD_IMM,
  87
  88         /**
  89          * Stores an immediate value in the index field that can be turned
  90          * into a small immediate field by qpu_encode_small_immediate().
  91          */
  92         QFILE_SMALL_IMM,
  93 };
  94
  95 /**
  96  * A reference to a QPU register or a virtual temp register.
  97  */
  98 struct qreg {
  99         enum qfile file;
 100         uint32_t index;
 101 };
 102
 103 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
 104 {
 105         return (struct qreg){file, index};
 106 }
 107
 108 static inline struct qreg vir_nop_reg(void)
 109 {
 110         return (struct qreg){QFILE_NULL, 0};
 111 }
 112
 113 /**
 114  * A reference to an actual register at the QPU level, for register
 115  * allocation.
 116  */
 117 struct qpu_reg {
 118         bool magic;
 119         bool smimm;
 120         int index;
 121 };
 122
 123 struct qinst {
 124         /** Entry in qblock->instructions */
 125         struct list_head link;
 126
 127         /**
 128          * The instruction being wrapped.  Its condition codes, pack flags,
 129          * signals, etc. will all be used, with just the register references
 130          * being replaced by the contents of qinst->dst and qinst->src[].
 131          */
 132         struct v3d_qpu_instr qpu;
 133
 134         /* Pre-register-allocation references to src/dst registers */
 135         struct qreg dst;
 136         struct qreg src[3];
 137         bool cond_is_exec_mask;
 138         bool has_implicit_uniform;
 139         bool is_last_thrsw;
 140
 141         /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
 142          * the uncompiled stream it is.
 143          */
 144         int uniform;
 145 };
 146
 147 enum quniform_contents {
 148         /**
 149          * Indicates that a constant 32-bit value is copied from the program's
 150          * uniform contents.
 151          */
 152         QUNIFORM_CONSTANT,
 153         /**
 154          * Indicates that the program's uniform contents are used as an index
 155          * into the GL uniform storage.
 156          */
 157         QUNIFORM_UNIFORM,
 158
 159         /** @{
 160          * Scaling factors from clip coordinates to relative to the viewport
 161          * center.
 162          *
 163          * This is used by the coordinate and vertex shaders to produce the
 164          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 165          * point offsets from the viewport ccenter.
 166          */
 167         QUNIFORM_VIEWPORT_X_SCALE,
 168         QUNIFORM_VIEWPORT_Y_SCALE,
 169         /** @} */
 170
 171         QUNIFORM_VIEWPORT_Z_OFFSET,
 172         QUNIFORM_VIEWPORT_Z_SCALE,
 173
 174         QUNIFORM_USER_CLIP_PLANE,
 175
 176         /**
 177          * A reference to a V3D 3.x texture config parameter 0 uniform.
 178          *
 179          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 180          * defines texture type, miplevels, and such.  It will be found as a
 181          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 182          */
 183         QUNIFORM_TEXTURE_CONFIG_P0_0,
 184         QUNIFORM_TEXTURE_CONFIG_P0_1,
 185         QUNIFORM_TEXTURE_CONFIG_P0_2,
 186         QUNIFORM_TEXTURE_CONFIG_P0_3,
 187         QUNIFORM_TEXTURE_CONFIG_P0_4,
 188         QUNIFORM_TEXTURE_CONFIG_P0_5,
 189         QUNIFORM_TEXTURE_CONFIG_P0_6,
 190         QUNIFORM_TEXTURE_CONFIG_P0_7,
 191         QUNIFORM_TEXTURE_CONFIG_P0_8,
 192         QUNIFORM_TEXTURE_CONFIG_P0_9,
 193         QUNIFORM_TEXTURE_CONFIG_P0_10,
 194         QUNIFORM_TEXTURE_CONFIG_P0_11,
 195         QUNIFORM_TEXTURE_CONFIG_P0_12,
 196         QUNIFORM_TEXTURE_CONFIG_P0_13,
 197         QUNIFORM_TEXTURE_CONFIG_P0_14,
 198         QUNIFORM_TEXTURE_CONFIG_P0_15,
 199         QUNIFORM_TEXTURE_CONFIG_P0_16,
 200         QUNIFORM_TEXTURE_CONFIG_P0_17,
 201         QUNIFORM_TEXTURE_CONFIG_P0_18,
 202         QUNIFORM_TEXTURE_CONFIG_P0_19,
 203         QUNIFORM_TEXTURE_CONFIG_P0_20,
 204         QUNIFORM_TEXTURE_CONFIG_P0_21,
 205         QUNIFORM_TEXTURE_CONFIG_P0_22,
 206         QUNIFORM_TEXTURE_CONFIG_P0_23,
 207         QUNIFORM_TEXTURE_CONFIG_P0_24,
 208         QUNIFORM_TEXTURE_CONFIG_P0_25,
 209         QUNIFORM_TEXTURE_CONFIG_P0_26,
 210         QUNIFORM_TEXTURE_CONFIG_P0_27,
 211         QUNIFORM_TEXTURE_CONFIG_P0_28,
 212         QUNIFORM_TEXTURE_CONFIG_P0_29,
 213         QUNIFORM_TEXTURE_CONFIG_P0_30,
 214         QUNIFORM_TEXTURE_CONFIG_P0_31,
 215         QUNIFORM_TEXTURE_CONFIG_P0_32,
 216
 217         /**
 218          * A reference to a V3D 3.x texture config parameter 1 uniform.
 219          *
 220          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 221          * has the pointer to the indirect texture state.  Our data[] field
 222          * will have a packed p1 value, but the address field will be just
 223          * which texture unit's texture should be referenced.
 224          */
 225         QUNIFORM_TEXTURE_CONFIG_P1,
 226
 227         /* A V3D 4.x texture config parameter.  The high 8 bits will be
 228          * which texture or sampler is being sampled, and the driver must
 229          * replace the address field with the appropriate address.
 230          */
 231         QUNIFORM_TMU_CONFIG_P0,
 232         QUNIFORM_TMU_CONFIG_P1,
 233
 234         QUNIFORM_IMAGE_TMU_CONFIG_P0,
 235
 236         QUNIFORM_TEXTURE_FIRST_LEVEL,
 237
 238         QUNIFORM_TEXTURE_WIDTH,
 239         QUNIFORM_TEXTURE_HEIGHT,
 240         QUNIFORM_TEXTURE_DEPTH,
 241         QUNIFORM_TEXTURE_ARRAY_SIZE,
 242         QUNIFORM_TEXTURE_LEVELS,
 243
 244         QUNIFORM_UBO_ADDR,
 245
 246         QUNIFORM_TEXRECT_SCALE_X,
 247         QUNIFORM_TEXRECT_SCALE_Y,
 248
 249         /* Returns the base offset of the SSBO given by the data value. */
 250         QUNIFORM_SSBO_OFFSET,
 251
 252         /* Returns the size of the SSBO given by the data value. */
 253         QUNIFORM_GET_BUFFER_SIZE,
 254
 255         /* Sizes (in pixels) of a shader image given by the data value. */
 256         QUNIFORM_IMAGE_WIDTH,
 257         QUNIFORM_IMAGE_HEIGHT,
 258         QUNIFORM_IMAGE_DEPTH,
 259         QUNIFORM_IMAGE_ARRAY_SIZE,
 260
 261         QUNIFORM_ALPHA_REF,
 262
 263         /* Number of workgroups passed to glDispatchCompute in the dimension
 264          * selected by the data value.
 265          */
 266         QUNIFORM_NUM_WORK_GROUPS,
 267
 268         /**
 269          * Returns the the offset of the scratch buffer for register spilling.
 270          */
 271         QUNIFORM_SPILL_OFFSET,
 272         QUNIFORM_SPILL_SIZE_PER_THREAD,
 273
 274         /**
 275          * Returns the offset of the shared memory for compute shaders.
 276          *
 277          * This will be accessed using TMU general memory operations, so the
 278          * L2T cache will effectively be the shared memory area.
 279          */
 280         QUNIFORM_SHARED_OFFSET,
 281 };
 282
 283 static inline uint32_t v3d_tmu_config_data_create(uint32_t unit, uint32_t value)
 284 {
 285         return unit << 24 | value;
 286 }
 287
 288 static inline uint32_t v3d_tmu_config_data_get_unit(uint32_t data)
 289 {
 290         return data >> 24;
 291 }
 292
 293 static inline uint32_t v3d_tmu_config_data_get_value(uint32_t data)
 294 {
 295         return data & 0xffffff;
 296 }
 297
 298 struct v3d_varying_slot {
 299         uint8_t slot_and_component;
 300 };
 301
 302 static inline struct v3d_varying_slot
 303 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
 304 {
 305         assert(slot < 255 / 4);
 306         return (struct v3d_varying_slot){ (slot << 2) + component };
 307 }
 308
 309 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
 310 {
 311         return slot.slot_and_component >> 2;
 312 }
 313
 314 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
 315 {
 316         return slot.slot_and_component & 3;
 317 }
 318
 319 struct v3d_ubo_range {
 320         /**
 321          * offset in bytes from the start of the ubo where this range is
 322          * uploaded.
 323          *
 324          * Only set once used is set.
 325          */
 326         uint32_t dst_offset;
 327
 328         /**
 329          * offset in bytes from the start of the gallium uniforms where the
 330          * data comes from.
 331          */
 332         uint32_t src_offset;
 333
 334         /** size in bytes of this ubo range */
 335         uint32_t size;
 336 };
 337
 338 struct v3d_key {
 339         void *shader_state;
 340         struct {
 341                 uint8_t swizzle[4];
 342                 uint8_t return_size;
 343                 uint8_t return_channels;
 344                 bool clamp_s:1;
 345                 bool clamp_t:1;
 346                 bool clamp_r:1;
 347         } tex[V3D_MAX_TEXTURE_SAMPLERS];
 348         uint8_t ucp_enables;
 349 };
 350
 351 struct v3d_fs_key {
 352         struct v3d_key base;
 353         bool depth_enabled;
 354         bool is_points;
 355         bool is_lines;
 356         bool alpha_test;
 357         bool point_coord_upper_left;
 358         bool light_twoside;
 359         bool msaa;
 360         bool sample_coverage;
 361         bool sample_alpha_to_coverage;
 362         bool sample_alpha_to_one;
 363         bool clamp_color;
 364         bool shade_model_flat;
 365         /* Mask of which color render targets are present. */
 366         uint8_t cbufs;
 367         uint8_t swap_color_rb;
 368         /* Mask of which render targets need to be written as 32-bit floats */
 369         uint8_t f32_color_rb;
 370         /* Masks of which render targets need to be written as ints/uints.
 371          * Used by gallium to work around lost information in TGSI.
 372          */
 373         uint8_t int_color_rb;
 374         uint8_t uint_color_rb;
 375         uint8_t alpha_test_func;
 376         uint8_t logicop_func;
 377         uint32_t point_sprite_mask;
 378
 379         struct pipe_rt_blend_state blend;
 380 };
 381
 382 struct v3d_vs_key {
 383         struct v3d_key base;
 384
 385         struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
 386         uint8_t num_fs_inputs;
 387
 388         bool is_coord;
 389         bool per_vertex_point_size;
 390         bool clamp_color;
 391 };
 392
 393 /** A basic block of VIR intructions. */
 394 struct qblock {
 395         struct list_head link;
 396
 397         struct list_head instructions;
 398
 399         struct set *predecessors;
 400         struct qblock *successors[2];
 401
 402         int index;
 403
 404         /* Instruction IPs for the first and last instruction of the block.
 405          * Set by qpu_schedule.c.
 406          */
 407         uint32_t start_qpu_ip;
 408         uint32_t end_qpu_ip;
 409
 410         /* Instruction IP for the branch instruction of the block.  Set by
 411          * qpu_schedule.c.
 412          */
 413         uint32_t branch_qpu_ip;
 414
 415         /** Offset within the uniform stream at the start of the block. */
 416         uint32_t start_uniform;
 417         /** Offset within the uniform stream of the branch instruction */
 418         uint32_t branch_uniform;
 419
 420         /** @{ used by v3d_vir_live_variables.c */
 421         BITSET_WORD *def;
 422         BITSET_WORD *use;
 423         BITSET_WORD *live_in;
 424         BITSET_WORD *live_out;
 425         int start_ip, end_ip;
 426         /** @} */
 427 };
 428
 429 /** Which util/list.h add mode we should use when inserting an instruction. */
 430 enum vir_cursor_mode {
 431         vir_cursor_add,
 432         vir_cursor_addtail,
 433 };
 434
 435 /**
 436  * Tracking structure for where new instructions should be inserted.  Create
 437  * with one of the vir_after_inst()-style helper functions.
 438  *
 439  * This does not protect against removal of the block or instruction, so we
 440  * have an assert in instruction removal to try to catch it.
 441  */
 442 struct vir_cursor {
 443         enum vir_cursor_mode mode;
 444         struct list_head *link;
 445 };
 446
 447 static inline struct vir_cursor
 448 vir_before_inst(struct qinst *inst)
 449 {
 450         return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
 451 }
 452
 453 static inline struct vir_cursor
 454 vir_after_inst(struct qinst *inst)
 455 {
 456         return (struct vir_cursor){ vir_cursor_add, &inst->link };
 457 }
 458
 459 static inline struct vir_cursor
 460 vir_before_block(struct qblock *block)
 461 {
 462         return (struct vir_cursor){ vir_cursor_add, &block->instructions };
 463 }
 464
 465 static inline struct vir_cursor
 466 vir_after_block(struct qblock *block)
 467 {
 468         return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
 469 }
 470
 471 /**
 472  * Compiler state saved across compiler invocations, for any expensive global
 473  * setup.
 474  */
 475 struct v3d_compiler {
 476         const struct v3d_device_info *devinfo;
 477         struct ra_regs *regs;
 478         unsigned int reg_class_phys[3];
 479         unsigned int reg_class_phys_or_acc[3];
 480 };
 481
 482 struct v3d_compile {
 483         const struct v3d_device_info *devinfo;
 484         nir_shader *s;
 485         nir_function_impl *impl;
 486         struct exec_list *cf_node_list;
 487         const struct v3d_compiler *compiler;
 488
 489         void (*debug_output)(const char *msg,
 490                              void *debug_output_data);
 491         void *debug_output_data;
 492
 493         /**
 494          * Mapping from nir_register * or nir_ssa_def * to array of struct
 495          * qreg for the values.
 496          */
 497         struct hash_table *def_ht;
 498
 499         /* For each temp, the instruction generating its value. */
 500         struct qinst **defs;
 501         uint32_t defs_array_size;
 502
 503         /**
 504          * Inputs to the shader, arranged by TGSI declaration order.
 505          *
 506          * Not all fragment shader QFILE_VARY reads are present in this array.
 507          */
 508         struct qreg *inputs;
 509         struct qreg *outputs;
 510         bool msaa_per_sample_output;
 511         struct qreg color_reads[V3D_MAX_SAMPLES];
 512         struct qreg sample_colors[V3D_MAX_SAMPLES];
 513         uint32_t inputs_array_size;
 514         uint32_t outputs_array_size;
 515         uint32_t uniforms_array_size;
 516
 517         /* Booleans for whether the corresponding QFILE_VARY[i] is
 518          * flat-shaded.  This includes gl_FragColor flat-shading, which is
 519          * customized based on the shademodel_flat shader key.
 520          */
 521         uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 522
 523         uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 524
 525         uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 526
 527         bool uses_center_w;
 528         bool writes_z;
 529
 530         struct v3d_ubo_range *ubo_ranges;
 531         bool *ubo_range_used;
 532         uint32_t ubo_ranges_array_size;
 533         /** Number of uniform areas tracked in ubo_ranges. */
 534         uint32_t num_ubo_ranges;
 535         uint32_t next_ubo_dst_offset;
 536
 537         /* State for whether we're executing on each channel currently.  0 if
 538          * yes, otherwise a block number + 1 that the channel jumped to.
 539          */
 540         struct qreg execute;
 541
 542         struct qreg line_x, point_x, point_y;
 543
 544         /**
 545          * Instance ID, which comes in before the vertex attribute payload if
 546          * the shader record requests it.
 547          */
 548         struct qreg iid;
 549
 550         /**
 551          * Vertex ID, which comes in before the vertex attribute payload
 552          * (after Instance ID) if the shader record requests it.
 553          */
 554         struct qreg vid;
 555
 556         /* Fragment shader payload regs. */
 557         struct qreg payload_w, payload_w_centroid, payload_z;
 558
 559         struct qreg cs_payload[2];
 560         struct qreg cs_shared_offset;
 561         int local_invocation_index_bits;
 562
 563         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
 564         uint32_t num_vpm_writes;
 565
 566         /* Size in bytes of registers that have been spilled. This is how much
 567          * space needs to be available in the spill BO per thread per QPU.
 568          */
 569         uint32_t spill_size;
 570         /* Shader-db stats */
 571         uint32_t spills, fills, loops;
 572         /**
 573          * Register spilling's per-thread base address, shared between each
 574          * spill/fill's addressing calculations.
 575          */
 576         struct qreg spill_base;
 577         /* Bit vector of which temps may be spilled */
 578         BITSET_WORD *spillable;
 579
 580         /**
 581          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 582          *
 583          * This includes those that aren't part of the VPM varyings, like
 584          * point/line coordinates.
 585          */
 586         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 587
 588         /**
 589          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 590          * of the output is.  Used to emit from the VS in the order that the
 591          * FS needs.
 592          */
 593         struct v3d_varying_slot *output_slots;
 594
 595         struct pipe_shader_state *shader_state;
 596         struct v3d_key *key;
 597         struct v3d_fs_key *fs_key;
 598         struct v3d_vs_key *vs_key;
 599
 600         /* Live ranges of temps. */
 601         int *temp_start, *temp_end;
 602         bool live_intervals_valid;
 603
 604         uint32_t *uniform_data;
 605         enum quniform_contents *uniform_contents;
 606         uint32_t uniform_array_size;
 607         uint32_t num_uniforms;
 608         uint32_t num_outputs;
 609         uint32_t output_position_index;
 610         nir_variable *output_color_var[4];
 611         uint32_t output_point_size_index;
 612         uint32_t output_sample_mask_index;
 613
 614         struct qreg undef;
 615         uint32_t num_temps;
 616
 617         struct vir_cursor cursor;
 618         struct list_head blocks;
 619         int next_block_index;
 620         struct qblock *cur_block;
 621         struct qblock *loop_cont_block;
 622         struct qblock *loop_break_block;
 623
 624         uint64_t *qpu_insts;
 625         uint32_t qpu_inst_count;
 626         uint32_t qpu_inst_size;
 627
 628         /* For the FS, the number of varying inputs not counting the
 629          * point/line varyings payload
 630          */
 631         uint32_t num_inputs;
 632
 633         /**
 634          * Number of inputs from num_inputs remaining to be queued to the read
 635          * FIFO in the VS/CS.
 636          */
 637         uint32_t num_inputs_remaining;
 638
 639         /* Number of inputs currently in the read FIFO for the VS/CS */
 640         uint32_t num_inputs_in_fifo;
 641
 642         /** Next offset in the VPM to read from in the VS/CS */
 643         uint32_t vpm_read_offset;
 644
 645         uint32_t program_id;
 646         uint32_t variant_id;
 647
 648         /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
 649          * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
 650          * limiting ourselves to the part of the physical reg space.
 651          *
 652          * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x.  On
 653          * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
 654          * physical reg space in half.
 655          */
 656         uint8_t threads;
 657         struct qinst *last_thrsw;
 658         bool last_thrsw_at_top_level;
 659
 660         bool failed;
 661 };
 662
 663 struct v3d_uniform_list {
 664         enum quniform_contents *contents;
 665         uint32_t *data;
 666         uint32_t count;
 667 };
 668
 669 struct v3d_prog_data {
 670         struct v3d_uniform_list uniforms;
 671
 672         struct v3d_ubo_range *ubo_ranges;
 673         uint32_t num_ubo_ranges;
 674         uint32_t ubo_size;
 675         uint32_t spill_size;
 676
 677         uint8_t num_inputs;
 678         uint8_t threads;
 679
 680         /* For threads > 1, whether the program should be dispatched in the
 681          * after-final-THRSW state.
 682          */
 683         bool single_seg;
 684 };
 685
 686 struct v3d_vs_prog_data {
 687         struct v3d_prog_data base;
 688
 689         bool uses_iid, uses_vid;
 690
 691         /* Number of components read from each vertex attribute. */
 692         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
 693
 694         /* Total number of components read, for the shader state record. */
 695         uint32_t vpm_input_size;
 696
 697         /* Total number of components written, for the shader state record. */
 698         uint32_t vpm_output_size;
 699
 700         /* Set if there should be separate VPM segments for input and output.
 701          * If unset, vpm_input_size will be 0.
 702          */
 703         bool separate_segments;
 704
 705         /* Value to be programmed in VCM_CACHE_SIZE. */
 706         uint8_t vcm_cache_size;
 707 };
 708
 709 struct v3d_fs_prog_data {
 710         struct v3d_prog_data base;
 711
 712         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 713
 714         /* Array of flat shade flags.
 715          *
 716          * Each entry is only 24 bits (high 8 bits 0), to match the hardware
 717          * packet layout.
 718          */
 719         uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 720
 721         uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 722
 723         uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 724
 725         bool writes_z;
 726         bool disable_ez;
 727         bool uses_center_w;
 728 };
 729
 730 /* Special nir_load_input intrinsic index for loading the current TLB
 731  * destination color.
 732  */
 733 #define V3D_NIR_TLB_COLOR_READ_INPUT            2000000000
 734
 735 #define V3D_NIR_MS_MASK_OUTPUT                  2000000000
 736
 737 extern const nir_shader_compiler_options v3d_nir_options;
 738
 739 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
 740 void v3d_compiler_free(const struct v3d_compiler *compiler);
 741 void v3d_optimize_nir(struct nir_shader *s);
 742
 743 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
 744                       struct v3d_key *key,
 745                       struct v3d_prog_data **prog_data,
 746                       nir_shader *s,
 747                       void (*debug_output)(const char *msg,
 748                                            void *debug_output_data),
 749                       void *debug_output_data,
 750                       int program_id, int variant_id,
 751                       uint32_t *final_assembly_size);
 752
 753 void v3d_nir_to_vir(struct v3d_compile *c);
 754
 755 void vir_compile_destroy(struct v3d_compile *c);
 756 const char *vir_get_stage_name(struct v3d_compile *c);
 757 struct qblock *vir_new_block(struct v3d_compile *c);
 758 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
 759 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 760 struct qblock *vir_entry_block(struct v3d_compile *c);
 761 struct qblock *vir_exit_block(struct v3d_compile *c);
 762 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
 763                            struct qreg src0, struct qreg src1);
 764 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
 765                            struct qreg src0, struct qreg src1);
 766 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
 767 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
 768 struct qreg vir_uniform(struct v3d_compile *c,
 769                         enum quniform_contents contents,
 770                         uint32_t data);
 771 void vir_schedule_instructions(struct v3d_compile *c);
 772 struct v3d_qpu_instr v3d_qpu_nop(void);
 773
 774 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
 775 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
 776 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
 777 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
 778 void vir_set_uf(struct qinst *inst, enum v3d_qpu_uf uf);
 779 void vir_set_unpack(struct qinst *inst, int src,
 780                     enum v3d_qpu_input_unpack unpack);
 781
 782 struct qreg vir_get_temp(struct v3d_compile *c);
 783 void vir_emit_last_thrsw(struct v3d_compile *c);
 784 void vir_calculate_live_intervals(struct v3d_compile *c);
 785 bool vir_has_implicit_uniform(struct qinst *inst);
 786 int vir_get_implicit_uniform_src(struct qinst *inst);
 787 int vir_get_non_sideband_nsrc(struct qinst *inst);
 788 int vir_get_nsrc(struct qinst *inst);
 789 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
 790 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
 791 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
 792 bool vir_is_raw_mov(struct qinst *inst);
 793 bool vir_is_tex(struct qinst *inst);
 794 bool vir_is_add(struct qinst *inst);
 795 bool vir_is_mul(struct qinst *inst);
 796 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
 797 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
 798 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
 799 uint8_t vir_channels_written(struct qinst *inst);
 800 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
 801 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
 802                     struct qreg result);
 803 void vir_emit_thrsw(struct v3d_compile *c);
 804
 805 void vir_dump(struct v3d_compile *c);
 806 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
 807 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
 808
 809 void vir_validate(struct v3d_compile *c);
 810
 811 void vir_optimize(struct v3d_compile *c);
 812 bool vir_opt_algebraic(struct v3d_compile *c);
 813 bool vir_opt_constant_folding(struct v3d_compile *c);
 814 bool vir_opt_copy_propagate(struct v3d_compile *c);
 815 bool vir_opt_dead_code(struct v3d_compile *c);
 816 bool vir_opt_peephole_sf(struct v3d_compile *c);
 817 bool vir_opt_small_immediates(struct v3d_compile *c);
 818 bool vir_opt_vpm(struct v3d_compile *c);
 819 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
 820 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
 821 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
 822 void v3d_nir_lower_image_load_store(nir_shader *s);
 823 void vir_lower_uniforms(struct v3d_compile *c);
 824
 825 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
 826 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
 827 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 828 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 829 void v3d40_vir_emit_image_load_store(struct v3d_compile *c,
 830                                      nir_intrinsic_instr *instr);
 831
 832 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
 833 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
 834 void qpu_validate(struct v3d_compile *c);
 835 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
 836 bool vir_init_reg_sets(struct v3d_compiler *compiler);
 837
 838 bool v3d_gl_format_is_return_32(GLenum format);
 839
 840 static inline bool
 841 quniform_contents_is_texture_p0(enum quniform_contents contents)
 842 {
 843         return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
 844                 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
 845                             V3D_MAX_TEXTURE_SAMPLERS));
 846 }
 847
 848 static inline struct qreg
 849 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
 850 {
 851         return vir_uniform(c, QUNIFORM_CONSTANT, ui);
 852 }
 853
 854 static inline struct qreg
 855 vir_uniform_f(struct v3d_compile *c, float f)
 856 {
 857         return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 858 }
 859
 860 #define VIR_ALU0(name, vir_inst, op)                                     \
 861 static inline struct qreg                                                \
 862 vir_##name(struct v3d_compile *c)                                        \
 863 {                                                                        \
 864         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 865                                         c->undef, c->undef));            \
 866 }                                                                        \
 867 static inline struct qinst *                                             \
 868 vir_##name##_dest(struct v3d_compile *c, struct qreg dest)               \
 869 {                                                                        \
 870         return vir_emit_nondef(c, vir_inst(op, dest,                     \
 871                                            c->undef, c->undef));         \
 872 }
 873
 874 #define VIR_ALU1(name, vir_inst, op)                                     \
 875 static inline struct qreg                                                \
 876 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 877 {                                                                        \
 878         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 879                                         a, c->undef));                   \
 880 }                                                                        \
 881 static inline struct qinst *                                             \
 882 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 883                   struct qreg a)                                         \
 884 {                                                                        \
 885         return vir_emit_nondef(c, vir_inst(op, dest, a,          \
 886                                            c->undef));                   \
 887 }
 888
 889 #define VIR_ALU2(name, vir_inst, op)                                       \
 890 static inline struct qreg                                                \
 891 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)          \
 892 {                                                                        \
 893         return vir_emit_def(c, vir_inst(op, c->undef, a, b));    \
 894 }                                                                        \
 895 static inline struct qinst *                                             \
 896 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 897                   struct qreg a, struct qreg b)                          \
 898 {                                                                        \
 899         return vir_emit_nondef(c, vir_inst(op, dest, a, b));     \
 900 }
 901
 902 #define VIR_NODST_0(name, vir_inst, op)                                 \
 903 static inline struct qinst *                                            \
 904 vir_##name(struct v3d_compile *c)                                       \
 905 {                                                                       \
 906         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 907                                            c->undef, c->undef));        \
 908 }
 909
 910 #define VIR_NODST_1(name, vir_inst, op)                                               \
 911 static inline struct qinst *                                            \
 912 vir_##name(struct v3d_compile *c, struct qreg a)                        \
 913 {                                                                       \
 914         return vir_emit_nondef(c, vir_inst(op, c->undef,        \
 915                                            a, c->undef));               \
 916 }
 917
 918 #define VIR_NODST_2(name, vir_inst, op)                                               \
 919 static inline struct qinst *                                            \
 920 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)         \
 921 {                                                                       \
 922         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 923                                            a, b));                      \
 924 }
 925
 926 #define VIR_SFU(name)                                                      \
 927 static inline struct qreg                                                \
 928 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 929 {                                                                        \
 930         if (c->devinfo->ver >= 41) {                                     \
 931                 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name,    \
 932                                                     c->undef,            \
 933                                                     a, c->undef));       \
 934         } else {                                                         \
 935                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 936                 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 937         }                                                                \
 938 }                                                                        \
 939 static inline struct qinst *                                             \
 940 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 941                   struct qreg a)                                         \
 942 {                                                                        \
 943         if (c->devinfo->ver >= 41) {                                     \
 944                 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
 945                                                        dest,             \
 946                                                        a, c->undef));    \
 947         } else {                                                         \
 948                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 949                 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 950         }                                                                \
 951 }
 952
 953 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
 954 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
 955 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
 956 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
 957 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
 958 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
 959 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
 960 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
 961 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
 962 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
 963 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
 964
 965 VIR_A_ALU2(FADD)
 966 VIR_A_ALU2(VFPACK)
 967 VIR_A_ALU2(FSUB)
 968 VIR_A_ALU2(FMIN)
 969 VIR_A_ALU2(FMAX)
 970
 971 VIR_A_ALU2(ADD)
 972 VIR_A_ALU2(SUB)
 973 VIR_A_ALU2(SHL)
 974 VIR_A_ALU2(SHR)
 975 VIR_A_ALU2(ASR)
 976 VIR_A_ALU2(ROR)
 977 VIR_A_ALU2(MIN)
 978 VIR_A_ALU2(MAX)
 979 VIR_A_ALU2(UMIN)
 980 VIR_A_ALU2(UMAX)
 981 VIR_A_ALU2(AND)
 982 VIR_A_ALU2(OR)
 983 VIR_A_ALU2(XOR)
 984 VIR_A_ALU2(VADD)
 985 VIR_A_ALU2(VSUB)
 986 VIR_A_NODST_2(STVPMV)
 987 VIR_A_ALU1(NOT)
 988 VIR_A_ALU1(NEG)
 989 VIR_A_ALU1(FLAPUSH)
 990 VIR_A_ALU1(FLBPUSH)
 991 VIR_A_ALU1(FLPOP)
 992 VIR_A_ALU1(SETMSF)
 993 VIR_A_ALU1(SETREVF)
 994 VIR_A_ALU0(TIDX)
 995 VIR_A_ALU0(EIDX)
 996 VIR_A_ALU1(LDVPMV_IN)
 997 VIR_A_ALU1(LDVPMV_OUT)
 998 VIR_A_ALU0(TMUWT)
 999
1000 VIR_A_ALU0(FXCD)
1001 VIR_A_ALU0(XCD)
1002 VIR_A_ALU0(FYCD)
1003 VIR_A_ALU0(YCD)
1004 VIR_A_ALU0(MSF)
1005 VIR_A_ALU0(REVF)
1006 VIR_A_ALU0(BARRIERID)
1007 VIR_A_NODST_1(VPMSETUP)
1008 VIR_A_NODST_0(VPMWT)
1009 VIR_A_ALU2(FCMP)
1010 VIR_A_ALU2(VFMAX)
1011
1012 VIR_A_ALU1(FROUND)
1013 VIR_A_ALU1(FTOIN)
1014 VIR_A_ALU1(FTRUNC)
1015 VIR_A_ALU1(FTOIZ)
1016 VIR_A_ALU1(FFLOOR)
1017 VIR_A_ALU1(FTOUZ)
1018 VIR_A_ALU1(FCEIL)
1019 VIR_A_ALU1(FTOC)
1020
1021 VIR_A_ALU1(FDX)
1022 VIR_A_ALU1(FDY)
1023
1024 VIR_A_ALU1(ITOF)
1025 VIR_A_ALU1(CLZ)
1026 VIR_A_ALU1(UTOF)
1027
1028 VIR_M_ALU2(UMUL24)
1029 VIR_M_ALU2(FMUL)
1030 VIR_M_ALU2(SMUL24)
1031 VIR_M_NODST_2(MULTOP)
1032
1033 VIR_M_ALU1(MOV)
1034 VIR_M_ALU1(FMOV)
1035
1036 VIR_SFU(RECIP)
1037 VIR_SFU(RSQRT)
1038 VIR_SFU(EXP)
1039 VIR_SFU(LOG)
1040 VIR_SFU(SIN)
1041 VIR_SFU(RSQRT2)
1042
1043 static inline struct qinst *
1044 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1045              struct qreg dest, struct qreg src)
1046 {
1047         struct qinst *mov = vir_MOV_dest(c, dest, src);
1048         vir_set_cond(mov, cond);
1049         return mov;
1050 }
1051
1052 static inline struct qreg
1053 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1054         struct qreg src0, struct qreg src1)
1055 {
1056         struct qreg t = vir_get_temp(c);
1057         vir_MOV_dest(c, t, src1);
1058         vir_MOV_cond(c, cond, t, src0);
1059         return t;
1060 }
1061
1062 static inline struct qinst *
1063 vir_NOP(struct v3d_compile *c)
1064 {
1065         return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1066                                                c->undef, c->undef, c->undef));
1067 }
1068
1069 static inline struct qreg
1070 vir_LDTMU(struct v3d_compile *c)
1071 {
1072         if (c->devinfo->ver >= 41) {
1073                 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1074                                                    c->undef, c->undef);
1075                 ldtmu->qpu.sig.ldtmu = true;
1076
1077                 return vir_emit_def(c, ldtmu);
1078         } else {
1079                 vir_NOP(c)->qpu.sig.ldtmu = true;
1080                 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
1081         }
1082 }
1083
1084 static inline struct qreg
1085 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1086 {
1087         vir_MULTOP(c, src0, src1);
1088         return vir_UMUL24(c, src0, src1);
1089 }
1090
1091 /*
1092 static inline struct qreg
1093 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1094 {
1095         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1096                                         vir_reg(QFILE_LOAD_IMM, val), c->undef));
1097 }
1098
1099 static inline struct qreg
1100 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1101 {
1102         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1103                                         vir_reg(QFILE_LOAD_IMM, val),
1104                                         c->undef));
1105 }
1106 static inline struct qreg
1107 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1108 {
1109         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1110                                         vir_reg(QFILE_LOAD_IMM, val),
1111                                         c->undef));
1112 }
1113 */
1114
1115 static inline struct qinst *
1116 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1117 {
1118         /* The actual uniform_data value will be set at scheduling time */
1119         return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
1120 }
1121
1122 #define vir_for_each_block(block, c)                                    \
1123         list_for_each_entry(struct qblock, block, &c->blocks, link)
1124
1125 #define vir_for_each_block_rev(block, c)                                \
1126         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1127
1128 /* Loop over the non-NULL members of the successors array. */
1129 #define vir_for_each_successor(succ, block)                             \
1130         for (struct qblock *succ = block->successors[0];                \
1131              succ != NULL;                                              \
1132              succ = (succ == block->successors[1] ? NULL :              \
1133                      block->successors[1]))
1134
1135 #define vir_for_each_inst(inst, block)                                  \
1136         list_for_each_entry(struct qinst, inst, &block->instructions, link)
1137
1138 #define vir_for_each_inst_rev(inst, block)                                  \
1139         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1140
1141 #define vir_for_each_inst_safe(inst, block)                             \
1142         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1143
1144 #define vir_for_each_inst_inorder(inst, c)                              \
1145         vir_for_each_block(_block, c)                                   \
1146                 vir_for_each_inst(inst, _block)
1147
1148 #endif /* V3D_COMPILER_H */