src/broadcom/compiler/v3d_compiler.h

   1 /*
   2  * Copyright © 2016 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef V3D_COMPILER_H
  25 #define V3D_COMPILER_H
  26
  27 #include <assert.h>
  28 #include <stdio.h>
  29 #include <stdlib.h>
  30 #include <stdbool.h>
  31 #include <stdint.h>
  32 #include <string.h>
  33
  34 #include "util/macros.h"
  35 #include "common/v3d_debug.h"
  36 #include "common/v3d_device_info.h"
  37 #include "compiler/nir/nir.h"
  38 #include "util/list.h"
  39 #include "util/u_math.h"
  40
  41 #include "qpu/qpu_instr.h"
  42 #include "pipe/p_state.h"
  43
  44 #define V3D_MAX_TEXTURE_SAMPLERS 32
  45 #define V3D_MAX_SAMPLES 4
  46 #define V3D_MAX_FS_INPUTS 64
  47 #define V3D_MAX_VS_INPUTS 64
  48
  49 struct nir_builder;
  50
  51 struct v3d_fs_inputs {
  52         /**
  53          * Array of the meanings of the VPM inputs this shader needs.
  54          *
  55          * It doesn't include those that aren't part of the VPM, like
  56          * point/line coordinates.
  57          */
  58         struct v3d_varying_slot *input_slots;
  59         uint32_t num_inputs;
  60 };
  61
  62 enum qfile {
  63         /** An unused source or destination register. */
  64         QFILE_NULL,
  65
  66         /** A physical register, such as the W coordinate payload. */
  67         QFILE_REG,
  68         /** One of the regsiters for fixed function interactions. */
  69         QFILE_MAGIC,
  70
  71         /**
  72          *  A virtual register, that will be allocated to actual accumulator
  73          * or physical registers later.
  74          */
  75         QFILE_TEMP,
  76         QFILE_UNIF,
  77         QFILE_TLB,
  78         QFILE_TLBU,
  79
  80         /**
  81          * VPM reads use this with an index value to say what part of the VPM
  82          * is being read.
  83          */
  84         QFILE_VPM,
  85
  86         /**
  87          * Stores an immediate value in the index field that will be used
  88          * directly by qpu_load_imm().
  89          */
  90         QFILE_LOAD_IMM,
  91
  92         /**
  93          * Stores an immediate value in the index field that can be turned
  94          * into a small immediate field by qpu_encode_small_immediate().
  95          */
  96         QFILE_SMALL_IMM,
  97 };
  98
  99 /**
 100  * A reference to a QPU register or a virtual temp register.
 101  */
 102 struct qreg {
 103         enum qfile file;
 104         uint32_t index;
 105 };
 106
 107 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
 108 {
 109         return (struct qreg){file, index};
 110 }
 111
 112 /**
 113  * A reference to an actual register at the QPU level, for register
 114  * allocation.
 115  */
 116 struct qpu_reg {
 117         bool magic;
 118         bool smimm;
 119         int index;
 120 };
 121
 122 struct qinst {
 123         /** Entry in qblock->instructions */
 124         struct list_head link;
 125
 126         /**
 127          * The instruction being wrapped.  Its condition codes, pack flags,
 128          * signals, etc. will all be used, with just the register references
 129          * being replaced by the contents of qinst->dst and qinst->src[].
 130          */
 131         struct v3d_qpu_instr qpu;
 132
 133         /* Pre-register-allocation references to src/dst registers */
 134         struct qreg dst;
 135         struct qreg src[3];
 136         bool cond_is_exec_mask;
 137         bool has_implicit_uniform;
 138         bool is_last_thrsw;
 139
 140         /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
 141          * the uncompiled stream it is.
 142          */
 143         int uniform;
 144 };
 145
 146 enum quniform_contents {
 147         /**
 148          * Indicates that a constant 32-bit value is copied from the program's
 149          * uniform contents.
 150          */
 151         QUNIFORM_CONSTANT,
 152         /**
 153          * Indicates that the program's uniform contents are used as an index
 154          * into the GL uniform storage.
 155          */
 156         QUNIFORM_UNIFORM,
 157
 158         /** @{
 159          * Scaling factors from clip coordinates to relative to the viewport
 160          * center.
 161          *
 162          * This is used by the coordinate and vertex shaders to produce the
 163          * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
 164          * point offsets from the viewport ccenter.
 165          */
 166         QUNIFORM_VIEWPORT_X_SCALE,
 167         QUNIFORM_VIEWPORT_Y_SCALE,
 168         /** @} */
 169
 170         QUNIFORM_VIEWPORT_Z_OFFSET,
 171         QUNIFORM_VIEWPORT_Z_SCALE,
 172
 173         QUNIFORM_USER_CLIP_PLANE,
 174
 175         /**
 176          * A reference to a V3D 3.x texture config parameter 0 uniform.
 177          *
 178          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 179          * defines texture type, miplevels, and such.  It will be found as a
 180          * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
 181          */
 182         QUNIFORM_TEXTURE_CONFIG_P0_0,
 183         QUNIFORM_TEXTURE_CONFIG_P0_1,
 184         QUNIFORM_TEXTURE_CONFIG_P0_2,
 185         QUNIFORM_TEXTURE_CONFIG_P0_3,
 186         QUNIFORM_TEXTURE_CONFIG_P0_4,
 187         QUNIFORM_TEXTURE_CONFIG_P0_5,
 188         QUNIFORM_TEXTURE_CONFIG_P0_6,
 189         QUNIFORM_TEXTURE_CONFIG_P0_7,
 190         QUNIFORM_TEXTURE_CONFIG_P0_8,
 191         QUNIFORM_TEXTURE_CONFIG_P0_9,
 192         QUNIFORM_TEXTURE_CONFIG_P0_10,
 193         QUNIFORM_TEXTURE_CONFIG_P0_11,
 194         QUNIFORM_TEXTURE_CONFIG_P0_12,
 195         QUNIFORM_TEXTURE_CONFIG_P0_13,
 196         QUNIFORM_TEXTURE_CONFIG_P0_14,
 197         QUNIFORM_TEXTURE_CONFIG_P0_15,
 198         QUNIFORM_TEXTURE_CONFIG_P0_16,
 199         QUNIFORM_TEXTURE_CONFIG_P0_17,
 200         QUNIFORM_TEXTURE_CONFIG_P0_18,
 201         QUNIFORM_TEXTURE_CONFIG_P0_19,
 202         QUNIFORM_TEXTURE_CONFIG_P0_20,
 203         QUNIFORM_TEXTURE_CONFIG_P0_21,
 204         QUNIFORM_TEXTURE_CONFIG_P0_22,
 205         QUNIFORM_TEXTURE_CONFIG_P0_23,
 206         QUNIFORM_TEXTURE_CONFIG_P0_24,
 207         QUNIFORM_TEXTURE_CONFIG_P0_25,
 208         QUNIFORM_TEXTURE_CONFIG_P0_26,
 209         QUNIFORM_TEXTURE_CONFIG_P0_27,
 210         QUNIFORM_TEXTURE_CONFIG_P0_28,
 211         QUNIFORM_TEXTURE_CONFIG_P0_29,
 212         QUNIFORM_TEXTURE_CONFIG_P0_30,
 213         QUNIFORM_TEXTURE_CONFIG_P0_31,
 214         QUNIFORM_TEXTURE_CONFIG_P0_32,
 215
 216         /**
 217          * A reference to a V3D 3.x texture config parameter 1 uniform.
 218          *
 219          * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
 220          * has the pointer to the indirect texture state.  Our data[] field
 221          * will have a packed p1 value, but the address field will be just
 222          * which texture unit's texture should be referenced.
 223          */
 224         QUNIFORM_TEXTURE_CONFIG_P1,
 225
 226         /* A V3D 4.x texture config parameter.  The high 8 bits will be
 227          * which texture or sampler is being sampled, and the driver must
 228          * replace the address field with the appropriate address.
 229          */
 230         QUNIFORM_TMU_CONFIG_P0,
 231         QUNIFORM_TMU_CONFIG_P1,
 232
 233         QUNIFORM_TEXTURE_FIRST_LEVEL,
 234
 235         QUNIFORM_TEXTURE_WIDTH,
 236         QUNIFORM_TEXTURE_HEIGHT,
 237         QUNIFORM_TEXTURE_DEPTH,
 238         QUNIFORM_TEXTURE_ARRAY_SIZE,
 239         QUNIFORM_TEXTURE_LEVELS,
 240
 241         QUNIFORM_UBO_ADDR,
 242
 243         QUNIFORM_TEXRECT_SCALE_X,
 244         QUNIFORM_TEXRECT_SCALE_Y,
 245
 246         QUNIFORM_ALPHA_REF,
 247
 248         /**
 249          * Returns the the offset of the scratch buffer for register spilling.
 250          */
 251         QUNIFORM_SPILL_OFFSET,
 252         QUNIFORM_SPILL_SIZE_PER_THREAD,
 253 };
 254
 255 struct v3d_varying_slot {
 256         uint8_t slot_and_component;
 257 };
 258
 259 static inline struct v3d_varying_slot
 260 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
 261 {
 262         assert(slot < 255 / 4);
 263         return (struct v3d_varying_slot){ (slot << 2) + component };
 264 }
 265
 266 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
 267 {
 268         return slot.slot_and_component >> 2;
 269 }
 270
 271 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
 272 {
 273         return slot.slot_and_component & 3;
 274 }
 275
 276 struct v3d_ubo_range {
 277         /**
 278          * offset in bytes from the start of the ubo where this range is
 279          * uploaded.
 280          *
 281          * Only set once used is set.
 282          */
 283         uint32_t dst_offset;
 284
 285         /**
 286          * offset in bytes from the start of the gallium uniforms where the
 287          * data comes from.
 288          */
 289         uint32_t src_offset;
 290
 291         /** size in bytes of this ubo range */
 292         uint32_t size;
 293 };
 294
 295 struct v3d_key {
 296         void *shader_state;
 297         struct {
 298                 uint8_t swizzle[4];
 299                 uint8_t return_size;
 300                 uint8_t return_channels;
 301                 unsigned compare_mode:1;
 302                 unsigned compare_func:3;
 303                 bool clamp_s:1;
 304                 bool clamp_t:1;
 305                 bool clamp_r:1;
 306         } tex[V3D_MAX_TEXTURE_SAMPLERS];
 307         uint8_t ucp_enables;
 308 };
 309
 310 struct v3d_fs_key {
 311         struct v3d_key base;
 312         bool depth_enabled;
 313         bool is_points;
 314         bool is_lines;
 315         bool alpha_test;
 316         bool point_coord_upper_left;
 317         bool light_twoside;
 318         bool msaa;
 319         bool sample_coverage;
 320         bool sample_alpha_to_coverage;
 321         bool sample_alpha_to_one;
 322         bool clamp_color;
 323         bool shade_model_flat;
 324         uint8_t nr_cbufs;
 325         uint8_t swap_color_rb;
 326         /* Mask of which render targets need to be written as 32-bit floats */
 327         uint8_t f32_color_rb;
 328         /* Masks of which render targets need to be written as ints/uints.
 329          * Used by gallium to work around lost information in TGSI.
 330          */
 331         uint8_t int_color_rb;
 332         uint8_t uint_color_rb;
 333         uint8_t alpha_test_func;
 334         uint8_t logicop_func;
 335         uint32_t point_sprite_mask;
 336
 337         struct pipe_rt_blend_state blend;
 338 };
 339
 340 struct v3d_vs_key {
 341         struct v3d_key base;
 342
 343         struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
 344         uint8_t num_fs_inputs;
 345
 346         bool is_coord;
 347         bool per_vertex_point_size;
 348         bool clamp_color;
 349 };
 350
 351 /** A basic block of VIR intructions. */
 352 struct qblock {
 353         struct list_head link;
 354
 355         struct list_head instructions;
 356
 357         struct set *predecessors;
 358         struct qblock *successors[2];
 359
 360         int index;
 361
 362         /* Instruction IPs for the first and last instruction of the block.
 363          * Set by qpu_schedule.c.
 364          */
 365         uint32_t start_qpu_ip;
 366         uint32_t end_qpu_ip;
 367
 368         /* Instruction IP for the branch instruction of the block.  Set by
 369          * qpu_schedule.c.
 370          */
 371         uint32_t branch_qpu_ip;
 372
 373         /** Offset within the uniform stream at the start of the block. */
 374         uint32_t start_uniform;
 375         /** Offset within the uniform stream of the branch instruction */
 376         uint32_t branch_uniform;
 377
 378         /** @{ used by v3d_vir_live_variables.c */
 379         BITSET_WORD *def;
 380         BITSET_WORD *use;
 381         BITSET_WORD *live_in;
 382         BITSET_WORD *live_out;
 383         int start_ip, end_ip;
 384         /** @} */
 385 };
 386
 387 /** Which util/list.h add mode we should use when inserting an instruction. */
 388 enum vir_cursor_mode {
 389         vir_cursor_add,
 390         vir_cursor_addtail,
 391 };
 392
 393 /**
 394  * Tracking structure for where new instructions should be inserted.  Create
 395  * with one of the vir_after_inst()-style helper functions.
 396  *
 397  * This does not protect against removal of the block or instruction, so we
 398  * have an assert in instruction removal to try to catch it.
 399  */
 400 struct vir_cursor {
 401         enum vir_cursor_mode mode;
 402         struct list_head *link;
 403 };
 404
 405 static inline struct vir_cursor
 406 vir_before_inst(struct qinst *inst)
 407 {
 408         return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
 409 }
 410
 411 static inline struct vir_cursor
 412 vir_after_inst(struct qinst *inst)
 413 {
 414         return (struct vir_cursor){ vir_cursor_add, &inst->link };
 415 }
 416
 417 static inline struct vir_cursor
 418 vir_before_block(struct qblock *block)
 419 {
 420         return (struct vir_cursor){ vir_cursor_add, &block->instructions };
 421 }
 422
 423 static inline struct vir_cursor
 424 vir_after_block(struct qblock *block)
 425 {
 426         return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
 427 }
 428
 429 /**
 430  * Compiler state saved across compiler invocations, for any expensive global
 431  * setup.
 432  */
 433 struct v3d_compiler {
 434         const struct v3d_device_info *devinfo;
 435         struct ra_regs *regs;
 436         unsigned int reg_class_phys[3];
 437         unsigned int reg_class_phys_or_acc[3];
 438 };
 439
 440 struct v3d_compile {
 441         const struct v3d_device_info *devinfo;
 442         nir_shader *s;
 443         nir_function_impl *impl;
 444         struct exec_list *cf_node_list;
 445         const struct v3d_compiler *compiler;
 446
 447         /**
 448          * Mapping from nir_register * or nir_ssa_def * to array of struct
 449          * qreg for the values.
 450          */
 451         struct hash_table *def_ht;
 452
 453         /* For each temp, the instruction generating its value. */
 454         struct qinst **defs;
 455         uint32_t defs_array_size;
 456
 457         /**
 458          * Inputs to the shader, arranged by TGSI declaration order.
 459          *
 460          * Not all fragment shader QFILE_VARY reads are present in this array.
 461          */
 462         struct qreg *inputs;
 463         struct qreg *outputs;
 464         bool msaa_per_sample_output;
 465         struct qreg color_reads[V3D_MAX_SAMPLES];
 466         struct qreg sample_colors[V3D_MAX_SAMPLES];
 467         uint32_t inputs_array_size;
 468         uint32_t outputs_array_size;
 469         uint32_t uniforms_array_size;
 470
 471         /* Booleans for whether the corresponding QFILE_VARY[i] is
 472          * flat-shaded.  This includes gl_FragColor flat-shading, which is
 473          * customized based on the shademodel_flat shader key.
 474          */
 475         uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 476
 477         uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 478
 479         uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
 480
 481         bool uses_center_w;
 482
 483         struct v3d_ubo_range *ubo_ranges;
 484         bool *ubo_range_used;
 485         uint32_t ubo_ranges_array_size;
 486         /** Number of uniform areas tracked in ubo_ranges. */
 487         uint32_t num_ubo_ranges;
 488         uint32_t next_ubo_dst_offset;
 489
 490         /* State for whether we're executing on each channel currently.  0 if
 491          * yes, otherwise a block number + 1 that the channel jumped to.
 492          */
 493         struct qreg execute;
 494
 495         struct qreg line_x, point_x, point_y;
 496
 497         /**
 498          * Instance ID, which comes in before the vertex attribute payload if
 499          * the shader record requests it.
 500          */
 501         struct qreg iid;
 502
 503         /**
 504          * Vertex ID, which comes in before the vertex attribute payload
 505          * (after Instance ID) if the shader record requests it.
 506          */
 507         struct qreg vid;
 508
 509         /* Fragment shader payload regs. */
 510         struct qreg payload_w, payload_w_centroid, payload_z;
 511
 512         uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
 513         uint32_t num_vpm_writes;
 514
 515         /* Size in bytes of registers that have been spilled. This is how much
 516          * space needs to be available in the spill BO per thread per QPU.
 517          */
 518         uint32_t spill_size;
 519         /* Shader-db stats for register spilling. */
 520         uint32_t spills, fills;
 521         /**
 522          * Register spilling's per-thread base address, shared between each
 523          * spill/fill's addressing calculations.
 524          */
 525         struct qreg spill_base;
 526         /* Bit vector of which temps may be spilled */
 527         BITSET_WORD *spillable;
 528
 529         /**
 530          * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
 531          *
 532          * This includes those that aren't part of the VPM varyings, like
 533          * point/line coordinates.
 534          */
 535         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 536
 537         /**
 538          * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
 539          * of the output is.  Used to emit from the VS in the order that the
 540          * FS needs.
 541          */
 542         struct v3d_varying_slot *output_slots;
 543
 544         struct pipe_shader_state *shader_state;
 545         struct v3d_key *key;
 546         struct v3d_fs_key *fs_key;
 547         struct v3d_vs_key *vs_key;
 548
 549         /* Live ranges of temps. */
 550         int *temp_start, *temp_end;
 551         bool live_intervals_valid;
 552
 553         uint32_t *uniform_data;
 554         enum quniform_contents *uniform_contents;
 555         uint32_t uniform_array_size;
 556         uint32_t num_uniforms;
 557         uint32_t num_outputs;
 558         uint32_t output_position_index;
 559         nir_variable *output_color_var[4];
 560         uint32_t output_point_size_index;
 561         uint32_t output_sample_mask_index;
 562
 563         struct qreg undef;
 564         uint32_t num_temps;
 565
 566         struct vir_cursor cursor;
 567         struct list_head blocks;
 568         int next_block_index;
 569         struct qblock *cur_block;
 570         struct qblock *loop_cont_block;
 571         struct qblock *loop_break_block;
 572
 573         uint64_t *qpu_insts;
 574         uint32_t qpu_inst_count;
 575         uint32_t qpu_inst_size;
 576
 577         /* For the FS, the number of varying inputs not counting the
 578          * point/line varyings payload
 579          */
 580         uint32_t num_inputs;
 581
 582         /**
 583          * Number of inputs from num_inputs remaining to be queued to the read
 584          * FIFO in the VS/CS.
 585          */
 586         uint32_t num_inputs_remaining;
 587
 588         /* Number of inputs currently in the read FIFO for the VS/CS */
 589         uint32_t num_inputs_in_fifo;
 590
 591         /** Next offset in the VPM to read from in the VS/CS */
 592         uint32_t vpm_read_offset;
 593
 594         uint32_t program_id;
 595         uint32_t variant_id;
 596
 597         /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
 598          * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
 599          * limiting ourselves to the part of the physical reg space.
 600          *
 601          * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x.  On
 602          * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
 603          * physical reg space in half.
 604          */
 605         uint8_t threads;
 606         struct qinst *last_thrsw;
 607         bool last_thrsw_at_top_level;
 608
 609         bool failed;
 610 };
 611
 612 struct v3d_uniform_list {
 613         enum quniform_contents *contents;
 614         uint32_t *data;
 615         uint32_t count;
 616 };
 617
 618 struct v3d_prog_data {
 619         struct v3d_uniform_list uniforms;
 620
 621         struct v3d_ubo_range *ubo_ranges;
 622         uint32_t num_ubo_ranges;
 623         uint32_t ubo_size;
 624         uint32_t spill_size;
 625
 626         uint8_t num_inputs;
 627         uint8_t threads;
 628
 629         /* For threads > 1, whether the program should be dispatched in the
 630          * after-final-THRSW state.
 631          */
 632         bool single_seg;
 633 };
 634
 635 struct v3d_vs_prog_data {
 636         struct v3d_prog_data base;
 637
 638         bool uses_iid, uses_vid;
 639
 640         /* Number of components read from each vertex attribute. */
 641         uint8_t vattr_sizes[32];
 642
 643         /* Total number of components read, for the shader state record. */
 644         uint32_t vpm_input_size;
 645
 646         /* Total number of components written, for the shader state record. */
 647         uint32_t vpm_output_size;
 648
 649         /* Set if there should be separate VPM segments for input and output.
 650          * If unset, vpm_input_size will be 0.
 651          */
 652         bool separate_segments;
 653
 654         /* Value to be programmed in VCM_CACHE_SIZE. */
 655         uint8_t vcm_cache_size;
 656 };
 657
 658 struct v3d_fs_prog_data {
 659         struct v3d_prog_data base;
 660
 661         struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
 662
 663         /* Array of flat shade flags.
 664          *
 665          * Each entry is only 24 bits (high 8 bits 0), to match the hardware
 666          * packet layout.
 667          */
 668         uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 669
 670         uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 671
 672         uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
 673
 674         bool writes_z;
 675         bool discard;
 676         bool uses_center_w;
 677 };
 678
 679 /* Special nir_load_input intrinsic index for loading the current TLB
 680  * destination color.
 681  */
 682 #define V3D_NIR_TLB_COLOR_READ_INPUT            2000000000
 683
 684 #define V3D_NIR_MS_MASK_OUTPUT                  2000000000
 685
 686 extern const nir_shader_compiler_options v3d_nir_options;
 687
 688 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
 689 void v3d_compiler_free(const struct v3d_compiler *compiler);
 690 void v3d_optimize_nir(struct nir_shader *s);
 691
 692 uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
 693                          struct v3d_vs_key *key,
 694                          struct v3d_vs_prog_data *prog_data,
 695                          nir_shader *s,
 696                          int program_id, int variant_id,
 697                          uint32_t *final_assembly_size);
 698
 699 uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
 700                          struct v3d_fs_key *key,
 701                          struct v3d_fs_prog_data *prog_data,
 702                          nir_shader *s,
 703                          int program_id, int variant_id,
 704                          uint32_t *final_assembly_size);
 705
 706 void v3d_nir_to_vir(struct v3d_compile *c);
 707
 708 void vir_compile_destroy(struct v3d_compile *c);
 709 const char *vir_get_stage_name(struct v3d_compile *c);
 710 struct qblock *vir_new_block(struct v3d_compile *c);
 711 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
 712 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
 713 struct qblock *vir_entry_block(struct v3d_compile *c);
 714 struct qblock *vir_exit_block(struct v3d_compile *c);
 715 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
 716                            struct qreg src0, struct qreg src1);
 717 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
 718                            struct qreg src0, struct qreg src1);
 719 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
 720 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
 721 struct qreg vir_uniform(struct v3d_compile *c,
 722                         enum quniform_contents contents,
 723                         uint32_t data);
 724 void vir_schedule_instructions(struct v3d_compile *c);
 725 struct v3d_qpu_instr v3d_qpu_nop(void);
 726
 727 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
 728 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
 729 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
 730 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
 731 void vir_set_unpack(struct qinst *inst, int src,
 732                     enum v3d_qpu_input_unpack unpack);
 733
 734 struct qreg vir_get_temp(struct v3d_compile *c);
 735 void vir_emit_last_thrsw(struct v3d_compile *c);
 736 void vir_calculate_live_intervals(struct v3d_compile *c);
 737 bool vir_has_implicit_uniform(struct qinst *inst);
 738 int vir_get_implicit_uniform_src(struct qinst *inst);
 739 int vir_get_non_sideband_nsrc(struct qinst *inst);
 740 int vir_get_nsrc(struct qinst *inst);
 741 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
 742 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
 743 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
 744 bool vir_is_raw_mov(struct qinst *inst);
 745 bool vir_is_tex(struct qinst *inst);
 746 bool vir_is_add(struct qinst *inst);
 747 bool vir_is_mul(struct qinst *inst);
 748 bool vir_is_float_input(struct qinst *inst);
 749 bool vir_depends_on_flags(struct qinst *inst);
 750 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
 751 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
 752 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
 753 uint8_t vir_channels_written(struct qinst *inst);
 754 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
 755 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
 756                     struct qreg result);
 757 void vir_emit_thrsw(struct v3d_compile *c);
 758
 759 void vir_dump(struct v3d_compile *c);
 760 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
 761
 762 void vir_validate(struct v3d_compile *c);
 763
 764 void vir_optimize(struct v3d_compile *c);
 765 bool vir_opt_algebraic(struct v3d_compile *c);
 766 bool vir_opt_constant_folding(struct v3d_compile *c);
 767 bool vir_opt_copy_propagate(struct v3d_compile *c);
 768 bool vir_opt_dead_code(struct v3d_compile *c);
 769 bool vir_opt_peephole_sf(struct v3d_compile *c);
 770 bool vir_opt_small_immediates(struct v3d_compile *c);
 771 bool vir_opt_vpm(struct v3d_compile *c);
 772 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
 773 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
 774 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
 775 void vir_lower_uniforms(struct v3d_compile *c);
 776
 777 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
 778 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
 779 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 780 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
 781
 782 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
 783 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
 784 void qpu_validate(struct v3d_compile *c);
 785 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c, bool *spilled);
 786 bool vir_init_reg_sets(struct v3d_compiler *compiler);
 787
 788 void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
 789
 790 static inline bool
 791 quniform_contents_is_texture_p0(enum quniform_contents contents)
 792 {
 793         return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
 794                 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
 795                             V3D_MAX_TEXTURE_SAMPLERS));
 796 }
 797
 798 static inline struct qreg
 799 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
 800 {
 801         return vir_uniform(c, QUNIFORM_CONSTANT, ui);
 802 }
 803
 804 static inline struct qreg
 805 vir_uniform_f(struct v3d_compile *c, float f)
 806 {
 807         return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
 808 }
 809
 810 #define VIR_ALU0(name, vir_inst, op)                                     \
 811 static inline struct qreg                                                \
 812 vir_##name(struct v3d_compile *c)                                        \
 813 {                                                                        \
 814         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 815                                         c->undef, c->undef));            \
 816 }                                                                        \
 817 static inline struct qinst *                                             \
 818 vir_##name##_dest(struct v3d_compile *c, struct qreg dest)               \
 819 {                                                                        \
 820         return vir_emit_nondef(c, vir_inst(op, dest,                     \
 821                                            c->undef, c->undef));         \
 822 }
 823
 824 #define VIR_ALU1(name, vir_inst, op)                                     \
 825 static inline struct qreg                                                \
 826 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 827 {                                                                        \
 828         return vir_emit_def(c, vir_inst(op, c->undef,                    \
 829                                         a, c->undef));                   \
 830 }                                                                        \
 831 static inline struct qinst *                                             \
 832 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 833                   struct qreg a)                                         \
 834 {                                                                        \
 835         return vir_emit_nondef(c, vir_inst(op, dest, a,          \
 836                                            c->undef));                   \
 837 }
 838
 839 #define VIR_ALU2(name, vir_inst, op)                                       \
 840 static inline struct qreg                                                \
 841 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)          \
 842 {                                                                        \
 843         return vir_emit_def(c, vir_inst(op, c->undef, a, b));    \
 844 }                                                                        \
 845 static inline struct qinst *                                             \
 846 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 847                   struct qreg a, struct qreg b)                          \
 848 {                                                                        \
 849         return vir_emit_nondef(c, vir_inst(op, dest, a, b));     \
 850 }
 851
 852 #define VIR_NODST_0(name, vir_inst, op)                                 \
 853 static inline struct qinst *                                            \
 854 vir_##name(struct v3d_compile *c)                                       \
 855 {                                                                       \
 856         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 857                                            c->undef, c->undef));        \
 858 }
 859
 860 #define VIR_NODST_1(name, vir_inst, op)                                               \
 861 static inline struct qinst *                                            \
 862 vir_##name(struct v3d_compile *c, struct qreg a)                        \
 863 {                                                                       \
 864         return vir_emit_nondef(c, vir_inst(op, c->undef,        \
 865                                            a, c->undef));               \
 866 }
 867
 868 #define VIR_NODST_2(name, vir_inst, op)                                               \
 869 static inline struct qinst *                                            \
 870 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b)         \
 871 {                                                                       \
 872         return vir_emit_nondef(c, vir_inst(op, c->undef,                \
 873                                            a, b));                      \
 874 }
 875
 876 #define VIR_SFU(name)                                                      \
 877 static inline struct qreg                                                \
 878 vir_##name(struct v3d_compile *c, struct qreg a)                         \
 879 {                                                                        \
 880         if (c->devinfo->ver >= 41) {                                     \
 881                 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name,    \
 882                                                     c->undef,            \
 883                                                     a, c->undef));       \
 884         } else {                                                         \
 885                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 886                 return vir_FMOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 887         }                                                                \
 888 }                                                                        \
 889 static inline struct qinst *                                             \
 890 vir_##name##_dest(struct v3d_compile *c, struct qreg dest,               \
 891                   struct qreg a)                                         \
 892 {                                                                        \
 893         if (c->devinfo->ver >= 41) {                                     \
 894                 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
 895                                                        dest,             \
 896                                                        a, c->undef));    \
 897         } else {                                                         \
 898                 vir_FMOV_dest(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_##name), a); \
 899                 return vir_FMOV_dest(c, dest, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4)); \
 900         }                                                                \
 901 }
 902
 903 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
 904 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
 905 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
 906 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
 907 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
 908 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
 909 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
 910 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
 911 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
 912 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
 913 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
 914
 915 VIR_A_ALU2(FADD)
 916 VIR_A_ALU2(VFPACK)
 917 VIR_A_ALU2(FSUB)
 918 VIR_A_ALU2(FMIN)
 919 VIR_A_ALU2(FMAX)
 920
 921 VIR_A_ALU2(ADD)
 922 VIR_A_ALU2(SUB)
 923 VIR_A_ALU2(SHL)
 924 VIR_A_ALU2(SHR)
 925 VIR_A_ALU2(ASR)
 926 VIR_A_ALU2(ROR)
 927 VIR_A_ALU2(MIN)
 928 VIR_A_ALU2(MAX)
 929 VIR_A_ALU2(UMIN)
 930 VIR_A_ALU2(UMAX)
 931 VIR_A_ALU2(AND)
 932 VIR_A_ALU2(OR)
 933 VIR_A_ALU2(XOR)
 934 VIR_A_ALU2(VADD)
 935 VIR_A_ALU2(VSUB)
 936 VIR_A_NODST_2(STVPMV)
 937 VIR_A_ALU1(NOT)
 938 VIR_A_ALU1(NEG)
 939 VIR_A_ALU1(FLAPUSH)
 940 VIR_A_ALU1(FLBPUSH)
 941 VIR_A_ALU1(FLPOP)
 942 VIR_A_ALU1(SETMSF)
 943 VIR_A_ALU1(SETREVF)
 944 VIR_A_ALU0(TIDX)
 945 VIR_A_ALU0(EIDX)
 946 VIR_A_ALU1(LDVPMV_IN)
 947 VIR_A_ALU1(LDVPMV_OUT)
 948 VIR_A_ALU0(TMUWT)
 949
 950 VIR_A_ALU0(FXCD)
 951 VIR_A_ALU0(XCD)
 952 VIR_A_ALU0(FYCD)
 953 VIR_A_ALU0(YCD)
 954 VIR_A_ALU0(MSF)
 955 VIR_A_ALU0(REVF)
 956 VIR_A_NODST_1(VPMSETUP)
 957 VIR_A_NODST_0(VPMWT)
 958 VIR_A_ALU2(FCMP)
 959 VIR_A_ALU2(VFMAX)
 960
 961 VIR_A_ALU1(FROUND)
 962 VIR_A_ALU1(FTOIN)
 963 VIR_A_ALU1(FTRUNC)
 964 VIR_A_ALU1(FTOIZ)
 965 VIR_A_ALU1(FFLOOR)
 966 VIR_A_ALU1(FTOUZ)
 967 VIR_A_ALU1(FCEIL)
 968 VIR_A_ALU1(FTOC)
 969
 970 VIR_A_ALU1(FDX)
 971 VIR_A_ALU1(FDY)
 972
 973 VIR_A_ALU1(ITOF)
 974 VIR_A_ALU1(CLZ)
 975 VIR_A_ALU1(UTOF)
 976
 977 VIR_M_ALU2(UMUL24)
 978 VIR_M_ALU2(FMUL)
 979 VIR_M_ALU2(SMUL24)
 980 VIR_M_NODST_2(MULTOP)
 981
 982 VIR_M_ALU1(MOV)
 983 VIR_M_ALU1(FMOV)
 984
 985 VIR_SFU(RECIP)
 986 VIR_SFU(RSQRT)
 987 VIR_SFU(EXP)
 988 VIR_SFU(LOG)
 989 VIR_SFU(SIN)
 990 VIR_SFU(RSQRT2)
 991
 992 static inline struct qinst *
 993 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
 994              struct qreg dest, struct qreg src)
 995 {
 996         struct qinst *mov = vir_MOV_dest(c, dest, src);
 997         vir_set_cond(mov, cond);
 998         return mov;
 999 }
1000
1001 static inline struct qreg
1002 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1003         struct qreg src0, struct qreg src1)
1004 {
1005         struct qreg t = vir_get_temp(c);
1006         vir_MOV_dest(c, t, src1);
1007         vir_MOV_cond(c, cond, t, src0);
1008         return t;
1009 }
1010
1011 static inline struct qinst *
1012 vir_NOP(struct v3d_compile *c)
1013 {
1014         return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1015                                                c->undef, c->undef, c->undef));
1016 }
1017
1018 static inline struct qreg
1019 vir_LDTMU(struct v3d_compile *c)
1020 {
1021         if (c->devinfo->ver >= 41) {
1022                 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1023                                                    c->undef, c->undef);
1024                 ldtmu->qpu.sig.ldtmu = true;
1025
1026                 return vir_emit_def(c, ldtmu);
1027         } else {
1028                 vir_NOP(c)->qpu.sig.ldtmu = true;
1029                 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
1030         }
1031 }
1032
1033 static inline struct qreg
1034 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1035 {
1036         vir_MULTOP(c, src0, src1);
1037         return vir_UMUL24(c, src0, src1);
1038 }
1039
1040 /*
1041 static inline struct qreg
1042 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
1043 {
1044         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
1045                                         vir_reg(QFILE_LOAD_IMM, val), c->undef));
1046 }
1047
1048 static inline struct qreg
1049 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
1050 {
1051         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
1052                                         vir_reg(QFILE_LOAD_IMM, val),
1053                                         c->undef));
1054 }
1055 static inline struct qreg
1056 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
1057 {
1058         return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
1059                                         vir_reg(QFILE_LOAD_IMM, val),
1060                                         c->undef));
1061 }
1062 */
1063
1064 static inline struct qinst *
1065 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_cond cond)
1066 {
1067         /* The actual uniform_data value will be set at scheduling time */
1068         return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
1069 }
1070
1071 #define vir_for_each_block(block, c)                                    \
1072         list_for_each_entry(struct qblock, block, &c->blocks, link)
1073
1074 #define vir_for_each_block_rev(block, c)                                \
1075         list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1076
1077 /* Loop over the non-NULL members of the successors array. */
1078 #define vir_for_each_successor(succ, block)                             \
1079         for (struct qblock *succ = block->successors[0];                \
1080              succ != NULL;                                              \
1081              succ = (succ == block->successors[1] ? NULL :              \
1082                      block->successors[1]))
1083
1084 #define vir_for_each_inst(inst, block)                                  \
1085         list_for_each_entry(struct qinst, inst, &block->instructions, link)
1086
1087 #define vir_for_each_inst_rev(inst, block)                                  \
1088         list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1089
1090 #define vir_for_each_inst_safe(inst, block)                             \
1091         list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1092
1093 #define vir_for_each_inst_inorder(inst, c)                              \
1094         vir_for_each_block(_block, c)                                   \
1095                 vir_for_each_inst(inst, _block)
1096
1097 #endif /* V3D_COMPILER_H */