2 * Copyright © 2016-2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
28 vir_get_nsrc(struct qinst
*inst
)
30 switch (inst
->qpu
.type
) {
31 case V3D_QPU_INSTR_TYPE_BRANCH
:
33 case V3D_QPU_INSTR_TYPE_ALU
:
34 if (inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
)
35 return v3d_qpu_add_op_num_src(inst
->qpu
.alu
.add
.op
);
37 return v3d_qpu_mul_op_num_src(inst
->qpu
.alu
.mul
.op
);
44 * Returns whether the instruction has any side effects that must be
48 vir_has_side_effects(struct v3d_compile
*c
, struct qinst
*inst
)
50 switch (inst
->qpu
.type
) {
51 case V3D_QPU_INSTR_TYPE_BRANCH
:
53 case V3D_QPU_INSTR_TYPE_ALU
:
54 switch (inst
->qpu
.alu
.add
.op
) {
55 case V3D_QPU_A_SETREVF
:
56 case V3D_QPU_A_SETMSF
:
57 case V3D_QPU_A_VPMSETUP
:
58 case V3D_QPU_A_STVPMV
:
59 case V3D_QPU_A_STVPMD
:
60 case V3D_QPU_A_STVPMP
:
68 switch (inst
->qpu
.alu
.mul
.op
) {
69 case V3D_QPU_M_MULTOP
:
76 if (inst
->qpu
.sig
.ldtmu
||
77 inst
->qpu
.sig
.ldvary
||
78 inst
->qpu
.sig
.ldtlbu
||
79 inst
->qpu
.sig
.ldtlb
||
80 inst
->qpu
.sig
.wrtmuc
||
81 inst
->qpu
.sig
.thrsw
) {
89 vir_is_raw_mov(struct qinst
*inst
)
91 if (inst
->qpu
.type
!= V3D_QPU_INSTR_TYPE_ALU
||
92 (inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_FMOV
&&
93 inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_MOV
)) {
97 if (inst
->qpu
.alu
.add
.output_pack
!= V3D_QPU_PACK_NONE
||
98 inst
->qpu
.alu
.mul
.output_pack
!= V3D_QPU_PACK_NONE
) {
102 if (inst
->qpu
.alu
.add
.a_unpack
!= V3D_QPU_UNPACK_NONE
||
103 inst
->qpu
.alu
.add
.b_unpack
!= V3D_QPU_UNPACK_NONE
||
104 inst
->qpu
.alu
.mul
.a_unpack
!= V3D_QPU_UNPACK_NONE
||
105 inst
->qpu
.alu
.mul
.b_unpack
!= V3D_QPU_UNPACK_NONE
) {
109 if (inst
->qpu
.flags
.ac
!= V3D_QPU_COND_NONE
||
110 inst
->qpu
.flags
.mc
!= V3D_QPU_COND_NONE
)
117 vir_is_add(struct qinst
*inst
)
119 return (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
120 inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
);
124 vir_is_mul(struct qinst
*inst
)
126 return (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
127 inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_NOP
);
131 vir_is_tex(struct qinst
*inst
)
133 if (inst
->dst
.file
== QFILE_MAGIC
)
134 return v3d_qpu_magic_waddr_is_tmu(inst
->dst
.index
);
136 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
137 inst
->qpu
.alu
.add
.op
== V3D_QPU_A_TMUWT
) {
145 vir_writes_r3(const struct v3d_device_info
*devinfo
, struct qinst
*inst
)
147 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
148 switch (inst
->src
[i
].file
) {
156 if (devinfo
->ver
< 41 && (inst
->qpu
.sig
.ldvary
||
157 inst
->qpu
.sig
.ldtlb
||
158 inst
->qpu
.sig
.ldtlbu
||
159 inst
->qpu
.sig
.ldvpm
)) {
167 vir_writes_r4(const struct v3d_device_info
*devinfo
, struct qinst
*inst
)
169 switch (inst
->dst
.file
) {
171 switch (inst
->dst
.index
) {
172 case V3D_QPU_WADDR_RECIP
:
173 case V3D_QPU_WADDR_RSQRT
:
174 case V3D_QPU_WADDR_EXP
:
175 case V3D_QPU_WADDR_LOG
:
176 case V3D_QPU_WADDR_SIN
:
184 if (devinfo
->ver
< 41 && inst
->qpu
.sig
.ldtmu
)
191 vir_set_unpack(struct qinst
*inst
, int src
,
192 enum v3d_qpu_input_unpack unpack
)
194 assert(src
== 0 || src
== 1);
196 if (vir_is_add(inst
)) {
198 inst
->qpu
.alu
.add
.a_unpack
= unpack
;
200 inst
->qpu
.alu
.add
.b_unpack
= unpack
;
202 assert(vir_is_mul(inst
));
204 inst
->qpu
.alu
.mul
.a_unpack
= unpack
;
206 inst
->qpu
.alu
.mul
.b_unpack
= unpack
;
211 vir_set_cond(struct qinst
*inst
, enum v3d_qpu_cond cond
)
213 if (vir_is_add(inst
)) {
214 inst
->qpu
.flags
.ac
= cond
;
216 assert(vir_is_mul(inst
));
217 inst
->qpu
.flags
.mc
= cond
;
222 vir_set_pf(struct qinst
*inst
, enum v3d_qpu_pf pf
)
224 if (vir_is_add(inst
)) {
225 inst
->qpu
.flags
.apf
= pf
;
227 assert(vir_is_mul(inst
));
228 inst
->qpu
.flags
.mpf
= pf
;
233 vir_set_uf(struct qinst
*inst
, enum v3d_qpu_uf uf
)
235 if (vir_is_add(inst
)) {
236 inst
->qpu
.flags
.auf
= uf
;
238 assert(vir_is_mul(inst
));
239 inst
->qpu
.flags
.muf
= uf
;
245 vir_channels_written(struct qinst
*inst
)
247 if (vir_is_mul(inst
)) {
248 switch (inst
->dst
.pack
) {
249 case QPU_PACK_MUL_NOP
:
250 case QPU_PACK_MUL_8888
:
252 case QPU_PACK_MUL_8A
:
254 case QPU_PACK_MUL_8B
:
256 case QPU_PACK_MUL_8C
:
258 case QPU_PACK_MUL_8D
:
262 switch (inst
->dst
.pack
) {
264 case QPU_PACK_A_8888
:
265 case QPU_PACK_A_8888_SAT
:
266 case QPU_PACK_A_32_SAT
:
269 case QPU_PACK_A_8A_SAT
:
272 case QPU_PACK_A_8B_SAT
:
275 case QPU_PACK_A_8C_SAT
:
278 case QPU_PACK_A_8D_SAT
:
281 case QPU_PACK_A_16A_SAT
:
284 case QPU_PACK_A_16B_SAT
:
288 unreachable("Bad pack field");
293 vir_get_temp(struct v3d_compile
*c
)
297 reg
.file
= QFILE_TEMP
;
298 reg
.index
= c
->num_temps
++;
300 if (c
->num_temps
> c
->defs_array_size
) {
301 uint32_t old_size
= c
->defs_array_size
;
302 c
->defs_array_size
= MAX2(old_size
* 2, 16);
304 c
->defs
= reralloc(c
, c
->defs
, struct qinst
*,
306 memset(&c
->defs
[old_size
], 0,
307 sizeof(c
->defs
[0]) * (c
->defs_array_size
- old_size
));
309 c
->spillable
= reralloc(c
, c
->spillable
,
311 BITSET_WORDS(c
->defs_array_size
));
312 for (int i
= old_size
; i
< c
->defs_array_size
; i
++)
313 BITSET_SET(c
->spillable
, i
);
320 vir_add_inst(enum v3d_qpu_add_op op
, struct qreg dst
, struct qreg src0
, struct qreg src1
)
322 struct qinst
*inst
= calloc(1, sizeof(*inst
));
324 inst
->qpu
= v3d_qpu_nop();
325 inst
->qpu
.alu
.add
.op
= op
;
336 vir_mul_inst(enum v3d_qpu_mul_op op
, struct qreg dst
, struct qreg src0
, struct qreg src1
)
338 struct qinst
*inst
= calloc(1, sizeof(*inst
));
340 inst
->qpu
= v3d_qpu_nop();
341 inst
->qpu
.alu
.mul
.op
= op
;
352 vir_branch_inst(struct v3d_compile
*c
, enum v3d_qpu_branch_cond cond
)
354 struct qinst
*inst
= calloc(1, sizeof(*inst
));
356 inst
->qpu
= v3d_qpu_nop();
357 inst
->qpu
.type
= V3D_QPU_INSTR_TYPE_BRANCH
;
358 inst
->qpu
.branch
.cond
= cond
;
359 inst
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_NONE
;
360 inst
->qpu
.branch
.bdi
= V3D_QPU_BRANCH_DEST_REL
;
361 inst
->qpu
.branch
.ub
= true;
362 inst
->qpu
.branch
.bdu
= V3D_QPU_BRANCH_DEST_REL
;
364 inst
->dst
= vir_nop_reg();
365 inst
->uniform
= vir_get_uniform_index(c
, QUNIFORM_CONSTANT
, 0);
371 vir_emit(struct v3d_compile
*c
, struct qinst
*inst
)
373 switch (c
->cursor
.mode
) {
375 list_add(&inst
->link
, c
->cursor
.link
);
377 case vir_cursor_addtail
:
378 list_addtail(&inst
->link
, c
->cursor
.link
);
382 c
->cursor
= vir_after_inst(inst
);
383 c
->live_intervals_valid
= false;
386 /* Updates inst to write to a new temporary, emits it, and notes the def. */
388 vir_emit_def(struct v3d_compile
*c
, struct qinst
*inst
)
390 assert(inst
->dst
.file
== QFILE_NULL
);
392 /* If we're emitting an instruction that's a def, it had better be
393 * writing a register.
395 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
) {
396 assert(inst
->qpu
.alu
.add
.op
== V3D_QPU_A_NOP
||
397 v3d_qpu_add_op_has_dst(inst
->qpu
.alu
.add
.op
));
398 assert(inst
->qpu
.alu
.mul
.op
== V3D_QPU_M_NOP
||
399 v3d_qpu_mul_op_has_dst(inst
->qpu
.alu
.mul
.op
));
402 inst
->dst
= vir_get_temp(c
);
404 if (inst
->dst
.file
== QFILE_TEMP
)
405 c
->defs
[inst
->dst
.index
] = inst
;
413 vir_emit_nondef(struct v3d_compile
*c
, struct qinst
*inst
)
415 if (inst
->dst
.file
== QFILE_TEMP
)
416 c
->defs
[inst
->dst
.index
] = NULL
;
424 vir_new_block(struct v3d_compile
*c
)
426 struct qblock
*block
= rzalloc(c
, struct qblock
);
428 list_inithead(&block
->instructions
);
430 block
->predecessors
= _mesa_set_create(block
,
432 _mesa_key_pointer_equal
);
434 block
->index
= c
->next_block_index
++;
440 vir_set_emit_block(struct v3d_compile
*c
, struct qblock
*block
)
442 c
->cur_block
= block
;
443 c
->cursor
= vir_after_block(block
);
444 list_addtail(&block
->link
, &c
->blocks
);
448 vir_entry_block(struct v3d_compile
*c
)
450 return list_first_entry(&c
->blocks
, struct qblock
, link
);
454 vir_exit_block(struct v3d_compile
*c
)
456 return list_last_entry(&c
->blocks
, struct qblock
, link
);
460 vir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
)
462 _mesa_set_add(successor
->predecessors
, predecessor
);
463 if (predecessor
->successors
[0]) {
464 assert(!predecessor
->successors
[1]);
465 predecessor
->successors
[1] = successor
;
467 predecessor
->successors
[0] = successor
;
471 const struct v3d_compiler
*
472 v3d_compiler_init(const struct v3d_device_info
*devinfo
)
474 struct v3d_compiler
*compiler
= rzalloc(NULL
, struct v3d_compiler
);
478 compiler
->devinfo
= devinfo
;
480 if (!vir_init_reg_sets(compiler
)) {
481 ralloc_free(compiler
);
489 v3d_compiler_free(const struct v3d_compiler
*compiler
)
491 ralloc_free((void *)compiler
);
494 static struct v3d_compile
*
495 vir_compile_init(const struct v3d_compiler
*compiler
,
498 void (*debug_output
)(const char *msg
,
499 void *debug_output_data
),
500 void *debug_output_data
,
501 int program_id
, int variant_id
)
503 struct v3d_compile
*c
= rzalloc(NULL
, struct v3d_compile
);
505 c
->compiler
= compiler
;
506 c
->devinfo
= compiler
->devinfo
;
508 c
->program_id
= program_id
;
509 c
->variant_id
= variant_id
;
511 c
->debug_output
= debug_output
;
512 c
->debug_output_data
= debug_output_data
;
514 s
= nir_shader_clone(c
, s
);
517 list_inithead(&c
->blocks
);
518 vir_set_emit_block(c
, vir_new_block(c
));
520 c
->output_position_index
= -1;
521 c
->output_sample_mask_index
= -1;
523 c
->def_ht
= _mesa_hash_table_create(c
, _mesa_hash_pointer
,
524 _mesa_key_pointer_equal
);
530 type_size_vec4(const struct glsl_type
*type
, bool bindless
)
532 return glsl_count_attribute_slots(type
, false);
536 v3d_lower_nir(struct v3d_compile
*c
)
538 struct nir_lower_tex_options tex_options
= {
540 .lower_tg4_broadcom_swizzle
= true,
542 .lower_rect
= false, /* XXX: Use this on V3D 3.x */
544 /* Apply swizzles to all samplers. */
545 .swizzle_result
= ~0,
548 /* Lower the format swizzle and (for 32-bit returns)
549 * ARB_texture_swizzle-style swizzle.
551 for (int i
= 0; i
< ARRAY_SIZE(c
->key
->tex
); i
++) {
552 for (int j
= 0; j
< 4; j
++)
553 tex_options
.swizzles
[i
][j
] = c
->key
->tex
[i
].swizzle
[j
];
555 if (c
->key
->tex
[i
].clamp_s
)
556 tex_options
.saturate_s
|= 1 << i
;
557 if (c
->key
->tex
[i
].clamp_t
)
558 tex_options
.saturate_t
|= 1 << i
;
559 if (c
->key
->tex
[i
].clamp_r
)
560 tex_options
.saturate_r
|= 1 << i
;
561 if (c
->key
->tex
[i
].return_size
== 16) {
562 tex_options
.lower_tex_packing
[i
] =
563 nir_lower_tex_packing_16
;
567 /* CS textures may not have return_size reflecting the shadow state. */
568 nir_foreach_variable(var
, &c
->s
->uniforms
) {
569 const struct glsl_type
*type
= glsl_without_array(var
->type
);
570 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
572 if (!glsl_type_is_sampler(type
) ||
573 !glsl_sampler_type_is_shadow(type
))
576 for (int i
= 0; i
< array_len
; i
++) {
577 tex_options
.lower_tex_packing
[var
->data
.binding
+ i
] =
578 nir_lower_tex_packing_16
;
582 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
583 NIR_PASS_V(c
->s
, nir_lower_system_values
);
585 NIR_PASS_V(c
->s
, nir_lower_vars_to_scratch
,
586 nir_var_function_temp
,
588 glsl_get_natural_size_align_bytes
);
589 NIR_PASS_V(c
->s
, v3d_nir_lower_scratch
);
593 v3d_set_prog_data_uniforms(struct v3d_compile
*c
,
594 struct v3d_prog_data
*prog_data
)
596 int count
= c
->num_uniforms
;
597 struct v3d_uniform_list
*ulist
= &prog_data
->uniforms
;
599 ulist
->count
= count
;
600 ulist
->data
= ralloc_array(prog_data
, uint32_t, count
);
601 memcpy(ulist
->data
, c
->uniform_data
,
602 count
* sizeof(*ulist
->data
));
603 ulist
->contents
= ralloc_array(prog_data
, enum quniform_contents
, count
);
604 memcpy(ulist
->contents
, c
->uniform_contents
,
605 count
* sizeof(*ulist
->contents
));
609 v3d_vs_set_prog_data(struct v3d_compile
*c
,
610 struct v3d_vs_prog_data
*prog_data
)
612 /* The vertex data gets format converted by the VPM so that
613 * each attribute channel takes up a VPM column. Precompute
614 * the sizes for the shader record.
616 for (int i
= 0; i
< ARRAY_SIZE(prog_data
->vattr_sizes
); i
++) {
617 prog_data
->vattr_sizes
[i
] = c
->vattr_sizes
[i
];
618 prog_data
->vpm_input_size
+= c
->vattr_sizes
[i
];
621 prog_data
->uses_vid
= (c
->s
->info
.system_values_read
&
622 (1ull << SYSTEM_VALUE_VERTEX_ID
));
623 prog_data
->uses_iid
= (c
->s
->info
.system_values_read
&
624 (1ull << SYSTEM_VALUE_INSTANCE_ID
));
626 if (prog_data
->uses_vid
)
627 prog_data
->vpm_input_size
++;
628 if (prog_data
->uses_iid
)
629 prog_data
->vpm_input_size
++;
631 /* Input/output segment size are in sectors (8 rows of 32 bits per
634 prog_data
->vpm_input_size
= align(prog_data
->vpm_input_size
, 8) / 8;
635 prog_data
->vpm_output_size
= align(c
->vpm_output_size
, 8) / 8;
637 /* Set us up for shared input/output segments. This is apparently
638 * necessary for our VCM setup to avoid varying corruption.
640 prog_data
->separate_segments
= false;
641 prog_data
->vpm_output_size
= MAX2(prog_data
->vpm_output_size
,
642 prog_data
->vpm_input_size
);
643 prog_data
->vpm_input_size
= 0;
645 /* Compute VCM cache size. We set up our program to take up less than
646 * half of the VPM, so that any set of bin and render programs won't
647 * run out of space. We need space for at least one input segment,
648 * and then allocate the rest to output segments (one for the current
649 * program, the rest to VCM). The valid range of the VCM cache size
650 * field is 1-4 16-vertex batches, but GFXH-1744 limits us to 2-4
653 assert(c
->devinfo
->vpm_size
);
654 int sector_size
= V3D_CHANNELS
* sizeof(uint32_t) * 8;
655 int vpm_size_in_sectors
= c
->devinfo
->vpm_size
/ sector_size
;
656 int half_vpm
= vpm_size_in_sectors
/ 2;
657 int vpm_output_sectors
= half_vpm
- prog_data
->vpm_input_size
;
658 int vpm_output_batches
= vpm_output_sectors
/ prog_data
->vpm_output_size
;
659 assert(vpm_output_batches
>= 2);
660 prog_data
->vcm_cache_size
= CLAMP(vpm_output_batches
- 1, 2, 4);
664 v3d_set_fs_prog_data_inputs(struct v3d_compile
*c
,
665 struct v3d_fs_prog_data
*prog_data
)
667 prog_data
->num_inputs
= c
->num_inputs
;
668 memcpy(prog_data
->input_slots
, c
->input_slots
,
669 c
->num_inputs
* sizeof(*c
->input_slots
));
671 STATIC_ASSERT(ARRAY_SIZE(prog_data
->flat_shade_flags
) >
672 (V3D_MAX_FS_INPUTS
- 1) / 24);
673 for (int i
= 0; i
< V3D_MAX_FS_INPUTS
; i
++) {
674 if (BITSET_TEST(c
->flat_shade_flags
, i
))
675 prog_data
->flat_shade_flags
[i
/ 24] |= 1 << (i
% 24);
677 if (BITSET_TEST(c
->noperspective_flags
, i
))
678 prog_data
->noperspective_flags
[i
/ 24] |= 1 << (i
% 24);
680 if (BITSET_TEST(c
->centroid_flags
, i
))
681 prog_data
->centroid_flags
[i
/ 24] |= 1 << (i
% 24);
686 v3d_fs_set_prog_data(struct v3d_compile
*c
,
687 struct v3d_fs_prog_data
*prog_data
)
689 v3d_set_fs_prog_data_inputs(c
, prog_data
);
690 prog_data
->writes_z
= c
->writes_z
;
691 prog_data
->disable_ez
= !c
->s
->info
.fs
.early_fragment_tests
;
692 prog_data
->uses_center_w
= c
->uses_center_w
;
693 prog_data
->uses_implicit_point_line_varyings
=
694 c
->uses_implicit_point_line_varyings
;
695 prog_data
->lock_scoreboard_on_first_thrsw
=
696 c
->lock_scoreboard_on_first_thrsw
;
700 v3d_cs_set_prog_data(struct v3d_compile
*c
,
701 struct v3d_compute_prog_data
*prog_data
)
703 prog_data
->shared_size
= c
->s
->info
.cs
.shared_size
;
707 v3d_set_prog_data(struct v3d_compile
*c
,
708 struct v3d_prog_data
*prog_data
)
710 prog_data
->threads
= c
->threads
;
711 prog_data
->single_seg
= !c
->last_thrsw
;
712 prog_data
->spill_size
= c
->spill_size
;
714 v3d_set_prog_data_uniforms(c
, prog_data
);
716 if (c
->s
->info
.stage
== MESA_SHADER_COMPUTE
) {
717 v3d_cs_set_prog_data(c
, (struct v3d_compute_prog_data
*)prog_data
);
718 } else if (c
->s
->info
.stage
== MESA_SHADER_VERTEX
) {
719 v3d_vs_set_prog_data(c
, (struct v3d_vs_prog_data
*)prog_data
);
721 assert(c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
);
722 v3d_fs_set_prog_data(c
, (struct v3d_fs_prog_data
*)prog_data
);
727 v3d_return_qpu_insts(struct v3d_compile
*c
, uint32_t *final_assembly_size
)
729 *final_assembly_size
= c
->qpu_inst_count
* sizeof(uint64_t);
731 uint64_t *qpu_insts
= malloc(*final_assembly_size
);
735 memcpy(qpu_insts
, c
->qpu_insts
, *final_assembly_size
);
737 vir_compile_destroy(c
);
743 v3d_nir_lower_vs_early(struct v3d_compile
*c
)
745 /* Split our I/O vars and dead code eliminate the unused
748 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar_early
,
749 nir_var_shader_in
| nir_var_shader_out
);
750 uint64_t used_outputs
[4] = {0};
751 for (int i
= 0; i
< c
->vs_key
->num_fs_inputs
; i
++) {
752 int slot
= v3d_slot_get_slot(c
->vs_key
->fs_inputs
[i
]);
753 int comp
= v3d_slot_get_component(c
->vs_key
->fs_inputs
[i
]);
754 used_outputs
[comp
] |= 1ull << slot
;
756 NIR_PASS_V(c
->s
, nir_remove_unused_io_vars
,
757 &c
->s
->outputs
, used_outputs
, NULL
); /* demotes to globals */
758 NIR_PASS_V(c
->s
, nir_lower_global_vars_to_local
);
759 v3d_optimize_nir(c
->s
);
760 NIR_PASS_V(c
->s
, nir_remove_dead_variables
, nir_var_shader_in
);
761 NIR_PASS_V(c
->s
, nir_lower_io
, nir_var_shader_in
| nir_var_shader_out
,
763 (nir_lower_io_options
)0);
767 v3d_fixup_fs_output_types(struct v3d_compile
*c
)
769 nir_foreach_variable(var
, &c
->s
->outputs
) {
772 switch (var
->data
.location
) {
773 case FRAG_RESULT_COLOR
:
776 case FRAG_RESULT_DATA0
:
777 case FRAG_RESULT_DATA1
:
778 case FRAG_RESULT_DATA2
:
779 case FRAG_RESULT_DATA3
:
780 mask
= 1 << (var
->data
.location
- FRAG_RESULT_DATA0
);
784 if (c
->fs_key
->int_color_rb
& mask
) {
786 glsl_vector_type(GLSL_TYPE_INT
,
787 glsl_get_components(var
->type
));
788 } else if (c
->fs_key
->uint_color_rb
& mask
) {
790 glsl_vector_type(GLSL_TYPE_UINT
,
791 glsl_get_components(var
->type
));
797 v3d_nir_lower_fs_early(struct v3d_compile
*c
)
799 if (c
->fs_key
->int_color_rb
|| c
->fs_key
->uint_color_rb
)
800 v3d_fixup_fs_output_types(c
);
802 NIR_PASS_V(c
->s
, v3d_nir_lower_logic_ops
, c
);
804 /* If the shader has no non-TLB side effects, we can promote it to
805 * enabling early_fragment_tests even if the user didn't.
807 if (!(c
->s
->info
.num_images
||
808 c
->s
->info
.num_ssbos
||
809 c
->s
->info
.num_abos
)) {
810 c
->s
->info
.fs
.early_fragment_tests
= true;
815 v3d_nir_lower_vs_late(struct v3d_compile
*c
)
817 if (c
->vs_key
->clamp_color
)
818 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
820 if (c
->key
->ucp_enables
) {
821 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, c
->key
->ucp_enables
,
823 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
,
827 /* Note: VS output scalarizing must happen after nir_lower_clip_vs. */
828 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
832 v3d_nir_lower_fs_late(struct v3d_compile
*c
)
834 if (c
->fs_key
->light_twoside
)
835 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
837 if (c
->fs_key
->clamp_color
)
838 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
840 if (c
->fs_key
->alpha_test
) {
841 NIR_PASS_V(c
->s
, nir_lower_alpha_test
,
842 c
->fs_key
->alpha_test_func
,
846 if (c
->key
->ucp_enables
)
847 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, c
->key
->ucp_enables
);
849 /* Note: FS input scalarizing must happen after
850 * nir_lower_two_sided_color, which only handles a vec4 at a time.
852 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_in
);
856 vir_get_max_temps(struct v3d_compile
*c
)
859 vir_for_each_inst_inorder(inst
, c
)
862 uint32_t *pressure
= rzalloc_array(NULL
, uint32_t, max_ip
);
864 for (int t
= 0; t
< c
->num_temps
; t
++) {
865 for (int i
= c
->temp_start
[t
]; (i
< c
->temp_end
[t
] &&
873 uint32_t max_temps
= 0;
874 for (int i
= 0; i
< max_ip
; i
++)
875 max_temps
= MAX2(max_temps
, pressure
[i
]);
877 ralloc_free(pressure
);
882 uint64_t *v3d_compile(const struct v3d_compiler
*compiler
,
884 struct v3d_prog_data
**out_prog_data
,
886 void (*debug_output
)(const char *msg
,
887 void *debug_output_data
),
888 void *debug_output_data
,
889 int program_id
, int variant_id
,
890 uint32_t *final_assembly_size
)
892 struct v3d_prog_data
*prog_data
;
893 struct v3d_compile
*c
= vir_compile_init(compiler
, key
, s
,
894 debug_output
, debug_output_data
,
895 program_id
, variant_id
);
897 switch (c
->s
->info
.stage
) {
898 case MESA_SHADER_VERTEX
:
899 c
->vs_key
= (struct v3d_vs_key
*)key
;
900 prog_data
= rzalloc_size(NULL
, sizeof(struct v3d_vs_prog_data
));
902 case MESA_SHADER_FRAGMENT
:
903 c
->fs_key
= (struct v3d_fs_key
*)key
;
904 prog_data
= rzalloc_size(NULL
, sizeof(struct v3d_fs_prog_data
));
906 case MESA_SHADER_COMPUTE
:
907 prog_data
= rzalloc_size(NULL
,
908 sizeof(struct v3d_compute_prog_data
));
911 unreachable("unsupported shader stage");
914 if (c
->s
->info
.stage
== MESA_SHADER_VERTEX
) {
915 v3d_nir_lower_vs_early(c
);
916 } else if (c
->s
->info
.stage
!= MESA_SHADER_COMPUTE
) {
917 assert(c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
);
918 v3d_nir_lower_fs_early(c
);
923 if (c
->s
->info
.stage
== MESA_SHADER_VERTEX
) {
924 v3d_nir_lower_vs_late(c
);
925 } else if (c
->s
->info
.stage
!= MESA_SHADER_COMPUTE
) {
926 assert(c
->s
->info
.stage
== MESA_SHADER_FRAGMENT
);
927 v3d_nir_lower_fs_late(c
);
930 NIR_PASS_V(c
->s
, v3d_nir_lower_io
, c
);
931 NIR_PASS_V(c
->s
, v3d_nir_lower_txf_ms
, c
);
932 NIR_PASS_V(c
->s
, v3d_nir_lower_image_load_store
);
933 NIR_PASS_V(c
->s
, nir_lower_idiv
);
935 v3d_optimize_nir(c
->s
);
936 NIR_PASS_V(c
->s
, nir_lower_bool_to_int32
);
937 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
941 v3d_set_prog_data(c
, prog_data
);
943 *out_prog_data
= prog_data
;
946 int ret
= asprintf(&shaderdb
,
947 "%s shader: %d inst, %d threads, %d loops, "
948 "%d uniforms, %d max-temps, %d:%d spills:fills",
949 vir_get_stage_name(c
),
954 vir_get_max_temps(c
),
958 if (V3D_DEBUG
& V3D_DEBUG_SHADERDB
)
959 fprintf(stderr
, "SHADER-DB: %s\n", shaderdb
);
961 c
->debug_output(shaderdb
, c
->debug_output_data
);
965 return v3d_return_qpu_insts(c
, final_assembly_size
);
969 vir_remove_instruction(struct v3d_compile
*c
, struct qinst
*qinst
)
971 if (qinst
->dst
.file
== QFILE_TEMP
)
972 c
->defs
[qinst
->dst
.index
] = NULL
;
974 assert(&qinst
->link
!= c
->cursor
.link
);
976 list_del(&qinst
->link
);
979 c
->live_intervals_valid
= false;
983 vir_follow_movs(struct v3d_compile
*c
, struct qreg reg
)
988 while (reg.file == QFILE_TEMP &&
989 c->defs[reg.index] &&
990 (c->defs[reg.index]->op == QOP_MOV ||
991 c->defs[reg.index]->op == QOP_FMOV) &&
992 !c->defs[reg.index]->dst.pack &&
993 !c->defs[reg.index]->src[0].pack) {
994 reg = c->defs[reg.index]->src[0];
1003 vir_compile_destroy(struct v3d_compile
*c
)
1005 /* Defuse the assert that we aren't removing the cursor's instruction.
1007 c
->cursor
.link
= NULL
;
1009 vir_for_each_block(block
, c
) {
1010 while (!list_empty(&block
->instructions
)) {
1011 struct qinst
*qinst
=
1012 list_first_entry(&block
->instructions
,
1013 struct qinst
, link
);
1014 vir_remove_instruction(c
, qinst
);
1022 vir_get_uniform_index(struct v3d_compile
*c
,
1023 enum quniform_contents contents
,
1026 for (int i
= 0; i
< c
->num_uniforms
; i
++) {
1027 if (c
->uniform_contents
[i
] == contents
&&
1028 c
->uniform_data
[i
] == data
) {
1033 uint32_t uniform
= c
->num_uniforms
++;
1035 if (uniform
>= c
->uniform_array_size
) {
1036 c
->uniform_array_size
= MAX2(MAX2(16, uniform
+ 1),
1037 c
->uniform_array_size
* 2);
1039 c
->uniform_data
= reralloc(c
, c
->uniform_data
,
1041 c
->uniform_array_size
);
1042 c
->uniform_contents
= reralloc(c
, c
->uniform_contents
,
1043 enum quniform_contents
,
1044 c
->uniform_array_size
);
1047 c
->uniform_contents
[uniform
] = contents
;
1048 c
->uniform_data
[uniform
] = data
;
1054 vir_uniform(struct v3d_compile
*c
,
1055 enum quniform_contents contents
,
1058 struct qinst
*inst
= vir_NOP(c
);
1059 inst
->qpu
.sig
.ldunif
= true;
1060 inst
->uniform
= vir_get_uniform_index(c
, contents
, data
);
1061 inst
->dst
= vir_get_temp(c
);
1062 c
->defs
[inst
->dst
.index
] = inst
;
1066 #define OPTPASS(func) \
1068 bool stage_progress = func(c); \
1069 if (stage_progress) { \
1071 if (print_opt_debug) { \
1073 "VIR opt pass %2d: %s progress\n", \
1076 /*XXX vir_validate(c);*/ \
1081 vir_optimize(struct v3d_compile
*c
)
1083 bool print_opt_debug
= false;
1087 bool progress
= false;
1089 OPTPASS(vir_opt_copy_propagate
);
1090 OPTPASS(vir_opt_redundant_flags
);
1091 OPTPASS(vir_opt_dead_code
);
1092 OPTPASS(vir_opt_small_immediates
);
1102 vir_get_stage_name(struct v3d_compile
*c
)
1104 if (c
->vs_key
&& c
->vs_key
->is_coord
)
1105 return "MESA_SHADER_COORD";
1107 return gl_shader_stage_name(c
->s
->info
.stage
);