2 * Copyright © 2016-2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
28 vir_get_non_sideband_nsrc(struct qinst
*inst
)
30 switch (inst
->qpu
.type
) {
31 case V3D_QPU_INSTR_TYPE_BRANCH
:
33 case V3D_QPU_INSTR_TYPE_ALU
:
34 if (inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
)
35 return v3d_qpu_add_op_num_src(inst
->qpu
.alu
.add
.op
);
37 return v3d_qpu_mul_op_num_src(inst
->qpu
.alu
.mul
.op
);
44 vir_get_nsrc(struct qinst
*inst
)
46 int nsrc
= vir_get_non_sideband_nsrc(inst
);
48 if (vir_has_implicit_uniform(inst
))
55 vir_has_implicit_uniform(struct qinst
*inst
)
57 switch (inst
->qpu
.type
) {
58 case V3D_QPU_INSTR_TYPE_BRANCH
:
60 case V3D_QPU_INSTR_TYPE_ALU
:
61 switch (inst
->dst
.file
) {
65 return inst
->has_implicit_uniform
;
71 /* The sideband uniform for textures gets stored after the normal ALU
75 vir_get_implicit_uniform_src(struct qinst
*inst
)
77 if (!vir_has_implicit_uniform(inst
))
79 return vir_get_nsrc(inst
) - 1;
83 * Returns whether the instruction has any side effects that must be
87 vir_has_side_effects(struct v3d_compile
*c
, struct qinst
*inst
)
89 switch (inst
->qpu
.type
) {
90 case V3D_QPU_INSTR_TYPE_BRANCH
:
92 case V3D_QPU_INSTR_TYPE_ALU
:
93 switch (inst
->qpu
.alu
.add
.op
) {
94 case V3D_QPU_A_SETREVF
:
95 case V3D_QPU_A_SETMSF
:
96 case V3D_QPU_A_VPMSETUP
:
97 case V3D_QPU_A_STVPMV
:
98 case V3D_QPU_A_STVPMD
:
99 case V3D_QPU_A_STVPMP
:
100 case V3D_QPU_A_VPMWT
:
101 case V3D_QPU_A_TMUWT
:
107 switch (inst
->qpu
.alu
.mul
.op
) {
108 case V3D_QPU_M_MULTOP
:
115 if (inst
->qpu
.sig
.ldtmu
||
116 inst
->qpu
.sig
.ldvary
||
117 inst
->qpu
.sig
.wrtmuc
||
118 inst
->qpu
.sig
.thrsw
) {
126 vir_is_float_input(struct qinst
*inst
)
128 /* XXX: More instrs */
129 switch (inst
->qpu
.type
) {
130 case V3D_QPU_INSTR_TYPE_BRANCH
:
132 case V3D_QPU_INSTR_TYPE_ALU
:
133 switch (inst
->qpu
.alu
.add
.op
) {
138 case V3D_QPU_A_FTOIN
:
144 switch (inst
->qpu
.alu
.mul
.op
) {
146 case V3D_QPU_M_VFMUL
:
158 vir_is_raw_mov(struct qinst
*inst
)
160 if (inst
->qpu
.type
!= V3D_QPU_INSTR_TYPE_ALU
||
161 (inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_FMOV
&&
162 inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_MOV
)) {
166 if (inst
->qpu
.alu
.add
.output_pack
!= V3D_QPU_PACK_NONE
||
167 inst
->qpu
.alu
.mul
.output_pack
!= V3D_QPU_PACK_NONE
) {
171 if (inst
->qpu
.flags
.ac
!= V3D_QPU_COND_NONE
||
172 inst
->qpu
.flags
.mc
!= V3D_QPU_COND_NONE
)
179 vir_is_add(struct qinst
*inst
)
181 return (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
182 inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
);
186 vir_is_mul(struct qinst
*inst
)
188 return (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
189 inst
->qpu
.alu
.mul
.op
!= V3D_QPU_M_NOP
);
193 vir_is_tex(struct qinst
*inst
)
195 if (inst
->dst
.file
== QFILE_MAGIC
)
196 return v3d_qpu_magic_waddr_is_tmu(inst
->dst
.index
);
198 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
&&
199 inst
->qpu
.alu
.add
.op
== V3D_QPU_A_TMUWT
) {
207 vir_depends_on_flags(struct qinst
*inst
)
209 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_BRANCH
) {
210 return (inst
->qpu
.branch
.cond
!= V3D_QPU_BRANCH_COND_ALWAYS
);
212 return (inst
->qpu
.flags
.ac
!= V3D_QPU_COND_NONE
&&
213 inst
->qpu
.flags
.mc
!= V3D_QPU_COND_NONE
);
218 vir_writes_r3(const struct v3d_device_info
*devinfo
, struct qinst
*inst
)
220 for (int i
= 0; i
< vir_get_nsrc(inst
); i
++) {
221 switch (inst
->src
[i
].file
) {
229 if (devinfo
->ver
< 41 && (inst
->qpu
.sig
.ldvary
||
230 inst
->qpu
.sig
.ldtlb
||
231 inst
->qpu
.sig
.ldtlbu
||
232 inst
->qpu
.sig
.ldvpm
)) {
240 vir_writes_r4(const struct v3d_device_info
*devinfo
, struct qinst
*inst
)
242 switch (inst
->dst
.file
) {
244 switch (inst
->dst
.index
) {
245 case V3D_QPU_WADDR_RECIP
:
246 case V3D_QPU_WADDR_RSQRT
:
247 case V3D_QPU_WADDR_EXP
:
248 case V3D_QPU_WADDR_LOG
:
249 case V3D_QPU_WADDR_SIN
:
257 if (devinfo
->ver
< 41 && inst
->qpu
.sig
.ldtmu
)
264 vir_set_unpack(struct qinst
*inst
, int src
,
265 enum v3d_qpu_input_unpack unpack
)
267 assert(src
== 0 || src
== 1);
269 if (vir_is_add(inst
)) {
271 inst
->qpu
.alu
.add
.a_unpack
= unpack
;
273 inst
->qpu
.alu
.add
.b_unpack
= unpack
;
275 assert(vir_is_mul(inst
));
277 inst
->qpu
.alu
.mul
.a_unpack
= unpack
;
279 inst
->qpu
.alu
.mul
.b_unpack
= unpack
;
284 vir_set_cond(struct qinst
*inst
, enum v3d_qpu_cond cond
)
286 if (vir_is_add(inst
)) {
287 inst
->qpu
.flags
.ac
= cond
;
289 assert(vir_is_mul(inst
));
290 inst
->qpu
.flags
.mc
= cond
;
295 vir_set_pf(struct qinst
*inst
, enum v3d_qpu_pf pf
)
297 if (vir_is_add(inst
)) {
298 inst
->qpu
.flags
.apf
= pf
;
300 assert(vir_is_mul(inst
));
301 inst
->qpu
.flags
.mpf
= pf
;
307 vir_channels_written(struct qinst
*inst
)
309 if (vir_is_mul(inst
)) {
310 switch (inst
->dst
.pack
) {
311 case QPU_PACK_MUL_NOP
:
312 case QPU_PACK_MUL_8888
:
314 case QPU_PACK_MUL_8A
:
316 case QPU_PACK_MUL_8B
:
318 case QPU_PACK_MUL_8C
:
320 case QPU_PACK_MUL_8D
:
324 switch (inst
->dst
.pack
) {
326 case QPU_PACK_A_8888
:
327 case QPU_PACK_A_8888_SAT
:
328 case QPU_PACK_A_32_SAT
:
331 case QPU_PACK_A_8A_SAT
:
334 case QPU_PACK_A_8B_SAT
:
337 case QPU_PACK_A_8C_SAT
:
340 case QPU_PACK_A_8D_SAT
:
343 case QPU_PACK_A_16A_SAT
:
346 case QPU_PACK_A_16B_SAT
:
350 unreachable("Bad pack field");
355 vir_get_temp(struct v3d_compile
*c
)
359 reg
.file
= QFILE_TEMP
;
360 reg
.index
= c
->num_temps
++;
362 if (c
->num_temps
> c
->defs_array_size
) {
363 uint32_t old_size
= c
->defs_array_size
;
364 c
->defs_array_size
= MAX2(old_size
* 2, 16);
366 c
->defs
= reralloc(c
, c
->defs
, struct qinst
*,
368 memset(&c
->defs
[old_size
], 0,
369 sizeof(c
->defs
[0]) * (c
->defs_array_size
- old_size
));
371 c
->spillable
= reralloc(c
, c
->spillable
,
373 BITSET_WORDS(c
->defs_array_size
));
374 for (int i
= old_size
; i
< c
->defs_array_size
; i
++)
375 BITSET_SET(c
->spillable
, i
);
382 vir_add_inst(enum v3d_qpu_add_op op
, struct qreg dst
, struct qreg src0
, struct qreg src1
)
384 struct qinst
*inst
= calloc(1, sizeof(*inst
));
386 inst
->qpu
= v3d_qpu_nop();
387 inst
->qpu
.alu
.add
.op
= op
;
398 vir_mul_inst(enum v3d_qpu_mul_op op
, struct qreg dst
, struct qreg src0
, struct qreg src1
)
400 struct qinst
*inst
= calloc(1, sizeof(*inst
));
402 inst
->qpu
= v3d_qpu_nop();
403 inst
->qpu
.alu
.mul
.op
= op
;
414 vir_branch_inst(enum v3d_qpu_branch_cond cond
, struct qreg src
)
416 struct qinst
*inst
= calloc(1, sizeof(*inst
));
418 inst
->qpu
= v3d_qpu_nop();
419 inst
->qpu
.type
= V3D_QPU_INSTR_TYPE_BRANCH
;
420 inst
->qpu
.branch
.cond
= cond
;
421 inst
->qpu
.branch
.msfign
= V3D_QPU_MSFIGN_NONE
;
422 inst
->qpu
.branch
.bdi
= V3D_QPU_BRANCH_DEST_REL
;
423 inst
->qpu
.branch
.ub
= true;
424 inst
->qpu
.branch
.bdu
= V3D_QPU_BRANCH_DEST_REL
;
426 inst
->dst
= vir_reg(QFILE_NULL
, 0);
434 vir_emit(struct v3d_compile
*c
, struct qinst
*inst
)
436 switch (c
->cursor
.mode
) {
438 list_add(&inst
->link
, c
->cursor
.link
);
440 case vir_cursor_addtail
:
441 list_addtail(&inst
->link
, c
->cursor
.link
);
445 c
->cursor
= vir_after_inst(inst
);
446 c
->live_intervals_valid
= false;
449 /* Updates inst to write to a new temporary, emits it, and notes the def. */
451 vir_emit_def(struct v3d_compile
*c
, struct qinst
*inst
)
453 assert(inst
->dst
.file
== QFILE_NULL
);
455 /* If we're emitting an instruction that's a def, it had better be
456 * writing a register.
458 if (inst
->qpu
.type
== V3D_QPU_INSTR_TYPE_ALU
) {
459 assert(inst
->qpu
.alu
.add
.op
== V3D_QPU_A_NOP
||
460 v3d_qpu_add_op_has_dst(inst
->qpu
.alu
.add
.op
));
461 assert(inst
->qpu
.alu
.mul
.op
== V3D_QPU_M_NOP
||
462 v3d_qpu_mul_op_has_dst(inst
->qpu
.alu
.mul
.op
));
465 inst
->dst
= vir_get_temp(c
);
467 if (inst
->dst
.file
== QFILE_TEMP
)
468 c
->defs
[inst
->dst
.index
] = inst
;
476 vir_emit_nondef(struct v3d_compile
*c
, struct qinst
*inst
)
478 if (inst
->dst
.file
== QFILE_TEMP
)
479 c
->defs
[inst
->dst
.index
] = NULL
;
487 vir_new_block(struct v3d_compile
*c
)
489 struct qblock
*block
= rzalloc(c
, struct qblock
);
491 list_inithead(&block
->instructions
);
493 block
->predecessors
= _mesa_set_create(block
,
495 _mesa_key_pointer_equal
);
497 block
->index
= c
->next_block_index
++;
503 vir_set_emit_block(struct v3d_compile
*c
, struct qblock
*block
)
505 c
->cur_block
= block
;
506 c
->cursor
= vir_after_block(block
);
507 list_addtail(&block
->link
, &c
->blocks
);
511 vir_entry_block(struct v3d_compile
*c
)
513 return list_first_entry(&c
->blocks
, struct qblock
, link
);
517 vir_exit_block(struct v3d_compile
*c
)
519 return list_last_entry(&c
->blocks
, struct qblock
, link
);
523 vir_link_blocks(struct qblock
*predecessor
, struct qblock
*successor
)
525 _mesa_set_add(successor
->predecessors
, predecessor
);
526 if (predecessor
->successors
[0]) {
527 assert(!predecessor
->successors
[1]);
528 predecessor
->successors
[1] = successor
;
530 predecessor
->successors
[0] = successor
;
534 const struct v3d_compiler
*
535 v3d_compiler_init(const struct v3d_device_info
*devinfo
)
537 struct v3d_compiler
*compiler
= rzalloc(NULL
, struct v3d_compiler
);
541 compiler
->devinfo
= devinfo
;
543 if (!vir_init_reg_sets(compiler
)) {
544 ralloc_free(compiler
);
552 v3d_compiler_free(const struct v3d_compiler
*compiler
)
554 ralloc_free((void *)compiler
);
557 static struct v3d_compile
*
558 vir_compile_init(const struct v3d_compiler
*compiler
,
561 int program_id
, int variant_id
)
563 struct v3d_compile
*c
= rzalloc(NULL
, struct v3d_compile
);
565 c
->compiler
= compiler
;
566 c
->devinfo
= compiler
->devinfo
;
568 c
->program_id
= program_id
;
569 c
->variant_id
= variant_id
;
572 s
= nir_shader_clone(c
, s
);
575 list_inithead(&c
->blocks
);
576 vir_set_emit_block(c
, vir_new_block(c
));
578 c
->output_position_index
= -1;
579 c
->output_point_size_index
= -1;
580 c
->output_sample_mask_index
= -1;
582 c
->def_ht
= _mesa_hash_table_create(c
, _mesa_hash_pointer
,
583 _mesa_key_pointer_equal
);
589 v3d_lower_nir(struct v3d_compile
*c
)
591 struct nir_lower_tex_options tex_options
= {
593 .lower_rect
= false, /* XXX: Use this on V3D 3.x */
595 /* Apply swizzles to all samplers. */
596 .swizzle_result
= ~0,
599 /* Lower the format swizzle and (for 32-bit returns)
600 * ARB_texture_swizzle-style swizzle.
602 for (int i
= 0; i
< ARRAY_SIZE(c
->key
->tex
); i
++) {
603 for (int j
= 0; j
< 4; j
++)
604 tex_options
.swizzles
[i
][j
] = c
->key
->tex
[i
].swizzle
[j
];
606 if (c
->key
->tex
[i
].clamp_s
)
607 tex_options
.saturate_s
|= 1 << i
;
608 if (c
->key
->tex
[i
].clamp_t
)
609 tex_options
.saturate_t
|= 1 << i
;
610 if (c
->key
->tex
[i
].clamp_r
)
611 tex_options
.saturate_r
|= 1 << i
;
614 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
618 v3d_lower_nir_late(struct v3d_compile
*c
)
620 NIR_PASS_V(c
->s
, v3d_nir_lower_io
, c
);
621 NIR_PASS_V(c
->s
, v3d_nir_lower_txf_ms
, c
);
622 NIR_PASS_V(c
->s
, nir_lower_idiv
);
626 v3d_set_prog_data_uniforms(struct v3d_compile
*c
,
627 struct v3d_prog_data
*prog_data
)
629 int count
= c
->num_uniforms
;
630 struct v3d_uniform_list
*ulist
= &prog_data
->uniforms
;
632 ulist
->count
= count
;
633 ulist
->data
= ralloc_array(prog_data
, uint32_t, count
);
634 memcpy(ulist
->data
, c
->uniform_data
,
635 count
* sizeof(*ulist
->data
));
636 ulist
->contents
= ralloc_array(prog_data
, enum quniform_contents
, count
);
637 memcpy(ulist
->contents
, c
->uniform_contents
,
638 count
* sizeof(*ulist
->contents
));
641 /* Copy the compiler UBO range state to the compiled shader, dropping out
642 * arrays that were never referenced by an indirect load.
644 * (Note that QIR dead code elimination of an array access still leaves that
645 * array alive, though)
648 v3d_set_prog_data_ubo(struct v3d_compile
*c
,
649 struct v3d_prog_data
*prog_data
)
651 if (!c
->num_ubo_ranges
)
654 prog_data
->num_ubo_ranges
= 0;
655 prog_data
->ubo_ranges
= ralloc_array(prog_data
, struct v3d_ubo_range
,
657 for (int i
= 0; i
< c
->num_ubo_ranges
; i
++) {
658 if (!c
->ubo_range_used
[i
])
661 struct v3d_ubo_range
*range
= &c
->ubo_ranges
[i
];
662 prog_data
->ubo_ranges
[prog_data
->num_ubo_ranges
++] = *range
;
663 prog_data
->ubo_size
+= range
->size
;
666 if (prog_data
->ubo_size
) {
667 if (V3D_DEBUG
& V3D_DEBUG_SHADERDB
) {
668 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
669 vir_get_stage_name(c
),
670 c
->program_id
, c
->variant_id
,
671 prog_data
->ubo_size
/ 4);
677 v3d_set_prog_data(struct v3d_compile
*c
,
678 struct v3d_prog_data
*prog_data
)
680 prog_data
->threads
= c
->threads
;
681 prog_data
->single_seg
= !c
->last_thrsw
;
682 prog_data
->spill_size
= c
->spill_size
;
684 v3d_set_prog_data_uniforms(c
, prog_data
);
685 v3d_set_prog_data_ubo(c
, prog_data
);
689 v3d_return_qpu_insts(struct v3d_compile
*c
, uint32_t *final_assembly_size
)
691 *final_assembly_size
= c
->qpu_inst_count
* sizeof(uint64_t);
693 uint64_t *qpu_insts
= malloc(*final_assembly_size
);
697 memcpy(qpu_insts
, c
->qpu_insts
, *final_assembly_size
);
699 vir_compile_destroy(c
);
704 uint64_t *v3d_compile_vs(const struct v3d_compiler
*compiler
,
705 struct v3d_vs_key
*key
,
706 struct v3d_vs_prog_data
*prog_data
,
708 int program_id
, int variant_id
,
709 uint32_t *final_assembly_size
)
711 struct v3d_compile
*c
= vir_compile_init(compiler
, &key
->base
, s
,
712 program_id
, variant_id
);
718 if (key
->clamp_color
)
719 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
721 if (key
->base
.ucp_enables
) {
722 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, key
->base
.ucp_enables
);
723 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
,
727 /* Note: VS output scalarizing must happen after nir_lower_clip_vs. */
728 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
730 v3d_lower_nir_late(c
);
731 v3d_optimize_nir(c
->s
);
732 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
736 v3d_set_prog_data(c
, &prog_data
->base
);
738 prog_data
->base
.num_inputs
= c
->num_inputs
;
740 /* The vertex data gets format converted by the VPM so that
741 * each attribute channel takes up a VPM column. Precompute
742 * the sizes for the shader record.
744 for (int i
= 0; i
< ARRAY_SIZE(prog_data
->vattr_sizes
); i
++) {
745 prog_data
->vattr_sizes
[i
] = c
->vattr_sizes
[i
];
746 prog_data
->vpm_input_size
+= c
->vattr_sizes
[i
];
749 prog_data
->uses_vid
= (s
->info
.system_values_read
&
750 (1ull << SYSTEM_VALUE_VERTEX_ID
));
751 prog_data
->uses_iid
= (s
->info
.system_values_read
&
752 (1ull << SYSTEM_VALUE_INSTANCE_ID
));
754 if (prog_data
->uses_vid
)
755 prog_data
->vpm_input_size
++;
756 if (prog_data
->uses_iid
)
757 prog_data
->vpm_input_size
++;
759 /* Input/output segment size are in 8x32-bit multiples. */
760 prog_data
->vpm_input_size
= align(prog_data
->vpm_input_size
, 8) / 8;
761 prog_data
->vpm_output_size
= align(c
->num_vpm_writes
, 8) / 8;
763 return v3d_return_qpu_insts(c
, final_assembly_size
);
767 v3d_set_fs_prog_data_inputs(struct v3d_compile
*c
,
768 struct v3d_fs_prog_data
*prog_data
)
770 prog_data
->base
.num_inputs
= c
->num_inputs
;
771 memcpy(prog_data
->input_slots
, c
->input_slots
,
772 c
->num_inputs
* sizeof(*c
->input_slots
));
774 STATIC_ASSERT(ARRAY_SIZE(prog_data
->flat_shade_flags
) >
775 (V3D_MAX_FS_INPUTS
- 1) / 24);
776 for (int i
= 0; i
< V3D_MAX_FS_INPUTS
; i
++) {
777 if (BITSET_TEST(c
->flat_shade_flags
, i
))
778 prog_data
->flat_shade_flags
[i
/ 24] |= 1 << (i
% 24);
780 if (BITSET_TEST(c
->noperspective_flags
, i
))
781 prog_data
->noperspective_flags
[i
/ 24] |= 1 << (i
% 24);
783 if (BITSET_TEST(c
->centroid_flags
, i
))
784 prog_data
->centroid_flags
[i
/ 24] |= 1 << (i
% 24);
789 v3d_fixup_fs_output_types(struct v3d_compile
*c
)
791 nir_foreach_variable(var
, &c
->s
->outputs
) {
794 switch (var
->data
.location
) {
795 case FRAG_RESULT_COLOR
:
798 case FRAG_RESULT_DATA0
:
799 case FRAG_RESULT_DATA1
:
800 case FRAG_RESULT_DATA2
:
801 case FRAG_RESULT_DATA3
:
802 mask
= 1 << (var
->data
.location
- FRAG_RESULT_DATA0
);
806 if (c
->fs_key
->int_color_rb
& mask
) {
808 glsl_vector_type(GLSL_TYPE_INT
,
809 glsl_get_components(var
->type
));
810 } else if (c
->fs_key
->uint_color_rb
& mask
) {
812 glsl_vector_type(GLSL_TYPE_UINT
,
813 glsl_get_components(var
->type
));
818 uint64_t *v3d_compile_fs(const struct v3d_compiler
*compiler
,
819 struct v3d_fs_key
*key
,
820 struct v3d_fs_prog_data
*prog_data
,
822 int program_id
, int variant_id
,
823 uint32_t *final_assembly_size
)
825 struct v3d_compile
*c
= vir_compile_init(compiler
, &key
->base
, s
,
826 program_id
, variant_id
);
830 if (key
->int_color_rb
|| key
->uint_color_rb
)
831 v3d_fixup_fs_output_types(c
);
835 if (key
->light_twoside
)
836 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
838 if (key
->clamp_color
)
839 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
841 if (key
->alpha_test
) {
842 NIR_PASS_V(c
->s
, nir_lower_alpha_test
, key
->alpha_test_func
,
846 if (key
->base
.ucp_enables
)
847 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, key
->base
.ucp_enables
);
849 /* Note: FS input scalarizing must happen after
850 * nir_lower_two_sided_color, which only handles a vec4 at a time.
852 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_in
);
854 v3d_lower_nir_late(c
);
855 v3d_optimize_nir(c
->s
);
856 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
860 v3d_set_prog_data(c
, &prog_data
->base
);
861 v3d_set_fs_prog_data_inputs(c
, prog_data
);
862 prog_data
->writes_z
= (c
->s
->info
.outputs_written
&
863 (1 << FRAG_RESULT_DEPTH
));
864 prog_data
->discard
= (c
->s
->info
.fs
.uses_discard
||
865 c
->fs_key
->sample_alpha_to_coverage
);
866 prog_data
->uses_center_w
= c
->uses_center_w
;
868 return v3d_return_qpu_insts(c
, final_assembly_size
);
872 vir_remove_instruction(struct v3d_compile
*c
, struct qinst
*qinst
)
874 if (qinst
->dst
.file
== QFILE_TEMP
)
875 c
->defs
[qinst
->dst
.index
] = NULL
;
877 assert(&qinst
->link
!= c
->cursor
.link
);
879 list_del(&qinst
->link
);
882 c
->live_intervals_valid
= false;
886 vir_follow_movs(struct v3d_compile
*c
, struct qreg reg
)
891 while (reg.file == QFILE_TEMP &&
892 c->defs[reg.index] &&
893 (c->defs[reg.index]->op == QOP_MOV ||
894 c->defs[reg.index]->op == QOP_FMOV) &&
895 !c->defs[reg.index]->dst.pack &&
896 !c->defs[reg.index]->src[0].pack) {
897 reg = c->defs[reg.index]->src[0];
906 vir_compile_destroy(struct v3d_compile
*c
)
908 /* Defuse the assert that we aren't removing the cursor's instruction.
910 c
->cursor
.link
= NULL
;
912 vir_for_each_block(block
, c
) {
913 while (!list_empty(&block
->instructions
)) {
914 struct qinst
*qinst
=
915 list_first_entry(&block
->instructions
,
917 vir_remove_instruction(c
, qinst
);
925 vir_uniform(struct v3d_compile
*c
,
926 enum quniform_contents contents
,
929 for (int i
= 0; i
< c
->num_uniforms
; i
++) {
930 if (c
->uniform_contents
[i
] == contents
&&
931 c
->uniform_data
[i
] == data
) {
932 return vir_reg(QFILE_UNIF
, i
);
936 uint32_t uniform
= c
->num_uniforms
++;
938 if (uniform
>= c
->uniform_array_size
) {
939 c
->uniform_array_size
= MAX2(MAX2(16, uniform
+ 1),
940 c
->uniform_array_size
* 2);
942 c
->uniform_data
= reralloc(c
, c
->uniform_data
,
944 c
->uniform_array_size
);
945 c
->uniform_contents
= reralloc(c
, c
->uniform_contents
,
946 enum quniform_contents
,
947 c
->uniform_array_size
);
950 c
->uniform_contents
[uniform
] = contents
;
951 c
->uniform_data
[uniform
] = data
;
953 return vir_reg(QFILE_UNIF
, uniform
);
957 vir_can_set_flags(struct v3d_compile
*c
, struct qinst
*inst
)
959 if (c
->devinfo
->ver
>= 40 && (v3d_qpu_reads_vpm(&inst
->qpu
) ||
960 v3d_qpu_uses_sfu(&inst
->qpu
))) {
968 vir_PF(struct v3d_compile
*c
, struct qreg src
, enum v3d_qpu_pf pf
)
970 struct qinst
*last_inst
= NULL
;
972 if (!list_empty(&c
->cur_block
->instructions
)) {
973 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
975 /* Can't stuff the PF into the last last inst if our cursor
976 * isn't pointing after it.
978 struct vir_cursor after_inst
= vir_after_inst(last_inst
);
979 if (c
->cursor
.mode
!= after_inst
.mode
||
980 c
->cursor
.link
!= after_inst
.link
)
984 if (src
.file
!= QFILE_TEMP
||
985 !c
->defs
[src
.index
] ||
986 last_inst
!= c
->defs
[src
.index
] ||
987 !vir_can_set_flags(c
, last_inst
)) {
988 /* XXX: Make the MOV be the appropriate type */
989 last_inst
= vir_MOV_dest(c
, vir_reg(QFILE_NULL
, 0), src
);
992 vir_set_pf(last_inst
, pf
);
995 #define OPTPASS(func) \
997 bool stage_progress = func(c); \
998 if (stage_progress) { \
1000 if (print_opt_debug) { \
1002 "VIR opt pass %2d: %s progress\n", \
1005 /*XXX vir_validate(c);*/ \
1010 vir_optimize(struct v3d_compile
*c
)
1012 bool print_opt_debug
= false;
1016 bool progress
= false;
1018 OPTPASS(vir_opt_copy_propagate
);
1019 OPTPASS(vir_opt_dead_code
);
1020 OPTPASS(vir_opt_small_immediates
);
1030 vir_get_stage_name(struct v3d_compile
*c
)
1032 if (c
->vs_key
&& c
->vs_key
->is_coord
)
1033 return "MESA_SHADER_COORD";
1035 return gl_shader_stage_name(c
->s
->info
.stage
);