2 * Copyright © 2016-2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "broadcom/common/v3d_device_info.h"
25 #include "v3d_compiler.h"
27 /* Prints a human-readable description of the uniform reference. */
29 vir_dump_uniform(enum quniform_contents contents
,
32 static const char *quniform_names
[] = {
33 [QUNIFORM_ALPHA_REF
] = "alpha_ref",
34 [QUNIFORM_VIEWPORT_X_SCALE
] = "vp_x_scale",
35 [QUNIFORM_VIEWPORT_Y_SCALE
] = "vp_y_scale",
36 [QUNIFORM_VIEWPORT_Z_OFFSET
] = "vp_z_offset",
37 [QUNIFORM_VIEWPORT_Z_SCALE
] = "vp_z_scale",
38 [QUNIFORM_SHARED_OFFSET
] = "shared_offset",
42 case QUNIFORM_CONSTANT
:
43 fprintf(stderr
, "0x%08x / %f", data
, uif(data
));
46 case QUNIFORM_UNIFORM
:
47 fprintf(stderr
, "push[%d]", data
);
50 case QUNIFORM_TEXTURE_CONFIG_P1
:
51 fprintf(stderr
, "tex[%d].p1", data
);
54 case QUNIFORM_TMU_CONFIG_P0
:
55 fprintf(stderr
, "tex[%d].p0 | 0x%x",
56 v3d_tmu_config_data_get_unit(data
),
57 v3d_tmu_config_data_get_value(data
));
60 case QUNIFORM_TMU_CONFIG_P1
:
61 fprintf(stderr
, "tex[%d].p1 | 0x%x",
62 v3d_tmu_config_data_get_unit(data
),
63 v3d_tmu_config_data_get_value(data
));
66 case QUNIFORM_IMAGE_TMU_CONFIG_P0
:
67 fprintf(stderr
, "img[%d].p0 | 0x%x",
68 v3d_tmu_config_data_get_unit(data
),
69 v3d_tmu_config_data_get_value(data
));
72 case QUNIFORM_TEXTURE_WIDTH
:
73 fprintf(stderr
, "tex[%d].width", data
);
75 case QUNIFORM_TEXTURE_HEIGHT
:
76 fprintf(stderr
, "tex[%d].height", data
);
78 case QUNIFORM_TEXTURE_DEPTH
:
79 fprintf(stderr
, "tex[%d].depth", data
);
81 case QUNIFORM_TEXTURE_ARRAY_SIZE
:
82 fprintf(stderr
, "tex[%d].array_size", data
);
84 case QUNIFORM_TEXTURE_LEVELS
:
85 fprintf(stderr
, "tex[%d].levels", data
);
88 case QUNIFORM_IMAGE_WIDTH
:
89 fprintf(stderr
, "img[%d].width", data
);
91 case QUNIFORM_IMAGE_HEIGHT
:
92 fprintf(stderr
, "img[%d].height", data
);
94 case QUNIFORM_IMAGE_DEPTH
:
95 fprintf(stderr
, "img[%d].depth", data
);
97 case QUNIFORM_IMAGE_ARRAY_SIZE
:
98 fprintf(stderr
, "img[%d].array_size", data
);
101 case QUNIFORM_UBO_ADDR
:
102 fprintf(stderr
, "ubo[%d]", data
);
105 case QUNIFORM_SSBO_OFFSET
:
106 fprintf(stderr
, "ssbo[%d]", data
);
109 case QUNIFORM_GET_BUFFER_SIZE
:
110 fprintf(stderr
, "ssbo_size[%d]", data
);
113 case QUNIFORM_NUM_WORK_GROUPS
:
114 fprintf(stderr
, "num_wg.%c", data
< 3 ? "xyz"[data
] : '?');
118 if (quniform_contents_is_texture_p0(contents
)) {
119 fprintf(stderr
, "tex[%d].p0: 0x%08x",
120 contents
- QUNIFORM_TEXTURE_CONFIG_P0_0
,
122 } else if (contents
< ARRAY_SIZE(quniform_names
) &&
123 quniform_names
[contents
]) {
124 fprintf(stderr
, "%s",
125 quniform_names
[contents
]);
127 fprintf(stderr
, "%d / 0x%08x", contents
, data
);
133 vir_print_reg(struct v3d_compile
*c
, const struct qinst
*inst
,
136 static const char *files
[] = {
140 [QFILE_TLBU
] = "tlbu",
146 fprintf(stderr
, "null");
150 fprintf(stderr
, "0x%08x (%f)", reg
.index
, uif(reg
.index
));
154 fprintf(stderr
, "rf%d", reg
.index
);
158 fprintf(stderr
, "%s", v3d_qpu_magic_waddr_name(reg
.index
));
161 case QFILE_SMALL_IMM
: {
163 bool ok
= v3d_qpu_small_imm_unpack(c
->devinfo
,
166 assert(ok
); (void) ok
;
168 if ((int)inst
->qpu
.raddr_b
>= -16 &&
169 (int)inst
->qpu
.raddr_b
<= 15)
170 fprintf(stderr
, "%d", unpacked
);
172 fprintf(stderr
, "%f", uif(unpacked
));
177 fprintf(stderr
, "vpm%d.%d",
178 reg
.index
/ 4, reg
.index
% 4);
183 fprintf(stderr
, "%s", files
[reg
.file
]);
187 fprintf(stderr
, "%s%d", files
[reg
.file
], reg
.index
);
188 fprintf(stderr
, " (");
189 vir_dump_uniform(c
->uniform_contents
[reg
.index
],
190 c
->uniform_data
[reg
.index
]);
191 fprintf(stderr
, ")");
195 fprintf(stderr
, "%s%d", files
[reg
.file
], reg
.index
);
201 vir_dump_sig_addr(const struct v3d_device_info
*devinfo
,
202 const struct v3d_qpu_instr
*instr
)
204 if (devinfo
->ver
< 41)
207 if (!instr
->sig_magic
)
208 fprintf(stderr
, ".rf%d", instr
->sig_addr
);
210 const char *name
= v3d_qpu_magic_waddr_name(instr
->sig_addr
);
212 fprintf(stderr
, ".%s", name
);
214 fprintf(stderr
, ".UNKNOWN%d", instr
->sig_addr
);
219 vir_dump_sig(struct v3d_compile
*c
, struct qinst
*inst
)
221 struct v3d_qpu_sig
*sig
= &inst
->qpu
.sig
;
224 fprintf(stderr
, "; thrsw");
226 fprintf(stderr
, "; ldvary");
227 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
230 fprintf(stderr
, "; ldvpm");
232 fprintf(stderr
, "; ldtmu");
233 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
236 fprintf(stderr
, "; ldtlb");
237 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
240 fprintf(stderr
, "; ldtlbu");
241 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
244 fprintf(stderr
, "; ldunif");
246 fprintf(stderr
, "; ldunifrf");
247 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
250 fprintf(stderr
, "; ldunifa");
251 if (sig
->ldunifarf
) {
252 fprintf(stderr
, "; ldunifarf");
253 vir_dump_sig_addr(c
->devinfo
, &inst
->qpu
);
256 fprintf(stderr
, "; wrtmuc");
260 vir_dump_alu(struct v3d_compile
*c
, struct qinst
*inst
)
262 struct v3d_qpu_instr
*instr
= &inst
->qpu
;
263 int nsrc
= vir_get_non_sideband_nsrc(inst
);
264 int sideband_nsrc
= vir_get_nsrc(inst
);
265 enum v3d_qpu_input_unpack unpack
[2];
267 if (inst
->qpu
.alu
.add
.op
!= V3D_QPU_A_NOP
) {
268 fprintf(stderr
, "%s", v3d_qpu_add_op_name(instr
->alu
.add
.op
));
269 fprintf(stderr
, "%s", v3d_qpu_cond_name(instr
->flags
.ac
));
270 fprintf(stderr
, "%s", v3d_qpu_pf_name(instr
->flags
.apf
));
271 fprintf(stderr
, "%s", v3d_qpu_uf_name(instr
->flags
.auf
));
272 fprintf(stderr
, " ");
274 vir_print_reg(c
, inst
, inst
->dst
);
275 fprintf(stderr
, "%s", v3d_qpu_pack_name(instr
->alu
.add
.output_pack
));
277 unpack
[0] = instr
->alu
.add
.a_unpack
;
278 unpack
[1] = instr
->alu
.add
.b_unpack
;
280 fprintf(stderr
, "%s", v3d_qpu_mul_op_name(instr
->alu
.mul
.op
));
281 fprintf(stderr
, "%s", v3d_qpu_cond_name(instr
->flags
.mc
));
282 fprintf(stderr
, "%s", v3d_qpu_pf_name(instr
->flags
.mpf
));
283 fprintf(stderr
, "%s", v3d_qpu_uf_name(instr
->flags
.muf
));
284 fprintf(stderr
, " ");
286 vir_print_reg(c
, inst
, inst
->dst
);
287 fprintf(stderr
, "%s", v3d_qpu_pack_name(instr
->alu
.mul
.output_pack
));
289 unpack
[0] = instr
->alu
.mul
.a_unpack
;
290 unpack
[1] = instr
->alu
.mul
.b_unpack
;
293 for (int i
= 0; i
< sideband_nsrc
; i
++) {
294 fprintf(stderr
, ", ");
295 vir_print_reg(c
, inst
, inst
->src
[i
]);
297 fprintf(stderr
, "%s", v3d_qpu_unpack_name(unpack
[i
]));
300 vir_dump_sig(c
, inst
);
304 vir_dump_inst(struct v3d_compile
*c
, struct qinst
*inst
)
306 struct v3d_qpu_instr
*instr
= &inst
->qpu
;
308 switch (inst
->qpu
.type
) {
309 case V3D_QPU_INSTR_TYPE_ALU
:
310 vir_dump_alu(c
, inst
);
312 case V3D_QPU_INSTR_TYPE_BRANCH
:
313 fprintf(stderr
, "b");
314 if (instr
->branch
.ub
)
315 fprintf(stderr
, "u");
317 fprintf(stderr
, "%s",
318 v3d_qpu_branch_cond_name(instr
->branch
.cond
));
319 fprintf(stderr
, "%s", v3d_qpu_msfign_name(instr
->branch
.msfign
));
321 switch (instr
->branch
.bdi
) {
322 case V3D_QPU_BRANCH_DEST_ABS
:
323 fprintf(stderr
, " zero_addr+0x%08x", instr
->branch
.offset
);
326 case V3D_QPU_BRANCH_DEST_REL
:
327 fprintf(stderr
, " %d", instr
->branch
.offset
);
330 case V3D_QPU_BRANCH_DEST_LINK_REG
:
331 fprintf(stderr
, " lri");
334 case V3D_QPU_BRANCH_DEST_REGFILE
:
335 fprintf(stderr
, " rf%d", instr
->branch
.raddr_a
);
339 if (instr
->branch
.ub
) {
340 switch (instr
->branch
.bdu
) {
341 case V3D_QPU_BRANCH_DEST_ABS
:
342 fprintf(stderr
, ", a:unif");
345 case V3D_QPU_BRANCH_DEST_REL
:
346 fprintf(stderr
, ", r:unif");
349 case V3D_QPU_BRANCH_DEST_LINK_REG
:
350 fprintf(stderr
, ", lri");
353 case V3D_QPU_BRANCH_DEST_REGFILE
:
354 fprintf(stderr
, ", rf%d", instr
->branch
.raddr_a
);
359 if (vir_has_implicit_uniform(inst
)) {
360 fprintf(stderr
, " ");
361 vir_print_reg(c
, inst
, inst
->src
[vir_get_implicit_uniform_src(inst
)]);
369 vir_dump(struct v3d_compile
*c
)
373 vir_for_each_block(block
, c
) {
374 fprintf(stderr
, "BLOCK %d:\n", block
->index
);
375 vir_for_each_inst(inst
, block
) {
376 if (c
->live_intervals_valid
) {
379 for (int i
= 0; i
< c
->num_temps
; i
++) {
380 if (c
->temp_start
[i
] != ip
)
386 fprintf(stderr
, ", ");
388 fprintf(stderr
, "S%4d", i
);
392 fprintf(stderr
, " ");
394 fprintf(stderr
, " ");
397 if (c
->live_intervals_valid
) {
400 for (int i
= 0; i
< c
->num_temps
; i
++) {
401 if (c
->temp_end
[i
] != ip
)
407 fprintf(stderr
, ", ");
409 fprintf(stderr
, "E%4d", i
);
413 fprintf(stderr
, " ");
415 fprintf(stderr
, " ");
418 vir_dump_inst(c
, inst
);
419 fprintf(stderr
, "\n");
422 if (block
->successors
[1]) {
423 fprintf(stderr
, "-> BLOCK %d, %d\n",
424 block
->successors
[0]->index
,
425 block
->successors
[1]->index
);
426 } else if (block
->successors
[0]) {
427 fprintf(stderr
, "-> BLOCK %d\n",
428 block
->successors
[0]->index
);