2 * Copyright © 2016 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 * Definitions of the unpacked form of QPU instructions. Assembly and
28 * disassembly will use this for talking about instructions, with qpu_encode.c
29 * and qpu_decode.c handling the pack and unpack of the actual 64-bit QPU
38 #include "util/macros.h"
40 struct v3d_device_info
;
97 /* 6 is reserved, but note 3.2.2.8: "Result Writes" */
98 V3D_QPU_WADDR_NOP
= 6,
99 V3D_QPU_WADDR_TLB
= 7,
100 V3D_QPU_WADDR_TLBU
= 8,
101 V3D_QPU_WADDR_TMU
= 9,
102 V3D_QPU_WADDR_TMUL
= 10,
103 V3D_QPU_WADDR_TMUD
= 11,
104 V3D_QPU_WADDR_TMUA
= 12,
105 V3D_QPU_WADDR_TMUAU
= 13,
106 V3D_QPU_WADDR_VPM
= 14,
107 V3D_QPU_WADDR_VPMU
= 15,
108 V3D_QPU_WADDR_SYNC
= 16,
109 V3D_QPU_WADDR_SYNCU
= 17,
110 V3D_QPU_WADDR_SYNCB
= 18,
111 V3D_QPU_WADDR_RECIP
= 19,
112 V3D_QPU_WADDR_RSQRT
= 20,
113 V3D_QPU_WADDR_EXP
= 21,
114 V3D_QPU_WADDR_LOG
= 22,
115 V3D_QPU_WADDR_SIN
= 23,
116 V3D_QPU_WADDR_RSQRT2
= 24,
117 V3D_QPU_WADDR_TMUC
= 32,
118 V3D_QPU_WADDR_TMUS
= 33,
119 V3D_QPU_WADDR_TMUT
= 34,
120 V3D_QPU_WADDR_TMUR
= 35,
121 V3D_QPU_WADDR_TMUI
= 36,
122 V3D_QPU_WADDR_TMUB
= 37,
123 V3D_QPU_WADDR_TMUDREF
= 38,
124 V3D_QPU_WADDR_TMUOFF
= 39,
125 V3D_QPU_WADDR_TMUSCM
= 40,
126 V3D_QPU_WADDR_TMUSF
= 41,
127 V3D_QPU_WADDR_TMUSLOD
= 42,
128 V3D_QPU_WADDR_TMUHS
= 43,
129 V3D_QPU_WADDR_TMUHSCM
= 44,
130 V3D_QPU_WADDR_TMUHSF
= 45,
131 V3D_QPU_WADDR_TMUHSLOD
= 46,
132 V3D_QPU_WADDR_R5REP
= 55,
135 struct v3d_qpu_flags
{
136 enum v3d_qpu_cond ac
, mc
;
137 enum v3d_qpu_pf apf
, mpf
;
138 enum v3d_qpu_uf auf
, muf
;
141 enum v3d_qpu_add_op
{
193 V3D_QPU_A_LDVPMV_OUT
,
195 V3D_QPU_A_LDVPMD_OUT
,
198 V3D_QPU_A_LDVPMG_OUT
,
219 enum v3d_qpu_mul_op
{
232 enum v3d_qpu_output_pack
{
235 * Convert to 16-bit float, put in low 16 bits of destination leaving
240 * Convert to 16-bit float, put in high 16 bits of destination leaving
246 enum v3d_qpu_input_unpack
{
248 * No-op input unpacking. Note that this enum's value doesn't match
249 * the packed QPU instruction value of the field (we use 0 so that the
250 * default on new instruction creation is no-op).
253 /** Absolute value. Only available for some operations. */
255 /** Convert low 16 bits from 16-bit float to 32-bit float. */
257 /** Convert high 16 bits from 16-bit float to 32-bit float. */
260 /** Convert to 16f and replicate it to the high bits. */
261 V3D_QPU_UNPACK_REPLICATE_32F_16
,
263 /** Replicate low 16 bits to high */
264 V3D_QPU_UNPACK_REPLICATE_L_16
,
266 /** Replicate high 16 bits to low */
267 V3D_QPU_UNPACK_REPLICATE_H_16
,
269 /** Swap high and low 16 bits */
270 V3D_QPU_UNPACK_SWAP_16
,
284 struct v3d_qpu_alu_instr
{
286 enum v3d_qpu_add_op op
;
287 enum v3d_qpu_mux a
, b
;
290 enum v3d_qpu_output_pack output_pack
;
291 enum v3d_qpu_input_unpack a_unpack
;
292 enum v3d_qpu_input_unpack b_unpack
;
296 enum v3d_qpu_mul_op op
;
297 enum v3d_qpu_mux a
, b
;
300 enum v3d_qpu_output_pack output_pack
;
301 enum v3d_qpu_input_unpack a_unpack
;
302 enum v3d_qpu_input_unpack b_unpack
;
306 enum v3d_qpu_branch_cond
{
307 V3D_QPU_BRANCH_COND_ALWAYS
,
308 V3D_QPU_BRANCH_COND_A0
,
309 V3D_QPU_BRANCH_COND_NA0
,
310 V3D_QPU_BRANCH_COND_ALLA
,
311 V3D_QPU_BRANCH_COND_ANYNA
,
312 V3D_QPU_BRANCH_COND_ANYA
,
313 V3D_QPU_BRANCH_COND_ALLNA
,
316 enum v3d_qpu_msfign
{
317 /** Ignore multisample flags when determining branch condition. */
320 * If no multisample flags are set in the lane (a pixel in the FS, a
321 * vertex in the VS), ignore the lane's condition when computing the
326 * If no multisample flags are set in a 2x2 quad in the FS, ignore the
327 * quad's a/b conditions.
332 enum v3d_qpu_branch_dest
{
333 V3D_QPU_BRANCH_DEST_ABS
,
334 V3D_QPU_BRANCH_DEST_REL
,
335 V3D_QPU_BRANCH_DEST_LINK_REG
,
336 V3D_QPU_BRANCH_DEST_REGFILE
,
339 struct v3d_qpu_branch_instr
{
340 enum v3d_qpu_branch_cond cond
;
341 enum v3d_qpu_msfign msfign
;
343 /** Selects how to compute the new IP if the branch is taken. */
344 enum v3d_qpu_branch_dest bdi
;
347 * Selects how to compute the new uniforms pointer if the branch is
348 * taken. (ABS/REL implicitly load a uniform and use that)
350 enum v3d_qpu_branch_dest bdu
;
353 * If set, then udest determines how the uniform stream will branch,
354 * otherwise the uniform stream is left as is.
363 enum v3d_qpu_instr_type
{
364 V3D_QPU_INSTR_TYPE_ALU
,
365 V3D_QPU_INSTR_TYPE_BRANCH
,
368 struct v3d_qpu_instr
{
369 enum v3d_qpu_instr_type type
;
371 struct v3d_qpu_sig sig
;
373 bool sig_magic
; /* If the signal writes to a magic address */
376 struct v3d_qpu_flags flags
;
379 struct v3d_qpu_alu_instr alu
;
380 struct v3d_qpu_branch_instr branch
;
384 const char *v3d_qpu_magic_waddr_name(enum v3d_qpu_waddr waddr
);
385 const char *v3d_qpu_add_op_name(enum v3d_qpu_add_op op
);
386 const char *v3d_qpu_mul_op_name(enum v3d_qpu_mul_op op
);
387 const char *v3d_qpu_cond_name(enum v3d_qpu_cond cond
);
388 const char *v3d_qpu_pf_name(enum v3d_qpu_pf pf
);
389 const char *v3d_qpu_uf_name(enum v3d_qpu_uf uf
);
390 const char *v3d_qpu_pack_name(enum v3d_qpu_output_pack pack
);
391 const char *v3d_qpu_unpack_name(enum v3d_qpu_input_unpack unpack
);
392 const char *v3d_qpu_branch_cond_name(enum v3d_qpu_branch_cond cond
);
393 const char *v3d_qpu_msfign_name(enum v3d_qpu_msfign msfign
);
395 bool v3d_qpu_add_op_has_dst(enum v3d_qpu_add_op op
);
396 bool v3d_qpu_mul_op_has_dst(enum v3d_qpu_mul_op op
);
397 int v3d_qpu_add_op_num_src(enum v3d_qpu_add_op op
);
398 int v3d_qpu_mul_op_num_src(enum v3d_qpu_mul_op op
);
400 bool v3d_qpu_sig_pack(const struct v3d_device_info
*devinfo
,
401 const struct v3d_qpu_sig
*sig
,
402 uint32_t *packed_sig
);
403 bool v3d_qpu_sig_unpack(const struct v3d_device_info
*devinfo
,
405 struct v3d_qpu_sig
*sig
);
408 v3d_qpu_flags_pack(const struct v3d_device_info
*devinfo
,
409 const struct v3d_qpu_flags
*cond
,
410 uint32_t *packed_cond
);
412 v3d_qpu_flags_unpack(const struct v3d_device_info
*devinfo
,
413 uint32_t packed_cond
,
414 struct v3d_qpu_flags
*cond
);
417 v3d_qpu_small_imm_pack(const struct v3d_device_info
*devinfo
,
419 uint32_t *packed_small_immediate
);
422 v3d_qpu_small_imm_unpack(const struct v3d_device_info
*devinfo
,
423 uint32_t packed_small_immediate
,
424 uint32_t *small_immediate
);
427 v3d_qpu_instr_pack(const struct v3d_device_info
*devinfo
,
428 const struct v3d_qpu_instr
*instr
,
429 uint64_t *packed_instr
);
431 v3d_qpu_instr_unpack(const struct v3d_device_info
*devinfo
,
432 uint64_t packed_instr
,
433 struct v3d_qpu_instr
*instr
);
435 bool v3d_qpu_magic_waddr_is_sfu(enum v3d_qpu_waddr waddr
) ATTRIBUTE_CONST
;
436 bool v3d_qpu_magic_waddr_is_tmu(enum v3d_qpu_waddr waddr
) ATTRIBUTE_CONST
;
437 bool v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr
) ATTRIBUTE_CONST
;
438 bool v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr
) ATTRIBUTE_CONST
;
439 bool v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr
) ATTRIBUTE_CONST
;
440 bool v3d_qpu_uses_tlb(const struct v3d_qpu_instr
*inst
) ATTRIBUTE_CONST
;
441 bool v3d_qpu_writes_tmu(const struct v3d_qpu_instr
*inst
) ATTRIBUTE_CONST
;
442 bool v3d_qpu_writes_r3(const struct v3d_device_info
*devinfo
,
443 const struct v3d_qpu_instr
*instr
) ATTRIBUTE_CONST
;
444 bool v3d_qpu_writes_r4(const struct v3d_device_info
*devinfo
,
445 const struct v3d_qpu_instr
*instr
) ATTRIBUTE_CONST
;
446 bool v3d_qpu_writes_r5(const struct v3d_device_info
*devinfo
,
447 const struct v3d_qpu_instr
*instr
) ATTRIBUTE_CONST
;
448 bool v3d_qpu_uses_mux(const struct v3d_qpu_instr
*inst
, enum v3d_qpu_mux mux
);
449 bool v3d_qpu_uses_vpm(const struct v3d_qpu_instr
*inst
) ATTRIBUTE_CONST
;
450 bool v3d_qpu_reads_vpm(const struct v3d_qpu_instr
*inst
) ATTRIBUTE_CONST
;
451 bool v3d_qpu_writes_vpm(const struct v3d_qpu_instr
*inst
) ATTRIBUTE_CONST
;
452 bool v3d_qpu_sig_writes_address(const struct v3d_device_info
*devinfo
,
453 const struct v3d_qpu_sig
*sig
) ATTRIBUTE_CONST
;