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[mesa.git] / src / broadcom / qpu / qpu_pack.c
1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <string.h>
25 #include "util/macros.h"
26
27 #include "broadcom/common/v3d_device_info.h"
28 #include "qpu_instr.h"
29
30 #ifndef QPU_MASK
31 #define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
32 /* Using the GNU statement expression extension */
33 #define QPU_SET_FIELD(value, field) \
34 ({ \
35 uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
36 assert((fieldval & ~ field ## _MASK) == 0); \
37 fieldval & field ## _MASK; \
38 })
39
40 #define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT))
41
42 #define QPU_UPDATE_FIELD(inst, value, field) \
43 (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
44 #endif /* QPU_MASK */
45
46 #define VC5_QPU_OP_MUL_SHIFT 58
47 #define VC5_QPU_OP_MUL_MASK QPU_MASK(63, 58)
48
49 #define VC5_QPU_SIG_SHIFT 53
50 #define VC5_QPU_SIG_MASK QPU_MASK(57, 53)
51
52 #define VC5_QPU_COND_SHIFT 46
53 #define VC5_QPU_COND_MASK QPU_MASK(52, 46)
54 #define VC5_QPU_COND_SIG_MAGIC_ADDR (1 << 6)
55
56 #define VC5_QPU_MM QPU_MASK(45, 45)
57 #define VC5_QPU_MA QPU_MASK(44, 44)
58
59 #define V3D_QPU_WADDR_M_SHIFT 38
60 #define V3D_QPU_WADDR_M_MASK QPU_MASK(43, 38)
61
62 #define VC5_QPU_BRANCH_ADDR_LOW_SHIFT 35
63 #define VC5_QPU_BRANCH_ADDR_LOW_MASK QPU_MASK(55, 35)
64
65 #define V3D_QPU_WADDR_A_SHIFT 32
66 #define V3D_QPU_WADDR_A_MASK QPU_MASK(37, 32)
67
68 #define VC5_QPU_BRANCH_COND_SHIFT 32
69 #define VC5_QPU_BRANCH_COND_MASK QPU_MASK(34, 32)
70
71 #define VC5_QPU_BRANCH_ADDR_HIGH_SHIFT 24
72 #define VC5_QPU_BRANCH_ADDR_HIGH_MASK QPU_MASK(31, 24)
73
74 #define VC5_QPU_OP_ADD_SHIFT 24
75 #define VC5_QPU_OP_ADD_MASK QPU_MASK(31, 24)
76
77 #define VC5_QPU_MUL_B_SHIFT 21
78 #define VC5_QPU_MUL_B_MASK QPU_MASK(23, 21)
79
80 #define VC5_QPU_BRANCH_MSFIGN_SHIFT 21
81 #define VC5_QPU_BRANCH_MSFIGN_MASK QPU_MASK(22, 21)
82
83 #define VC5_QPU_MUL_A_SHIFT 18
84 #define VC5_QPU_MUL_A_MASK QPU_MASK(20, 18)
85
86 #define VC5_QPU_ADD_B_SHIFT 15
87 #define VC5_QPU_ADD_B_MASK QPU_MASK(17, 15)
88
89 #define VC5_QPU_BRANCH_BDU_SHIFT 15
90 #define VC5_QPU_BRANCH_BDU_MASK QPU_MASK(17, 15)
91
92 #define VC5_QPU_BRANCH_UB QPU_MASK(14, 14)
93
94 #define VC5_QPU_ADD_A_SHIFT 12
95 #define VC5_QPU_ADD_A_MASK QPU_MASK(14, 12)
96
97 #define VC5_QPU_BRANCH_BDI_SHIFT 12
98 #define VC5_QPU_BRANCH_BDI_MASK QPU_MASK(13, 12)
99
100 #define VC5_QPU_RADDR_A_SHIFT 6
101 #define VC5_QPU_RADDR_A_MASK QPU_MASK(11, 6)
102
103 #define VC5_QPU_RADDR_B_SHIFT 0
104 #define VC5_QPU_RADDR_B_MASK QPU_MASK(5, 0)
105
106 #define THRSW .thrsw = true
107 #define LDUNIF .ldunif = true
108 #define LDUNIFRF .ldunifrf = true
109 #define LDUNIFA .ldunifa = true
110 #define LDUNIFARF .ldunifarf = true
111 #define LDTMU .ldtmu = true
112 #define LDVARY .ldvary = true
113 #define LDVPM .ldvpm = true
114 #define SMIMM .small_imm = true
115 #define LDTLB .ldtlb = true
116 #define LDTLBU .ldtlbu = true
117 #define UCB .ucb = true
118 #define ROT .rotate = true
119 #define WRTMUC .wrtmuc = true
120
121 static const struct v3d_qpu_sig v33_sig_map[] = {
122 /* MISC R3 R4 R5 */
123 [0] = { },
124 [1] = { THRSW, },
125 [2] = { LDUNIF },
126 [3] = { THRSW, LDUNIF },
127 [4] = { LDTMU, },
128 [5] = { THRSW, LDTMU, },
129 [6] = { LDTMU, LDUNIF },
130 [7] = { THRSW, LDTMU, LDUNIF },
131 [8] = { LDVARY, },
132 [9] = { THRSW, LDVARY, },
133 [10] = { LDVARY, LDUNIF },
134 [11] = { THRSW, LDVARY, LDUNIF },
135 [12] = { LDVARY, LDTMU, },
136 [13] = { THRSW, LDVARY, LDTMU, },
137 [14] = { SMIMM, LDVARY, },
138 [15] = { SMIMM, },
139 [16] = { LDTLB, },
140 [17] = { LDTLBU, },
141 /* 18-21 reserved */
142 [22] = { UCB, },
143 [23] = { ROT, },
144 [24] = { LDVPM, },
145 [25] = { THRSW, LDVPM, },
146 [26] = { LDVPM, LDUNIF },
147 [27] = { THRSW, LDVPM, LDUNIF },
148 [28] = { LDVPM, LDTMU, },
149 [29] = { THRSW, LDVPM, LDTMU, },
150 [30] = { SMIMM, LDVPM, },
151 [31] = { SMIMM, },
152 };
153
154 static const struct v3d_qpu_sig v40_sig_map[] = {
155 /* MISC R3 R4 R5 */
156 [0] = { },
157 [1] = { THRSW, },
158 [2] = { LDUNIF },
159 [3] = { THRSW, LDUNIF },
160 [4] = { LDTMU, },
161 [5] = { THRSW, LDTMU, },
162 [6] = { LDTMU, LDUNIF },
163 [7] = { THRSW, LDTMU, LDUNIF },
164 [8] = { LDVARY, },
165 [9] = { THRSW, LDVARY, },
166 [10] = { LDVARY, LDUNIF },
167 [11] = { THRSW, LDVARY, LDUNIF },
168 /* 12-13 reserved */
169 [14] = { SMIMM, LDVARY, },
170 [15] = { SMIMM, },
171 [16] = { LDTLB, },
172 [17] = { LDTLBU, },
173 [18] = { WRTMUC },
174 [19] = { THRSW, WRTMUC },
175 [20] = { LDVARY, WRTMUC },
176 [21] = { THRSW, LDVARY, WRTMUC },
177 [22] = { UCB, },
178 [23] = { ROT, },
179 /* 24-30 reserved */
180 [31] = { SMIMM, LDTMU, },
181 };
182
183 static const struct v3d_qpu_sig v41_sig_map[] = {
184 /* MISC phys R5 */
185 [0] = { },
186 [1] = { THRSW, },
187 [2] = { LDUNIF },
188 [3] = { THRSW, LDUNIF },
189 [4] = { LDTMU, },
190 [5] = { THRSW, LDTMU, },
191 [6] = { LDTMU, LDUNIF },
192 [7] = { THRSW, LDTMU, LDUNIF },
193 [8] = { LDVARY, },
194 [9] = { THRSW, LDVARY, },
195 [10] = { LDVARY, LDUNIF },
196 [11] = { THRSW, LDVARY, LDUNIF },
197 [12] = { LDUNIFRF },
198 [13] = { THRSW, LDUNIFRF },
199 [14] = { SMIMM, LDVARY, },
200 [15] = { SMIMM, },
201 [16] = { LDTLB, },
202 [17] = { LDTLBU, },
203 [18] = { WRTMUC },
204 [19] = { THRSW, WRTMUC },
205 [20] = { LDVARY, WRTMUC },
206 [21] = { THRSW, LDVARY, WRTMUC },
207 [22] = { UCB, },
208 [23] = { ROT, },
209 /* 24-30 reserved */
210 [24] = { LDUNIFA},
211 [25] = { LDUNIFARF },
212 [31] = { SMIMM, LDTMU, },
213 };
214
215 bool
216 v3d_qpu_sig_unpack(const struct v3d_device_info *devinfo,
217 uint32_t packed_sig,
218 struct v3d_qpu_sig *sig)
219 {
220 if (packed_sig >= ARRAY_SIZE(v33_sig_map))
221 return false;
222
223 if (devinfo->ver >= 41)
224 *sig = v41_sig_map[packed_sig];
225 else if (devinfo->ver == 40)
226 *sig = v40_sig_map[packed_sig];
227 else
228 *sig = v33_sig_map[packed_sig];
229
230 /* Signals with zeroed unpacked contents after element 0 are reserved. */
231 return (packed_sig == 0 ||
232 memcmp(sig, &v33_sig_map[0], sizeof(*sig)) != 0);
233 }
234
235 bool
236 v3d_qpu_sig_pack(const struct v3d_device_info *devinfo,
237 const struct v3d_qpu_sig *sig,
238 uint32_t *packed_sig)
239 {
240 static const struct v3d_qpu_sig *map;
241
242 if (devinfo->ver >= 41)
243 map = v41_sig_map;
244 else if (devinfo->ver == 40)
245 map = v40_sig_map;
246 else
247 map = v33_sig_map;
248
249 for (int i = 0; i < ARRAY_SIZE(v33_sig_map); i++) {
250 if (memcmp(&map[i], sig, sizeof(*sig)) == 0) {
251 *packed_sig = i;
252 return true;
253 }
254 }
255
256 return false;
257 }
258 static inline unsigned
259 fui( float f )
260 {
261 union {float f; unsigned ui;} fi;
262 fi.f = f;
263 return fi.ui;
264 }
265
266 static const uint32_t small_immediates[] = {
267 0, 1, 2, 3,
268 4, 5, 6, 7,
269 8, 9, 10, 11,
270 12, 13, 14, 15,
271 -16, -15, -14, -13,
272 -12, -11, -10, -9,
273 -8, -7, -6, -5,
274 -4, -3, -2, -1,
275 0x3b800000, /* 2.0^-8 */
276 0x3c000000, /* 2.0^-7 */
277 0x3c800000, /* 2.0^-6 */
278 0x3d000000, /* 2.0^-5 */
279 0x3d800000, /* 2.0^-4 */
280 0x3e000000, /* 2.0^-3 */
281 0x3e800000, /* 2.0^-2 */
282 0x3f000000, /* 2.0^-1 */
283 0x3f800000, /* 2.0^0 */
284 0x40000000, /* 2.0^1 */
285 0x40800000, /* 2.0^2 */
286 0x41000000, /* 2.0^3 */
287 0x41800000, /* 2.0^4 */
288 0x42000000, /* 2.0^5 */
289 0x42800000, /* 2.0^6 */
290 0x43000000, /* 2.0^7 */
291 };
292
293 bool
294 v3d_qpu_small_imm_unpack(const struct v3d_device_info *devinfo,
295 uint32_t packed_small_immediate,
296 uint32_t *small_immediate)
297 {
298 if (packed_small_immediate >= ARRAY_SIZE(small_immediates))
299 return false;
300
301 *small_immediate = small_immediates[packed_small_immediate];
302 return true;
303 }
304
305 bool
306 v3d_qpu_small_imm_pack(const struct v3d_device_info *devinfo,
307 uint32_t value,
308 uint32_t *packed_small_immediate)
309 {
310 STATIC_ASSERT(ARRAY_SIZE(small_immediates) == 48);
311
312 for (int i = 0; i < ARRAY_SIZE(small_immediates); i++) {
313 if (small_immediates[i] == value) {
314 *packed_small_immediate = i;
315 return true;
316 }
317 }
318
319 return false;
320 }
321
322 bool
323 v3d_qpu_flags_unpack(const struct v3d_device_info *devinfo,
324 uint32_t packed_cond,
325 struct v3d_qpu_flags *cond)
326 {
327 static const enum v3d_qpu_cond cond_map[4] = {
328 [0] = V3D_QPU_COND_IFA,
329 [1] = V3D_QPU_COND_IFB,
330 [2] = V3D_QPU_COND_IFNA,
331 [3] = V3D_QPU_COND_IFNB,
332 };
333
334 cond->ac = V3D_QPU_COND_NONE;
335 cond->mc = V3D_QPU_COND_NONE;
336 cond->apf = V3D_QPU_PF_NONE;
337 cond->mpf = V3D_QPU_PF_NONE;
338 cond->auf = V3D_QPU_UF_NONE;
339 cond->muf = V3D_QPU_UF_NONE;
340
341 if (packed_cond == 0) {
342 return true;
343 } else if (packed_cond >> 2 == 0) {
344 cond->apf = packed_cond & 0x3;
345 } else if (packed_cond >> 4 == 0) {
346 cond->auf = (packed_cond & 0xf) - 4 + V3D_QPU_UF_ANDZ;
347 } else if (packed_cond == 0x10) {
348 return false;
349 } else if (packed_cond >> 2 == 0x4) {
350 cond->mpf = packed_cond & 0x3;
351 } else if (packed_cond >> 4 == 0x1) {
352 cond->muf = (packed_cond & 0xf) - 4 + V3D_QPU_UF_ANDZ;
353 } else if (packed_cond >> 4 == 0x2) {
354 cond->ac = ((packed_cond >> 2) & 0x3) + V3D_QPU_COND_IFA;
355 cond->mpf = packed_cond & 0x3;
356 } else if (packed_cond >> 4 == 0x3) {
357 cond->mc = ((packed_cond >> 2) & 0x3) + V3D_QPU_COND_IFA;
358 cond->apf = packed_cond & 0x3;
359 } else if (packed_cond >> 6) {
360 cond->mc = cond_map[(packed_cond >> 4) & 0x3];
361 if (((packed_cond >> 2) & 0x3) == 0) {
362 cond->ac = cond_map[packed_cond & 0x3];
363 } else {
364 cond->auf = (packed_cond & 0xf) - 4 + V3D_QPU_UF_ANDZ;
365 }
366 }
367
368 return true;
369 }
370
371 bool
372 v3d_qpu_flags_pack(const struct v3d_device_info *devinfo,
373 const struct v3d_qpu_flags *cond,
374 uint32_t *packed_cond)
375 {
376 #define AC (1 << 0)
377 #define MC (1 << 1)
378 #define APF (1 << 2)
379 #define MPF (1 << 3)
380 #define AUF (1 << 4)
381 #define MUF (1 << 5)
382 static const struct {
383 uint8_t flags_present;
384 uint8_t bits;
385 } flags_table[] = {
386 { 0, 0 },
387 { APF, 0 },
388 { AUF, 0 },
389 { MPF, (1 << 4) },
390 { MUF, (1 << 4) },
391 { AC, (1 << 5) },
392 { AC | MPF, (1 << 5) },
393 { MC, (1 << 5) | (1 << 4) },
394 { MC | APF, (1 << 5) | (1 << 4) },
395 { MC | AC, (1 << 6) },
396 { MC | AUF, (1 << 6) },
397 };
398
399 uint8_t flags_present = 0;
400 if (cond->ac != V3D_QPU_COND_NONE)
401 flags_present |= AC;
402 if (cond->mc != V3D_QPU_COND_NONE)
403 flags_present |= MC;
404 if (cond->apf != V3D_QPU_PF_NONE)
405 flags_present |= APF;
406 if (cond->mpf != V3D_QPU_PF_NONE)
407 flags_present |= MPF;
408 if (cond->auf != V3D_QPU_UF_NONE)
409 flags_present |= AUF;
410 if (cond->muf != V3D_QPU_UF_NONE)
411 flags_present |= MUF;
412
413 for (int i = 0; i < ARRAY_SIZE(flags_table); i++) {
414 if (flags_table[i].flags_present != flags_present)
415 continue;
416
417 *packed_cond = flags_table[i].bits;
418
419 *packed_cond |= cond->apf;
420 *packed_cond |= cond->mpf;
421
422 if (flags_present & AUF)
423 *packed_cond |= cond->auf - V3D_QPU_UF_ANDZ + 4;
424 if (flags_present & MUF)
425 *packed_cond |= cond->muf - V3D_QPU_UF_ANDZ + 4;
426
427 if (flags_present & AC)
428 *packed_cond |= (cond->ac - V3D_QPU_COND_IFA) << 2;
429
430 if (flags_present & MC) {
431 if (*packed_cond & (1 << 6))
432 *packed_cond |= (cond->mc -
433 V3D_QPU_COND_IFA) << 4;
434 else
435 *packed_cond |= (cond->mc -
436 V3D_QPU_COND_IFA) << 2;
437 }
438
439 return true;
440 }
441
442 return false;
443 }
444
445 /* Make a mapping of the table of opcodes in the spec. The opcode is
446 * determined by a combination of the opcode field, and in the case of 0 or
447 * 1-arg opcodes, the mux_b field as well.
448 */
449 #define MUX_MASK(bot, top) (((1 << (top + 1)) - 1) - ((1 << (bot)) - 1))
450 #define ANYMUX MUX_MASK(0, 7)
451
452 struct opcode_desc {
453 uint8_t opcode_first;
454 uint8_t opcode_last;
455 uint8_t mux_b_mask;
456 uint8_t mux_a_mask;
457 uint8_t op;
458 /* 0 if it's the same across V3D versions, or a specific V3D version. */
459 uint8_t ver;
460 };
461
462 static const struct opcode_desc add_ops[] = {
463 /* FADD is FADDNF depending on the order of the mux_a/mux_b. */
464 { 0, 47, ANYMUX, ANYMUX, V3D_QPU_A_FADD },
465 { 0, 47, ANYMUX, ANYMUX, V3D_QPU_A_FADDNF },
466 { 53, 55, ANYMUX, ANYMUX, V3D_QPU_A_VFPACK },
467 { 56, 56, ANYMUX, ANYMUX, V3D_QPU_A_ADD },
468 { 57, 59, ANYMUX, ANYMUX, V3D_QPU_A_VFPACK },
469 { 60, 60, ANYMUX, ANYMUX, V3D_QPU_A_SUB },
470 { 61, 63, ANYMUX, ANYMUX, V3D_QPU_A_VFPACK },
471 { 64, 111, ANYMUX, ANYMUX, V3D_QPU_A_FSUB },
472 { 120, 120, ANYMUX, ANYMUX, V3D_QPU_A_MIN },
473 { 121, 121, ANYMUX, ANYMUX, V3D_QPU_A_MAX },
474 { 122, 122, ANYMUX, ANYMUX, V3D_QPU_A_UMIN },
475 { 123, 123, ANYMUX, ANYMUX, V3D_QPU_A_UMAX },
476 { 124, 124, ANYMUX, ANYMUX, V3D_QPU_A_SHL },
477 { 125, 125, ANYMUX, ANYMUX, V3D_QPU_A_SHR },
478 { 126, 126, ANYMUX, ANYMUX, V3D_QPU_A_ASR },
479 { 127, 127, ANYMUX, ANYMUX, V3D_QPU_A_ROR },
480 /* FMIN is instead FMAX depending on the order of the mux_a/mux_b. */
481 { 128, 175, ANYMUX, ANYMUX, V3D_QPU_A_FMIN },
482 { 128, 175, ANYMUX, ANYMUX, V3D_QPU_A_FMAX },
483 { 176, 180, ANYMUX, ANYMUX, V3D_QPU_A_VFMIN },
484
485 { 181, 181, ANYMUX, ANYMUX, V3D_QPU_A_AND },
486 { 182, 182, ANYMUX, ANYMUX, V3D_QPU_A_OR },
487 { 183, 183, ANYMUX, ANYMUX, V3D_QPU_A_XOR },
488
489 { 184, 184, ANYMUX, ANYMUX, V3D_QPU_A_VADD },
490 { 185, 185, ANYMUX, ANYMUX, V3D_QPU_A_VSUB },
491 { 186, 186, 1 << 0, ANYMUX, V3D_QPU_A_NOT },
492 { 186, 186, 1 << 1, ANYMUX, V3D_QPU_A_NEG },
493 { 186, 186, 1 << 2, ANYMUX, V3D_QPU_A_FLAPUSH },
494 { 186, 186, 1 << 3, ANYMUX, V3D_QPU_A_FLBPUSH },
495 { 186, 186, 1 << 4, ANYMUX, V3D_QPU_A_FLBPOP },
496 { 186, 186, 1 << 6, ANYMUX, V3D_QPU_A_SETMSF },
497 { 186, 186, 1 << 7, ANYMUX, V3D_QPU_A_SETREVF },
498 { 187, 187, 1 << 0, 1 << 0, V3D_QPU_A_NOP, 0 },
499 { 187, 187, 1 << 0, 1 << 1, V3D_QPU_A_TIDX },
500 { 187, 187, 1 << 0, 1 << 2, V3D_QPU_A_EIDX },
501 { 187, 187, 1 << 0, 1 << 3, V3D_QPU_A_LR },
502 { 187, 187, 1 << 0, 1 << 4, V3D_QPU_A_VFLA },
503 { 187, 187, 1 << 0, 1 << 5, V3D_QPU_A_VFLNA },
504 { 187, 187, 1 << 0, 1 << 6, V3D_QPU_A_VFLB },
505 { 187, 187, 1 << 0, 1 << 7, V3D_QPU_A_VFLNB },
506
507 { 187, 187, 1 << 1, MUX_MASK(0, 2), V3D_QPU_A_FXCD },
508 { 187, 187, 1 << 1, 1 << 3, V3D_QPU_A_XCD },
509 { 187, 187, 1 << 1, MUX_MASK(4, 6), V3D_QPU_A_FYCD },
510 { 187, 187, 1 << 1, 1 << 7, V3D_QPU_A_YCD },
511
512 { 187, 187, 1 << 2, 1 << 0, V3D_QPU_A_MSF },
513 { 187, 187, 1 << 2, 1 << 1, V3D_QPU_A_REVF },
514 { 187, 187, 1 << 2, 1 << 2, V3D_QPU_A_VDWWT },
515 { 187, 187, 1 << 2, 1 << 5, V3D_QPU_A_TMUWT },
516 { 187, 187, 1 << 2, 1 << 6, V3D_QPU_A_VPMWT },
517
518 { 187, 187, 1 << 3, ANYMUX, V3D_QPU_A_VPMSETUP, 33 },
519 { 188, 188, 1 << 0, ANYMUX, V3D_QPU_A_LDVPMV_IN, 40 },
520 { 188, 188, 1 << 1, ANYMUX, V3D_QPU_A_LDVPMD_IN, 40 },
521 { 188, 188, 1 << 2, ANYMUX, V3D_QPU_A_LDVPMP, 40 },
522 { 189, 189, ANYMUX, ANYMUX, V3D_QPU_A_LDVPMG_IN, 40 },
523
524 /* FIXME: MORE COMPLICATED */
525 /* { 190, 191, ANYMUX, ANYMUX, V3D_QPU_A_VFMOVABSNEGNAB }, */
526
527 { 192, 239, ANYMUX, ANYMUX, V3D_QPU_A_FCMP },
528 { 240, 244, ANYMUX, ANYMUX, V3D_QPU_A_VFMAX },
529
530 { 245, 245, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_FROUND },
531 { 245, 245, 1 << 3, ANYMUX, V3D_QPU_A_FTOIN },
532 { 245, 245, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_FTRUNC },
533 { 245, 245, 1 << 7, ANYMUX, V3D_QPU_A_FTOIZ },
534 { 246, 246, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_FFLOOR },
535 { 246, 246, 1 << 3, ANYMUX, V3D_QPU_A_FTOUZ },
536 { 246, 246, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_FCEIL },
537 { 246, 246, 1 << 7, ANYMUX, V3D_QPU_A_FTOC },
538
539 { 247, 247, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_FDX },
540 { 247, 247, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_FDY },
541
542 /* The stvpms are distinguished by the waddr field. */
543 { 248, 248, ANYMUX, ANYMUX, V3D_QPU_A_STVPMV },
544 { 248, 248, ANYMUX, ANYMUX, V3D_QPU_A_STVPMD },
545 { 248, 248, ANYMUX, ANYMUX, V3D_QPU_A_STVPMP },
546
547 { 252, 252, MUX_MASK(0, 2), ANYMUX, V3D_QPU_A_ITOF },
548 { 252, 252, 1 << 3, ANYMUX, V3D_QPU_A_CLZ },
549 { 252, 252, MUX_MASK(4, 6), ANYMUX, V3D_QPU_A_UTOF },
550 };
551
552 static const struct opcode_desc mul_ops[] = {
553 { 1, 1, ANYMUX, ANYMUX, V3D_QPU_M_ADD },
554 { 2, 2, ANYMUX, ANYMUX, V3D_QPU_M_SUB },
555 { 3, 3, ANYMUX, ANYMUX, V3D_QPU_M_UMUL24 },
556 { 4, 8, ANYMUX, ANYMUX, V3D_QPU_M_VFMUL },
557 { 9, 9, ANYMUX, ANYMUX, V3D_QPU_M_SMUL24 },
558 { 10, 10, ANYMUX, ANYMUX, V3D_QPU_M_MULTOP },
559 { 14, 14, ANYMUX, ANYMUX, V3D_QPU_M_FMOV },
560 { 15, 15, MUX_MASK(0, 3), ANYMUX, V3D_QPU_M_FMOV },
561 { 15, 15, 1 << 4, 1 << 0, V3D_QPU_M_NOP, 0 },
562 { 15, 15, 1 << 7, ANYMUX, V3D_QPU_M_MOV },
563 { 16, 63, ANYMUX, ANYMUX, V3D_QPU_M_FMUL },
564 };
565
566 static const struct opcode_desc *
567 lookup_opcode(const struct opcode_desc *opcodes, size_t num_opcodes,
568 uint32_t opcode, uint32_t mux_a, uint32_t mux_b)
569 {
570 for (int i = 0; i < num_opcodes; i++) {
571 const struct opcode_desc *op_desc = &opcodes[i];
572
573 if (opcode < op_desc->opcode_first ||
574 opcode > op_desc->opcode_last)
575 continue;
576
577 if (!(op_desc->mux_b_mask & (1 << mux_b)))
578 continue;
579
580 if (!(op_desc->mux_a_mask & (1 << mux_a)))
581 continue;
582
583 return op_desc;
584 }
585
586 return NULL;
587 }
588
589 static bool
590 v3d_qpu_float32_unpack_unpack(uint32_t packed,
591 enum v3d_qpu_input_unpack *unpacked)
592 {
593 switch (packed) {
594 case 0:
595 *unpacked = V3D_QPU_UNPACK_ABS;
596 return true;
597 case 1:
598 *unpacked = V3D_QPU_UNPACK_NONE;
599 return true;
600 case 2:
601 *unpacked = V3D_QPU_UNPACK_L;
602 return true;
603 case 3:
604 *unpacked = V3D_QPU_UNPACK_H;
605 return true;
606 default:
607 return false;
608 }
609 }
610
611 static bool
612 v3d_qpu_float32_unpack_pack(enum v3d_qpu_input_unpack unpacked,
613 uint32_t *packed)
614 {
615 switch (unpacked) {
616 case V3D_QPU_UNPACK_ABS:
617 *packed = 0;
618 return true;
619 case V3D_QPU_UNPACK_NONE:
620 *packed = 1;
621 return true;
622 case V3D_QPU_UNPACK_L:
623 *packed = 2;
624 return true;
625 case V3D_QPU_UNPACK_H:
626 *packed = 3;
627 return true;
628 default:
629 return false;
630 }
631 }
632
633 static bool
634 v3d_qpu_float16_unpack_unpack(uint32_t packed,
635 enum v3d_qpu_input_unpack *unpacked)
636 {
637 switch (packed) {
638 case 0:
639 *unpacked = V3D_QPU_UNPACK_NONE;
640 return true;
641 case 1:
642 *unpacked = V3D_QPU_UNPACK_REPLICATE_32F_16;
643 return true;
644 case 2:
645 *unpacked = V3D_QPU_UNPACK_REPLICATE_L_16;
646 return true;
647 case 3:
648 *unpacked = V3D_QPU_UNPACK_REPLICATE_H_16;
649 return true;
650 case 4:
651 *unpacked = V3D_QPU_UNPACK_SWAP_16;
652 return true;
653 default:
654 return false;
655 }
656 }
657
658 static bool
659 v3d_qpu_float16_unpack_pack(enum v3d_qpu_input_unpack unpacked,
660 uint32_t *packed)
661 {
662 switch (unpacked) {
663 case V3D_QPU_UNPACK_NONE:
664 *packed = 0;
665 return true;
666 case V3D_QPU_UNPACK_REPLICATE_32F_16:
667 *packed = 1;
668 return true;
669 case V3D_QPU_UNPACK_REPLICATE_L_16:
670 *packed = 2;
671 return true;
672 case V3D_QPU_UNPACK_REPLICATE_H_16:
673 *packed = 3;
674 return true;
675 case V3D_QPU_UNPACK_SWAP_16:
676 *packed = 4;
677 return true;
678 default:
679 return false;
680 }
681 }
682
683 static bool
684 v3d_qpu_float32_pack_pack(enum v3d_qpu_input_unpack unpacked,
685 uint32_t *packed)
686 {
687 switch (unpacked) {
688 case V3D_QPU_PACK_NONE:
689 *packed = 0;
690 return true;
691 case V3D_QPU_PACK_L:
692 *packed = 1;
693 return true;
694 case V3D_QPU_PACK_H:
695 *packed = 2;
696 return true;
697 default:
698 return false;
699 }
700 }
701
702 static bool
703 v3d_qpu_add_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
704 struct v3d_qpu_instr *instr)
705 {
706 uint32_t op = QPU_GET_FIELD(packed_inst, VC5_QPU_OP_ADD);
707 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_ADD_A);
708 uint32_t mux_b = QPU_GET_FIELD(packed_inst, VC5_QPU_ADD_B);
709 uint32_t waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
710
711 uint32_t map_op = op;
712 /* Some big clusters of opcodes are replicated with unpack
713 * flags
714 */
715 if (map_op >= 249 && map_op <= 251)
716 map_op = (map_op - 249 + 245);
717 if (map_op >= 253 && map_op <= 255)
718 map_op = (map_op - 253 + 245);
719
720 const struct opcode_desc *desc =
721 lookup_opcode(add_ops, ARRAY_SIZE(add_ops),
722 map_op, mux_a, mux_b);
723 if (!desc)
724 return false;
725
726 instr->alu.add.op = desc->op;
727
728 /* FADD/FADDNF and FMIN/FMAX are determined by the orders of the
729 * operands.
730 */
731 if (((op >> 2) & 3) * 8 + mux_a > (op & 3) * 8 + mux_b) {
732 if (instr->alu.add.op == V3D_QPU_A_FMIN)
733 instr->alu.add.op = V3D_QPU_A_FMAX;
734 if (instr->alu.add.op == V3D_QPU_A_FADD)
735 instr->alu.add.op = V3D_QPU_A_FADDNF;
736 }
737
738 /* Some QPU ops require a bit more than just basic opcode and mux a/b
739 * comparisons to distinguish them.
740 */
741 switch (instr->alu.add.op) {
742 case V3D_QPU_A_STVPMV:
743 case V3D_QPU_A_STVPMD:
744 case V3D_QPU_A_STVPMP:
745 switch (waddr) {
746 case 0:
747 instr->alu.add.op = V3D_QPU_A_STVPMV;
748 break;
749 case 1:
750 instr->alu.add.op = V3D_QPU_A_STVPMD;
751 break;
752 case 2:
753 instr->alu.add.op = V3D_QPU_A_STVPMP;
754 break;
755 default:
756 return false;
757 }
758 break;
759 default:
760 break;
761 }
762
763 switch (instr->alu.add.op) {
764 case V3D_QPU_A_FADD:
765 case V3D_QPU_A_FADDNF:
766 case V3D_QPU_A_FSUB:
767 case V3D_QPU_A_FMIN:
768 case V3D_QPU_A_FMAX:
769 case V3D_QPU_A_FCMP:
770 instr->alu.add.output_pack = (op >> 4) & 0x3;
771
772 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
773 &instr->alu.add.a_unpack)) {
774 return false;
775 }
776
777 if (!v3d_qpu_float32_unpack_unpack((op >> 0) & 0x3,
778 &instr->alu.add.b_unpack)) {
779 return false;
780 }
781 break;
782
783 case V3D_QPU_A_FFLOOR:
784 case V3D_QPU_A_FROUND:
785 case V3D_QPU_A_FTRUNC:
786 case V3D_QPU_A_FCEIL:
787 case V3D_QPU_A_FDX:
788 case V3D_QPU_A_FDY:
789 instr->alu.add.output_pack = mux_b & 0x3;
790
791 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
792 &instr->alu.add.a_unpack)) {
793 return false;
794 }
795 break;
796
797 case V3D_QPU_A_FTOIN:
798 case V3D_QPU_A_FTOIZ:
799 case V3D_QPU_A_FTOUZ:
800 case V3D_QPU_A_FTOC:
801 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
802
803 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
804 &instr->alu.add.a_unpack)) {
805 return false;
806 }
807 break;
808
809 case V3D_QPU_A_VFMIN:
810 case V3D_QPU_A_VFMAX:
811 if (!v3d_qpu_float16_unpack_unpack(op & 0x7,
812 &instr->alu.add.a_unpack)) {
813 return false;
814 }
815
816 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
817 instr->alu.add.b_unpack = V3D_QPU_UNPACK_NONE;
818 break;
819
820 default:
821 instr->alu.add.output_pack = V3D_QPU_PACK_NONE;
822 instr->alu.add.a_unpack = V3D_QPU_UNPACK_NONE;
823 instr->alu.add.b_unpack = V3D_QPU_UNPACK_NONE;
824 break;
825 }
826
827 instr->alu.add.a = mux_a;
828 instr->alu.add.b = mux_b;
829 instr->alu.add.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_A);
830
831 instr->alu.add.magic_write = false;
832 if (packed_inst & VC5_QPU_MA) {
833 switch (instr->alu.add.op) {
834 case V3D_QPU_A_LDVPMV_IN:
835 instr->alu.add.op = V3D_QPU_A_LDVPMV_OUT;
836 break;
837 case V3D_QPU_A_LDVPMD_IN:
838 instr->alu.add.op = V3D_QPU_A_LDVPMD_OUT;
839 break;
840 case V3D_QPU_A_LDVPMG_IN:
841 instr->alu.add.op = V3D_QPU_A_LDVPMG_OUT;
842 break;
843 default:
844 instr->alu.add.magic_write = true;
845 break;
846 }
847 }
848
849 return true;
850 }
851
852 static bool
853 v3d_qpu_mul_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst,
854 struct v3d_qpu_instr *instr)
855 {
856 uint32_t op = QPU_GET_FIELD(packed_inst, VC5_QPU_OP_MUL);
857 uint32_t mux_a = QPU_GET_FIELD(packed_inst, VC5_QPU_MUL_A);
858 uint32_t mux_b = QPU_GET_FIELD(packed_inst, VC5_QPU_MUL_B);
859
860 {
861 const struct opcode_desc *desc =
862 lookup_opcode(mul_ops, ARRAY_SIZE(mul_ops),
863 op, mux_a, mux_b);
864 if (!desc)
865 return false;
866
867 instr->alu.mul.op = desc->op;
868 }
869
870 switch (instr->alu.mul.op) {
871 case V3D_QPU_M_FMUL:
872 instr->alu.mul.output_pack = ((op >> 4) & 0x3) - 1;
873
874 if (!v3d_qpu_float32_unpack_unpack((op >> 2) & 0x3,
875 &instr->alu.mul.a_unpack)) {
876 return false;
877 }
878
879 if (!v3d_qpu_float32_unpack_unpack((op >> 0) & 0x3,
880 &instr->alu.mul.b_unpack)) {
881 return false;
882 }
883
884 break;
885
886 case V3D_QPU_M_FMOV:
887 instr->alu.mul.output_pack = (((op & 1) << 1) +
888 ((mux_b >> 2) & 1));
889
890 if (!v3d_qpu_float32_unpack_unpack(mux_b & 0x3,
891 &instr->alu.mul.a_unpack)) {
892 return false;
893 }
894
895 break;
896
897 case V3D_QPU_M_VFMUL:
898 instr->alu.mul.output_pack = V3D_QPU_PACK_NONE;
899
900 if (!v3d_qpu_float16_unpack_unpack(((op & 0x7) - 4) & 7,
901 &instr->alu.mul.a_unpack)) {
902 return false;
903 }
904
905 instr->alu.mul.b_unpack = V3D_QPU_UNPACK_NONE;
906
907 break;
908
909 default:
910 instr->alu.mul.output_pack = V3D_QPU_PACK_NONE;
911 instr->alu.mul.a_unpack = V3D_QPU_UNPACK_NONE;
912 instr->alu.mul.b_unpack = V3D_QPU_UNPACK_NONE;
913 break;
914 }
915
916 instr->alu.mul.a = mux_a;
917 instr->alu.mul.b = mux_b;
918 instr->alu.mul.waddr = QPU_GET_FIELD(packed_inst, V3D_QPU_WADDR_M);
919 instr->alu.mul.magic_write = packed_inst & VC5_QPU_MM;
920
921 return true;
922 }
923
924 static bool
925 v3d_qpu_add_pack(const struct v3d_device_info *devinfo,
926 const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
927 {
928 uint32_t waddr = instr->alu.add.waddr;
929 uint32_t mux_a = instr->alu.add.a;
930 uint32_t mux_b = instr->alu.add.b;
931 int nsrc = v3d_qpu_add_op_num_src(instr->alu.add.op);
932 const struct opcode_desc *desc;
933
934 int opcode;
935 for (desc = add_ops; desc != &add_ops[ARRAY_SIZE(add_ops)];
936 desc++) {
937 if (desc->op == instr->alu.add.op)
938 break;
939 }
940 if (desc == &add_ops[ARRAY_SIZE(add_ops)])
941 return false;
942
943 opcode = desc->opcode_first;
944
945 /* If an operation doesn't use an arg, its mux values may be used to
946 * identify the operation type.
947 */
948 if (nsrc < 2)
949 mux_b = ffs(desc->mux_b_mask) - 1;
950
951 if (nsrc < 1)
952 mux_a = ffs(desc->mux_a_mask) - 1;
953
954 bool no_magic_write = false;
955
956 switch (instr->alu.add.op) {
957 case V3D_QPU_A_STVPMV:
958 waddr = 0;
959 no_magic_write = true;
960 break;
961 case V3D_QPU_A_STVPMD:
962 waddr = 1;
963 no_magic_write = true;
964 break;
965 case V3D_QPU_A_STVPMP:
966 waddr = 2;
967 no_magic_write = true;
968 break;
969
970 case V3D_QPU_A_LDVPMV_IN:
971 case V3D_QPU_A_LDVPMD_IN:
972 case V3D_QPU_A_LDVPMP:
973 case V3D_QPU_A_LDVPMG_IN:
974 assert(!instr->alu.add.magic_write);
975 break;
976
977 case V3D_QPU_A_LDVPMV_OUT:
978 case V3D_QPU_A_LDVPMD_OUT:
979 case V3D_QPU_A_LDVPMG_OUT:
980 assert(!instr->alu.add.magic_write);
981 *packed_instr |= VC5_QPU_MA;
982 break;
983
984 default:
985 break;
986 }
987
988 switch (instr->alu.add.op) {
989 case V3D_QPU_A_FADD:
990 case V3D_QPU_A_FADDNF:
991 case V3D_QPU_A_FSUB:
992 case V3D_QPU_A_FMIN:
993 case V3D_QPU_A_FMAX:
994 case V3D_QPU_A_FCMP: {
995 uint32_t output_pack;
996 uint32_t a_unpack;
997 uint32_t b_unpack;
998
999 if (!v3d_qpu_float32_pack_pack(instr->alu.add.output_pack,
1000 &output_pack)) {
1001 return false;
1002 }
1003 opcode |= output_pack << 4;
1004
1005 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1006 &a_unpack)) {
1007 return false;
1008 }
1009
1010 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.b_unpack,
1011 &b_unpack)) {
1012 return false;
1013 }
1014
1015 /* These operations with commutative operands are
1016 * distinguished by which order their operands come in.
1017 */
1018 bool ordering = a_unpack * 8 + mux_a > b_unpack * 8 + mux_b;
1019 if (((instr->alu.add.op == V3D_QPU_A_FMIN ||
1020 instr->alu.add.op == V3D_QPU_A_FADD) && ordering) ||
1021 ((instr->alu.add.op == V3D_QPU_A_FMAX ||
1022 instr->alu.add.op == V3D_QPU_A_FADDNF) && !ordering)) {
1023 uint32_t temp;
1024
1025 temp = a_unpack;
1026 a_unpack = b_unpack;
1027 b_unpack = temp;
1028
1029 temp = mux_a;
1030 mux_a = mux_b;
1031 mux_b = temp;
1032 }
1033
1034 opcode |= a_unpack << 2;
1035 opcode |= b_unpack << 0;
1036 break;
1037 }
1038
1039 case V3D_QPU_A_FFLOOR:
1040 case V3D_QPU_A_FROUND:
1041 case V3D_QPU_A_FTRUNC:
1042 case V3D_QPU_A_FCEIL:
1043 case V3D_QPU_A_FDX:
1044 case V3D_QPU_A_FDY: {
1045 uint32_t packed;
1046
1047 if (!v3d_qpu_float32_pack_pack(instr->alu.add.output_pack,
1048 &packed)) {
1049 return false;
1050 }
1051 mux_b |= packed;
1052
1053 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1054 &packed)) {
1055 return false;
1056 }
1057 if (packed == 0)
1058 return false;
1059 opcode |= packed << 2;
1060 break;
1061 }
1062
1063 case V3D_QPU_A_FTOIN:
1064 case V3D_QPU_A_FTOIZ:
1065 case V3D_QPU_A_FTOUZ:
1066 case V3D_QPU_A_FTOC:
1067 if (instr->alu.add.output_pack != V3D_QPU_PACK_NONE)
1068 return false;
1069
1070 uint32_t packed;
1071 if (!v3d_qpu_float32_unpack_pack(instr->alu.add.a_unpack,
1072 &packed)) {
1073 return false;
1074 }
1075 if (packed == 0)
1076 return false;
1077 opcode |= packed << 2;
1078
1079 break;
1080
1081 case V3D_QPU_A_VFMIN:
1082 case V3D_QPU_A_VFMAX:
1083 if (instr->alu.add.output_pack != V3D_QPU_PACK_NONE ||
1084 instr->alu.add.b_unpack != V3D_QPU_UNPACK_NONE) {
1085 return false;
1086 }
1087
1088 if (!v3d_qpu_float16_unpack_pack(instr->alu.add.a_unpack,
1089 &packed)) {
1090 return false;
1091 }
1092 opcode |= packed;
1093 break;
1094
1095 default:
1096 if (instr->alu.add.op != V3D_QPU_A_NOP &&
1097 (instr->alu.add.output_pack != V3D_QPU_PACK_NONE ||
1098 instr->alu.add.a_unpack != V3D_QPU_UNPACK_NONE ||
1099 instr->alu.add.b_unpack != V3D_QPU_UNPACK_NONE)) {
1100 return false;
1101 }
1102 break;
1103 }
1104
1105 *packed_instr |= QPU_SET_FIELD(mux_a, VC5_QPU_ADD_A);
1106 *packed_instr |= QPU_SET_FIELD(mux_b, VC5_QPU_ADD_B);
1107 *packed_instr |= QPU_SET_FIELD(opcode, VC5_QPU_OP_ADD);
1108 *packed_instr |= QPU_SET_FIELD(waddr, V3D_QPU_WADDR_A);
1109 if (instr->alu.add.magic_write && !no_magic_write)
1110 *packed_instr |= VC5_QPU_MA;
1111
1112 return true;
1113 }
1114
1115 static bool
1116 v3d_qpu_mul_pack(const struct v3d_device_info *devinfo,
1117 const struct v3d_qpu_instr *instr, uint64_t *packed_instr)
1118 {
1119 uint32_t mux_a = instr->alu.mul.a;
1120 uint32_t mux_b = instr->alu.mul.b;
1121 int nsrc = v3d_qpu_mul_op_num_src(instr->alu.mul.op);
1122 const struct opcode_desc *desc;
1123
1124 for (desc = mul_ops; desc != &mul_ops[ARRAY_SIZE(mul_ops)];
1125 desc++) {
1126 if (desc->op == instr->alu.mul.op)
1127 break;
1128 }
1129 if (desc == &mul_ops[ARRAY_SIZE(mul_ops)])
1130 return false;
1131
1132 uint32_t opcode = desc->opcode_first;
1133
1134 /* Some opcodes have a single valid value for their mux a/b, so set
1135 * that here. If mux a/b determine packing, it will be set below.
1136 */
1137 if (nsrc < 2)
1138 mux_b = ffs(desc->mux_b_mask) - 1;
1139
1140 if (nsrc < 1)
1141 mux_a = ffs(desc->mux_a_mask) - 1;
1142
1143 switch (instr->alu.mul.op) {
1144 case V3D_QPU_M_FMUL: {
1145 uint32_t packed;
1146
1147 if (!v3d_qpu_float32_pack_pack(instr->alu.mul.output_pack,
1148 &packed)) {
1149 return false;
1150 }
1151 /* No need for a +1 because desc->opcode_first has a 1 in this
1152 * field.
1153 */
1154 opcode += packed << 4;
1155
1156 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.a_unpack,
1157 &packed)) {
1158 return false;
1159 }
1160 opcode |= packed << 2;
1161
1162 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.b_unpack,
1163 &packed)) {
1164 return false;
1165 }
1166 opcode |= packed << 0;
1167 break;
1168 }
1169
1170 case V3D_QPU_M_FMOV: {
1171 uint32_t packed;
1172
1173 if (!v3d_qpu_float32_pack_pack(instr->alu.mul.output_pack,
1174 &packed)) {
1175 return false;
1176 }
1177 opcode |= (packed >> 1) & 1;
1178 mux_b = (packed & 1) << 2;
1179
1180 if (!v3d_qpu_float32_unpack_pack(instr->alu.mul.a_unpack,
1181 &packed)) {
1182 return false;
1183 }
1184 mux_b |= packed;
1185 break;
1186 }
1187
1188 case V3D_QPU_M_VFMUL: {
1189 uint32_t packed;
1190
1191 if (instr->alu.mul.output_pack != V3D_QPU_PACK_NONE)
1192 return false;
1193
1194 if (!v3d_qpu_float16_unpack_pack(instr->alu.mul.a_unpack,
1195 &packed)) {
1196 return false;
1197 }
1198 if (instr->alu.mul.a_unpack == V3D_QPU_UNPACK_SWAP_16)
1199 opcode = 8;
1200 else
1201 opcode |= (packed + 4) & 7;
1202
1203 if (instr->alu.mul.b_unpack != V3D_QPU_UNPACK_NONE)
1204 return false;
1205
1206 break;
1207 }
1208
1209 default:
1210 break;
1211 }
1212
1213 *packed_instr |= QPU_SET_FIELD(mux_a, VC5_QPU_MUL_A);
1214 *packed_instr |= QPU_SET_FIELD(mux_b, VC5_QPU_MUL_B);
1215
1216 *packed_instr |= QPU_SET_FIELD(opcode, VC5_QPU_OP_MUL);
1217 *packed_instr |= QPU_SET_FIELD(instr->alu.mul.waddr, V3D_QPU_WADDR_M);
1218 if (instr->alu.mul.magic_write)
1219 *packed_instr |= VC5_QPU_MM;
1220
1221 return true;
1222 }
1223
1224 static bool
1225 v3d_qpu_instr_unpack_alu(const struct v3d_device_info *devinfo,
1226 uint64_t packed_instr,
1227 struct v3d_qpu_instr *instr)
1228 {
1229 instr->type = V3D_QPU_INSTR_TYPE_ALU;
1230
1231 if (!v3d_qpu_sig_unpack(devinfo,
1232 QPU_GET_FIELD(packed_instr, VC5_QPU_SIG),
1233 &instr->sig))
1234 return false;
1235
1236 uint32_t packed_cond = QPU_GET_FIELD(packed_instr, VC5_QPU_COND);
1237 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig)) {
1238 instr->sig_addr = packed_cond & ~VC5_QPU_COND_SIG_MAGIC_ADDR;
1239 instr->sig_magic = packed_cond & VC5_QPU_COND_SIG_MAGIC_ADDR;
1240
1241 instr->flags.ac = V3D_QPU_COND_NONE;
1242 instr->flags.mc = V3D_QPU_COND_NONE;
1243 instr->flags.apf = V3D_QPU_PF_NONE;
1244 instr->flags.mpf = V3D_QPU_PF_NONE;
1245 instr->flags.auf = V3D_QPU_UF_NONE;
1246 instr->flags.muf = V3D_QPU_UF_NONE;
1247 } else {
1248 if (!v3d_qpu_flags_unpack(devinfo, packed_cond, &instr->flags))
1249 return false;
1250 }
1251
1252 instr->raddr_a = QPU_GET_FIELD(packed_instr, VC5_QPU_RADDR_A);
1253 instr->raddr_b = QPU_GET_FIELD(packed_instr, VC5_QPU_RADDR_B);
1254
1255 if (!v3d_qpu_add_unpack(devinfo, packed_instr, instr))
1256 return false;
1257
1258 if (!v3d_qpu_mul_unpack(devinfo, packed_instr, instr))
1259 return false;
1260
1261 return true;
1262 }
1263
1264 static bool
1265 v3d_qpu_instr_unpack_branch(const struct v3d_device_info *devinfo,
1266 uint64_t packed_instr,
1267 struct v3d_qpu_instr *instr)
1268 {
1269 instr->type = V3D_QPU_INSTR_TYPE_BRANCH;
1270
1271 uint32_t cond = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_COND);
1272 if (cond == 0)
1273 instr->branch.cond = V3D_QPU_BRANCH_COND_ALWAYS;
1274 else if (V3D_QPU_BRANCH_COND_A0 + (cond - 2) <=
1275 V3D_QPU_BRANCH_COND_ALLNA)
1276 instr->branch.cond = V3D_QPU_BRANCH_COND_A0 + (cond - 2);
1277 else
1278 return false;
1279
1280 uint32_t msfign = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_MSFIGN);
1281 if (msfign == 3)
1282 return false;
1283 instr->branch.msfign = msfign;
1284
1285 instr->branch.bdi = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_BDI);
1286
1287 instr->branch.ub = packed_instr & VC5_QPU_BRANCH_UB;
1288 if (instr->branch.ub) {
1289 instr->branch.bdu = QPU_GET_FIELD(packed_instr,
1290 VC5_QPU_BRANCH_BDU);
1291 }
1292
1293 instr->branch.raddr_a = QPU_GET_FIELD(packed_instr,
1294 VC5_QPU_RADDR_A);
1295
1296 instr->branch.offset = 0;
1297
1298 instr->branch.offset +=
1299 QPU_GET_FIELD(packed_instr,
1300 VC5_QPU_BRANCH_ADDR_LOW) << 3;
1301
1302 instr->branch.offset +=
1303 QPU_GET_FIELD(packed_instr,
1304 VC5_QPU_BRANCH_ADDR_HIGH) << 24;
1305
1306 return true;
1307 }
1308
1309 bool
1310 v3d_qpu_instr_unpack(const struct v3d_device_info *devinfo,
1311 uint64_t packed_instr,
1312 struct v3d_qpu_instr *instr)
1313 {
1314 if (QPU_GET_FIELD(packed_instr, VC5_QPU_OP_MUL) != 0) {
1315 return v3d_qpu_instr_unpack_alu(devinfo, packed_instr, instr);
1316 } else {
1317 uint32_t sig = QPU_GET_FIELD(packed_instr, VC5_QPU_SIG);
1318
1319 if ((sig & 24) == 16) {
1320 return v3d_qpu_instr_unpack_branch(devinfo, packed_instr,
1321 instr);
1322 } else {
1323 return false;
1324 }
1325 }
1326 }
1327
1328 static bool
1329 v3d_qpu_instr_pack_alu(const struct v3d_device_info *devinfo,
1330 const struct v3d_qpu_instr *instr,
1331 uint64_t *packed_instr)
1332 {
1333 uint32_t sig;
1334 if (!v3d_qpu_sig_pack(devinfo, &instr->sig, &sig))
1335 return false;
1336 *packed_instr |= QPU_SET_FIELD(sig, VC5_QPU_SIG);
1337
1338 if (instr->type == V3D_QPU_INSTR_TYPE_ALU) {
1339 *packed_instr |= QPU_SET_FIELD(instr->raddr_a, VC5_QPU_RADDR_A);
1340 *packed_instr |= QPU_SET_FIELD(instr->raddr_b, VC5_QPU_RADDR_B);
1341
1342 if (!v3d_qpu_add_pack(devinfo, instr, packed_instr))
1343 return false;
1344 if (!v3d_qpu_mul_pack(devinfo, instr, packed_instr))
1345 return false;
1346
1347 uint32_t flags;
1348 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig)) {
1349 if (instr->flags.ac != V3D_QPU_COND_NONE ||
1350 instr->flags.mc != V3D_QPU_COND_NONE ||
1351 instr->flags.apf != V3D_QPU_PF_NONE ||
1352 instr->flags.mpf != V3D_QPU_PF_NONE ||
1353 instr->flags.auf != V3D_QPU_UF_NONE ||
1354 instr->flags.muf != V3D_QPU_UF_NONE) {
1355 return false;
1356 }
1357
1358 flags = instr->sig_addr;
1359 if (instr->sig_magic)
1360 flags |= VC5_QPU_COND_SIG_MAGIC_ADDR;
1361 } else {
1362 if (!v3d_qpu_flags_pack(devinfo, &instr->flags, &flags))
1363 return false;
1364 }
1365
1366 *packed_instr |= QPU_SET_FIELD(flags, VC5_QPU_COND);
1367 } else {
1368 if (v3d_qpu_sig_writes_address(devinfo, &instr->sig))
1369 return false;
1370 }
1371
1372 return true;
1373 }
1374
1375 static bool
1376 v3d_qpu_instr_pack_branch(const struct v3d_device_info *devinfo,
1377 const struct v3d_qpu_instr *instr,
1378 uint64_t *packed_instr)
1379 {
1380 *packed_instr |= QPU_SET_FIELD(16, VC5_QPU_SIG);
1381
1382 if (instr->branch.cond != V3D_QPU_BRANCH_COND_ALWAYS) {
1383 *packed_instr |= QPU_SET_FIELD(2 + (instr->branch.cond -
1384 V3D_QPU_BRANCH_COND_A0),
1385 VC5_QPU_BRANCH_COND);
1386 }
1387
1388 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,
1389 VC5_QPU_BRANCH_MSFIGN);
1390
1391 *packed_instr |= QPU_SET_FIELD(instr->branch.bdi,
1392 VC5_QPU_BRANCH_BDI);
1393
1394 if (instr->branch.ub) {
1395 *packed_instr |= VC5_QPU_BRANCH_UB;
1396 *packed_instr |= QPU_SET_FIELD(instr->branch.bdu,
1397 VC5_QPU_BRANCH_BDU);
1398 }
1399
1400 switch (instr->branch.bdi) {
1401 case V3D_QPU_BRANCH_DEST_ABS:
1402 case V3D_QPU_BRANCH_DEST_REL:
1403 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,
1404 VC5_QPU_BRANCH_MSFIGN);
1405
1406 *packed_instr |= QPU_SET_FIELD((instr->branch.offset &
1407 ~0xff000000) >> 3,
1408 VC5_QPU_BRANCH_ADDR_LOW);
1409
1410 *packed_instr |= QPU_SET_FIELD(instr->branch.offset >> 24,
1411 VC5_QPU_BRANCH_ADDR_HIGH);
1412
1413 case V3D_QPU_BRANCH_DEST_REGFILE:
1414 *packed_instr |= QPU_SET_FIELD(instr->branch.raddr_a,
1415 VC5_QPU_RADDR_A);
1416 break;
1417
1418 default:
1419 break;
1420 }
1421
1422 return true;
1423 }
1424
1425 bool
1426 v3d_qpu_instr_pack(const struct v3d_device_info *devinfo,
1427 const struct v3d_qpu_instr *instr,
1428 uint64_t *packed_instr)
1429 {
1430 *packed_instr = 0;
1431
1432 switch (instr->type) {
1433 case V3D_QPU_INSTR_TYPE_ALU:
1434 return v3d_qpu_instr_pack_alu(devinfo, instr, packed_instr);
1435 case V3D_QPU_INSTR_TYPE_BRANCH:
1436 return v3d_qpu_instr_pack_branch(devinfo, instr, packed_instr);
1437 default:
1438 return false;
1439 }
1440 }