src/bsv/bsv_lib/mux.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package mux;
  15         /*==== Package imports ==== */
  16         import TriState          ::*;
  17         import Vector                            ::*;
  18         import BUtils::*;
  19         import ConfigReg                        ::*;
  20         /*============================ */
  21         /*===== Project Imports ===== */
  22         import Semi_FIFOF        :: *;
  23         import AXI4_Lite_Types   :: *;
  24         /*============================ */
  25   `define ADDR 32
  26   `define DATA 64
  27   `define USER 0
  28   `define IONum 32
  29   `define GPIO_MUX
  30
  31         interface MUX#(numeric type ionum);
  32                 (*always_ready,always_enabled*)
  33                 method Vector#(ionum,Bit#(2))   mux;
  34                 interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USER) axi_slave;
  35         endinterface
  36
  37 //      (*synthesize*)
  38         module mkmux(MUX#(ionum_));
  39           Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg                                 <-replicateM(mkConfigReg(0));
  40
  41                 AXI4_Lite_Slave_Xactor_IFC #(`ADDR, `DATA, `USER)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
  42     let ionum=valueOf(ionum_);
  43                 rule rl_wr_respond;
  44                         // Get the wr request
  45       let aw <- pop_o (s_xactor.o_wr_addr);
  46       let w  <- pop_o (s_xactor.o_wr_data);
  47                 let b = AXI4_Lite_Wr_Resp {bresp: AXI4_LITE_OKAY, buser: aw.awuser};
  48                   if(aw.awaddr[5:0]=='h2c)
  49                     for(Integer i=0;i<min(ionum, 16);i=i+1) begin
  50           muxer_reg[i]<= w.wdata[i*2+1:i*2];
  51                         end
  52                   else if(aw.awaddr[5:0]=='h30 && ionum>=16)
  53                         for(Integer i=0;i<ionum-16;i=i+1) begin
  54           muxer_reg[i+16]<= w.wdata[i*2+1:i*2];
  55                         end
  56                         else
  57                                 b.bresp=AXI4_LITE_SLVERR;
  58         s_xactor.i_wr_resp.enq (b);
  59                 endrule
  60
  61                 rule rl_rd_respond;
  62                         let ar<- pop_o(s_xactor.o_rd_addr);
  63                         Bit#(32) temp=0;
  64                         AXI4_Lite_Rd_Data#(`DATA,`USER) r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: ?, ruser: 0};
  65                   if(ar.araddr[5:0]=='h2c)begin
  66                         for(Integer i=0;i<min(ionum, 16);i=i+1) begin
  67           temp[i*2+ 1:i*2]=muxer_reg[i];
  68                         end
  69         r.rdata=duplicate(temp);
  70       end
  71                   else if(ar.araddr[5:0]=='h30 && ionum>=16)begin
  72                         for(Integer i=0;i<ionum-16;i=i+1) begin
  73           temp[i*2+ 1:i*2]=muxer_reg[i+ 16];
  74                         end
  75         r.rdata=duplicate(temp);
  76       end
  77                         else
  78                                 r.rresp=AXI4_LITE_SLVERR;
  79                         s_xactor.i_rd_data.enq(r);
  80                 endrule
  81
  82                 interface axi_slave= s_xactor.axi_side;
  83                 method Vector#(ionum,Bit#(2))   mux;
  84                         Vector#(ionum,Bit#(2)) temp;
  85                         for(Integer i=0;i<ionum;i=i+1)
  86                                 temp[i]=pack(muxer_reg[i]);
  87                         return temp;
  88                 endmethod
  89         endmodule
  90
  91
  92   // instantiation template
  93         interface MUX_real;
  94                 (*always_ready,always_enabled*)
  95                 method Vector#(32,Bit#(2))   mux;
  96                 interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USER) axi_slave;
  97         endinterface
  98   (*synthesize*)
  99   module mkmux_real(MUX_real);
 100     MUX#(32) mymux <-mkmux();
 101     method mux=mymux.mux;
 102     interface axi_slave=mymux.axi_slave;
 103   endmodule
 104 endpackage
 105