1 package slow_peripherals;
2 /*===== Project imports =====*/
3 import defined_types::*;
4 import AXI4_Lite_Fabric::*;
5 import AXI4_Lite_Types::*;
9 import AXI4Lite_AXI4_Bridge::*;
10 `include "instance_defines.bsv"
11 /* ==== define the AXI Addresses ==== */
13 /*====== AXI4 Lite slave declarations =======*/
16 /*===========================*/
17 /*=== package imports ===*/
20 import ClientServer::*;
21 import Connectable::*;
24 /*=======================*/
25 /*===== Import the slow peripherals ====*/
34 import axiexpansion ::*;
36 /*=====================================*/
38 /*===== interface declaration =====*/
42 interface Get#(Bit#(67)) axiexp1_out;
43 interface Put#(Bit#(67)) axiexp1_in;
46 interface Ifc_slow_peripherals;
47 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
48 interface SP_ios slow_ios;
49 method Action external_int(Bit#(32) in);
51 method Bit#(1) msip_int;
52 method Bit#(1) mtip_int;
53 method Bit#(`Reg_width) mtime;
55 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
56 interface IOCellSide iocell_side; // mandatory interface
58 /*================================*/
60 function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
61 fn_address_mapping (Bit#(`PADDR) addr);
63 if(addr>=`ClintBase && addr<=`ClintEnd)
64 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
68 if(addr>=`PLICBase && addr<=`PLICEnd)
69 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
73 if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
74 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
78 return tuple2(False,?);
82 module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
83 Clock uart_clock, Reset uart_reset
84 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
85 )(Ifc_slow_peripherals);
86 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
87 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
89 /*======= Module declarations for each peripheral =======*/
92 Ifc_clint clint <- mkclint();
95 Ifc_PLIC_AXI plic <- mkplicperipheral();
96 Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
97 Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
100 Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
102 Ifc_pinmux pinmux <- mkpinmux; // mandatory
103 Wire#(Bit#(32)) wr_interrupt <- mkWire();
104 /*=======================================================*/
106 AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)
107 slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
108 Ifc_AXI4Lite_AXI4_Bridge
109 bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
111 mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
112 /*======= Slave connections to AXI4Lite fabric =========*/
115 mkConnection (slow_fabric.v_to_slaves
116 [fromInteger(valueOf(CLINT_slave_num))],
120 mkConnection (slow_fabric.v_to_slaves
121 [fromInteger(valueOf(Plic_slave_num))],
122 plic.axi4_slave_plic); //
125 mkConnection (slow_fabric.v_to_slaves
126 [fromInteger(valueOf(AxiExp1_slave_num))],
127 axiexp1.axi_slave); //
130 /*========== pinmux connections ============*/
133 rule connect_i2c0_scl;
134 pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
135 pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
137 rule connect_i2c0_scl_in;
138 i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
140 rule connect_i2c0_sda;
141 pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
142 pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
144 rule connect_i2c0_sda_in;
145 i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
147 rule connect_uart1tx;
148 pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
150 rule connect_uart1rx;
151 uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
153 for(Integer i=0;i<32;i=i+ 1)begin
154 rule connect_int_to_plic(wr_interrupt[i]==1);
155 ff_gateway_queue[i].enq(1);
156 plic.ifc_external_irq[i].irq_frm_gateway(True);
159 rule rl_completion_msg_from_plic;
160 let id <- plic.intrpt_completion;
162 `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
165 for(Integer i=0; i <32; i=i+1) begin
166 rule deq_gateway_queue;
167 if(interrupt_id==fromInteger(i)) begin
168 ff_gateway_queue[i].deq;
169 `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
173 /* for connectin inputs from pinmux as itnerrupts
174 rule connect_pinmux_eint;
175 wr_interrupt<= pinmux.peripheral_side.eint_input;
179 /*=======================================================*/
180 /*=================== PLIC Connections ==================== */
182 /*TODO DMA interrupt need to be connected to the plic
183 for(Integer i=1; i<8; i=i+1) begin
185 rule rl_connect_dma_interrupts_to_plic;
186 if(dma.interrupt_to_processor[i-1]==1'b1) begin
187 ff_gateway_queue[i].enq(1);
188 plic.ifc_external_irq[i].irq_frm_gateway(True);
192 rule rl_connect_dma_interrupts_to_plic;
193 ff_gateway_queue[i].enq(0);
198 rule rl_connect_i2c0_to_plic;
200 if(i2c0.isint()==1'b1) begin
201 ff_gateway_queue[8].enq(1);
202 plic.ifc_external_irq[8].irq_frm_gateway(True);
205 ff_gateway_queue[8].enq(0);
209 rule rl_connect_i2c1_to_plic;
211 if(i2c1.isint()==1'b1) begin
212 ff_gateway_queue[9].enq(1);
213 plic.ifc_external_irq[9].irq_frm_gateway(True);
216 ff_gateway_queue[9].enq(0);
220 rule rl_connect_i2c0_timerint_to_plic;
222 if(i2c0.timerint()==1'b1) begin
223 ff_gateway_queue[10].enq(1);
224 plic.ifc_external_irq[10].irq_frm_gateway(True);
227 ff_gateway_queue[10].enq(0);
231 rule rl_connect_i2c1_timerint_to_plic;
233 if(i2c1.timerint()==1'b1) begin
234 ff_gateway_queue[11].enq(1);
235 plic.ifc_external_irq[11].irq_frm_gateway(True);
238 ff_gateway_queue[11].enq(0);
242 rule rl_connect_i2c0_isber_to_plic;
244 if(i2c0.isber()==1'b1) begin
245 ff_gateway_queue[12].enq(1);
246 plic.ifc_external_irq[12].irq_frm_gateway(True);
249 ff_gateway_queue[12].enq(0);
253 rule rl_connect_i2c1_isber_to_plic;
255 if(i2c1.isber()==1'b1) begin
256 ff_gateway_queue[13].enq(1);
257 plic.ifc_external_irq[13].irq_frm_gateway(True);
260 ff_gateway_queue[13].enq(0);
264 for(Integer i = 14; i < 20; i=i+1) begin
265 rule rl_connect_qspi0_to_plic;
267 if(qspi0.interrupts()[i-14]==1'b1) begin
268 ff_gateway_queue[i].enq(1);
269 plic.ifc_external_irq[i].irq_frm_gateway(True);
272 ff_gateway_queue[i].enq(0);
277 for(Integer i = 20; i<26; i=i+1) begin
278 rule rl_connect_qspi1_to_plic;
280 if(qspi1.interrupts()[i-20]==1'b1) begin
281 ff_gateway_queue[i].enq(1);
282 plic.ifc_external_irq[i].irq_frm_gateway(True);
285 ff_gateway_queue[i].enq(0);
291 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
292 rule synchronize_the_uart0_interrupt;
293 uart0_interrupt.send(uart0.irq);
296 rule rl_connect_uart_to_plic;
298 if(uart0_interrupt.read==1'b1) begin
299 ff_gateway_queue[27].enq(1);
300 plic.ifc_external_irq[27].irq_frm_gateway(True);
304 ff_gateway_queue[27].enq(0);
308 for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
309 rule rl_raise_interrupts;
310 if((i-28)<`IONum) begin //Peripheral interrupts
311 if(gpio.to_plic[i-28]==1'b1) begin
312 plic.ifc_external_irq[i].irq_frm_gateway(True);
313 ff_gateway_queue[i].enq(1);
319 rule rl_completion_msg_from_plic;
320 let id <- plic.intrpt_completion;
322 `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
325 for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
326 rule deq_gateway_queue;
327 if(interrupt_id==fromInteger(i)) begin
328 ff_gateway_queue[i].deq;
329 `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
336 /*======================================================= */
338 /* ===== interface definition =======*/
339 interface axi_slave=bridge.axi_slave;
340 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
342 method msip_int=clint.msip_int;
343 method mtip_int=clint.mtip_int;
344 method mtime=clint.mtime;
347 method i2c0_isint=i2c0.isint;
350 method i2c1_isint=i2c1.isint;
352 `ifdef QSPI0 method qspi0_isint=qspi0.interrupts[5]; `endif
353 `ifdef QSPI1 method qspi1_isint=qspi1.interrupts[5]; `endif
354 `ifdef UART0 method uart0_intr=uart0.irq; `endif
355 interface SP_ios slow_ios;
357 interface uart0_coe=uart0.coe_rs232;
360 interface uart1_coe=uart1.coe_rs232;
363 interface i2c0_out=i2c0.out;
366 interface i2c1_out=i2c1.out;
369 interface qspi0_out = qspi0.out;
372 interface qspi1_out = qspi1.out;
375 interface axiexp1_out=axiexp1.slave_out;
376 interface axiexp1_in=axiexp1.slave_in;
379 interface pwm_o = pwm_bus.pwm_io;
383 interface iocell_side=pinmux.iocell_side;
384 interface pad_configa= gpioa.pad_config;
385 method Action external_int(Bit#(32) in);
389 /*===================================*/