1 package slow_peripherals;
2 /*===== Project imports =====*/
3 import defined_types::*;
4 import AXI4_Lite_Fabric::*;
5 import AXI4_Lite_Types::*;
9 import AXI4Lite_AXI4_Bridge::*;
10 import slow_memory_map::*;
11 `include "instance_defines.bsv"
12 /* ==== define the number of slow peripheral irqs ==== */
14 /*===========================*/
15 /*=== package imports ===*/
19 import ClientServer::*;
20 import Connectable::*;
23 /*=======================*/
24 /*===== Import the slow peripherals ====*/
33 import axiexpansion ::*;
35 /*=====================================*/
37 /*===== interface declaration =====*/
38 interface SP_dedicated_ios;
40 interface Get#(Bit#(67)) axiexp1_out;
41 interface Put#(Bit#(67)) axiexp1_in;
44 interface Ifc_slow_peripherals;
45 interface AXI4_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
46 interface SP_dedicated_ios slow_ios;
48 method Bit#(1) msip_int;
49 method Bit#(1) mtip_int;
50 method Bit#(`DATA) mtime;
52 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note;
54 interface IOCellSide iocell_side; // mandatory interface
59 /*================================*/
62 module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
63 Clock uart_clock, Reset uart_reset
64 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
65 )(Ifc_slow_peripherals);
66 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
67 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
69 /*======= Module declarations for each peripheral =======*/
72 Ifc_clint clint <- mkclint();
75 Ifc_PLIC_AXI plic <- mkplicperipheral();
76 Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
77 Vector#(`INTERRUPT_PINS, FIFO#(bit))
78 ff_gateway_queue <- replicateM(mkFIFO);
81 Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
83 Ifc_pinmux pinmux <- mkpinmux; // mandatory
86 /*=======================================================*/
88 AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `DATA,`USERSPACE)
89 slow_fabric <- mkAXI4_Lite_Fabric(fn_slow_address_mapping);
90 Ifc_AXI4Lite_AXI4_Bridge
91 bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
93 mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
94 /*======= Slave connections to AXI4Lite fabric =========*/
97 mkConnection (slow_fabric.v_to_slaves
98 [fromInteger(valueOf(CLINT_slave_num))],
102 mkConnection (slow_fabric.v_to_slaves
103 [fromInteger(valueOf(Plic_slave_num))],
104 plic.axi4_slave_plic); //
107 mkConnection (slow_fabric.v_to_slaves
108 [fromInteger(valueOf(AxiExp1_slave_num))],
109 axiexp1.axi_slave); //
112 /*========== pinmux connections ============*/
116 /*=================== PLIC Connections ==================== */
120 rule rl_completion_msg_from_plic;
121 let id <- plic.intrpt_completion;
124 $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id);
128 for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
129 rule deq_gateway_queue;
130 if(interrupt_id==fromInteger(i)) begin
131 ff_gateway_queue[i].deq;
133 $display($time,"Dequeing the Interrupt request for ID: %d",i);
138 /*TODO DMA interrupt need to be connected to the plic */
139 for(Integer i=1; i<8; i=i+1) begin
140 rule rl_connect_dma_interrupts_to_plic;
142 if(dma.interrupt_to_processor[i-1]==1'b1) begin
143 ff_gateway_queue[i].enq(1);
144 plic.ifc_external_irq[i].irq_frm_gateway(True);
147 ff_gateway_queue[i].enq(0);
153 /*======================================================= */
155 /* ===== interface definition =======*/
156 interface axi_slave=bridge.axi_slave;
157 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
159 method msip_int=clint.msip_int;
160 method mtip_int=clint.mtip_int;
161 method mtime=clint.mtime;
166 interface SP_dedicated_ios slow_ios;
167 /* template for dedicated peripherals
169 interface uart0_coe=uart0.coe_rs232;
172 interface uart1_coe=uart1.coe_rs232;
175 interface i2c0_out=i2c0.out;
178 interface i2c1_out=i2c1.out;
181 interface qspi0_out = qspi0.out;
184 interface qspi1_out = qspi1.out;
187 interface axiexp1_out=axiexp1.slave_out;
188 interface axiexp1_in=axiexp1.slave_in;
191 interface pwm_o = pwm_bus.pwm_io;
195 interface iocell_side=pinmux.iocell_side;
198 /*===================================*/