1 package slow_peripherals;
2 /*===== Project imports =====*/
3 import defined_types::*;
4 import AXI4_Lite_Fabric::*;
5 import AXI4_Lite_Types::*;
9 import AXI4Lite_AXI4_Bridge::*;
10 import slow_memory_map::*;
11 `include "instance_defines.bsv"
12 /* ==== define the number of slow peripheral irqs ==== */
14 /*===========================*/
15 /*=== package imports ===*/
18 import ClientServer::*;
19 import Connectable::*;
22 /*=======================*/
23 /*===== Import the slow peripherals ====*/
32 import axiexpansion ::*;
34 /*=====================================*/
36 /*===== interface declaration =====*/
37 interface SP_dedicated_ios;
39 interface Get#(Bit#(67)) axiexp1_out;
40 interface Put#(Bit#(67)) axiexp1_in;
43 interface Ifc_slow_peripherals;
44 interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
45 interface SP_dedicated_ios slow_ios;
47 method Bit#(1) msip_int;
48 method Bit#(1) mtip_int;
49 method Bit#(`DATA) mtime;
51 `ifdef PLIC method ActionValue#(SlowTuple2#(Bool,Bool)) intrpt_note;
53 interface IOCellSide iocell_side; // mandatory interface
58 /*================================*/
61 module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
62 Clock uart_clock, Reset uart_reset
63 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
64 )(Ifc_slow_peripherals);
65 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
66 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
68 /*======= Module declarations for each peripheral =======*/
71 Ifc_clint clint <- mkclint();
74 Ifc_PLIC_AXI plic <- mkplicperipheral();
75 Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
76 Vector#(`INTERRUPT_PINS, FIFO#(bit))
77 ff_gateway_queue <- replicateM(mkFIFO);
80 Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
82 Ifc_pinmux pinmux <- mkpinmux; // mandatory
84 /*=======================================================*/
86 AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
87 slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
88 Ifc_AXI4Lite_AXI4_Bridge
89 bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
91 mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
92 /*======= Slave connections to AXI4Lite fabric =========*/
95 mkConnection (slow_fabric.v_to_slaves
96 [fromInteger(valueOf(CLINT_slave_num))],
100 mkConnection (slow_fabric.v_to_slaves
101 [fromInteger(valueOf(Plic_slave_num))],
102 plic.axi4_slave_plic); //
105 mkConnection (slow_fabric.v_to_slaves
106 [fromInteger(valueOf(AxiExp1_slave_num))],
107 axiexp1.axi_slave); //
110 /*========== pinmux connections ============*/
114 /*=================== PLIC Connections ==================== */
118 rule rl_completion_msg_from_plic;
119 let id <- plic.intrpt_completion;
122 $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id);
126 for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
127 rule deq_gateway_queue;
128 if(interrupt_id==fromInteger(i)) begin
129 ff_gateway_queue[i].deq;
131 $display($time,"Dequeing the Interrupt request for ID: %d",i);
136 /*TODO DMA interrupt need to be connected to the plic */
137 for(Integer i=1; i<8; i=i+1) begin
138 rule rl_connect_dma_interrupts_to_plic;
140 if(dma.interrupt_to_processor[i-1]==1'b1) begin
141 ff_gateway_queue[i].enq(1);
142 plic.ifc_external_irq[i].irq_frm_gateway(True);
145 ff_gateway_queue[i].enq(0);
151 /*======================================================= */
153 /* ===== interface definition =======*/
154 interface axi_slave=bridge.axi_slave;
155 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
157 method msip_int=clint.msip_int;
158 method mtip_int=clint.mtip_int;
159 method mtime=clint.mtime;
164 interface SP_dedicated_ios slow_ios;
165 /* template for dedicated peripherals
167 interface uart0_coe=uart0.coe_rs232;
170 interface uart1_coe=uart1.coe_rs232;
173 interface i2c0_out=i2c0.out;
176 interface i2c1_out=i2c1.out;
179 interface qspi0_out = qspi0.out;
182 interface qspi1_out = qspi1.out;
185 interface axiexp1_out=axiexp1.slave_out;
186 interface axiexp1_in=axiexp1.slave_in;
189 interface pwm_o = pwm_bus.pwm_io;
193 interface iocell_side=pinmux.iocell_side;
196 /*===================================*/