4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
10 from ifacebase
import InterfacesBase
11 from bsv
.peripheral_gen
import PeripheralIface
12 from bsv
.peripheral_gen
import PeripheralInterfaces
16 """ pin interface declaration.
17 * name is the name of the pin
18 * ready, enabled and io all create a (* .... *) prefix
19 * action changes it to an "in" if true
22 def __init__(self
, name
,
35 self
.enabled
= enabled
38 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
39 self
.outenmode
= outenmode
41 # bsv will look like this (method declaration):
43 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
44 (*always_ready,always_enabled,result="io"*) method
45 Action io0_inputval (Bit#(1) in);
48 def ifacepfmt(self
, fmtfn
):
52 name
= fmtfn(self
.name_
)
57 res
+= "#(%s) %s;" % (self
.bitspec
, name
)
60 def ifacefmt(self
, fmtfn
):
64 status
.append('always_ready')
66 status
.append('always_enabled')
68 status
.append('result="io"')
71 res
+= ','.join(status
)
76 name
= fmtfn(self
.name
)
80 res
+= ' (%s in)' % self
.bitspec
82 res
+= " %s " % self
.bitspec
87 def ifacedef(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
90 fmtname
= fmtinfn(self
.name
)
92 res
+= fmtdecfn(self
.name
)
93 res
+= '(%s in);\n' % self
.bitspec
94 res
+= ' %s<=in;\n' % fmtname
97 fmtname
= fmtoutfn(self
.name
)
98 res
+= "%s=%s;" % (self
.name
, fmtname
)
100 # sample bsv method definition :
102 method Action cell0_mux(Bit#(2) in);
107 # sample bsv wire (wire definiton):
109 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
112 def wirefmt(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
113 res
= ' Wire#(%s) ' % self
.bitspec
115 res
+= '%s' % fmtinfn(self
.name
)
117 res
+= '%s' % fmtoutfn(self
.name
)
118 res
+= "<-mkDWire(0);"
121 def ifacedef2(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
123 fmtname
= fmtinfn(self
.name
)
124 res
= " interface %s = interface Put\n" % self
.name_
127 #res += fmtdecfn(self.name)
128 res
+= '(%s in);\n' % self
.bitspec
129 res
+= ' %s<=in;\n' % fmtname
130 res
+= ' endmethod\n'
131 res
+= ' endinterface;'
133 fmtname
= fmtoutfn(self
.name
)
134 res
= " interface %s = interface Get\n" % self
.name_
135 res
+= ' method ActionValue#'
136 res
+= '(%s) get;\n' % self
.bitspec
137 res
+= " return %s;\n" % (fmtname
)
138 res
+= ' endmethod\n'
139 res
+= ' endinterface;'
142 def ifacedef3(self
, idx
, fmtoutfn
, fmtinfn
, fmtdecfn
):
144 fmtname
= fmtinfn(self
.name
)
145 if self
.name
.endswith('outen'):
149 res
= " %s <= in[%d];" % (fmtname
, idx
)
151 fmtname
= fmtoutfn(self
.name
)
152 res
= " tget[%d] = %s;" % (idx
, fmtname
)
157 class InterfaceFmt(object):
159 def ifacepfmtdecpin(self
, pin
):
160 return pin
.ifacepfmt(self
.ifacepfmtdecfn
)
162 def ifacepfmtdecfn(self
, name
):
165 def ifacefmtoutfn(self
, name
):
166 return "wr%s" % name
# like wruart
168 def ifacefmtdecfn2(self
, name
):
169 return name
# like: uart
171 def ifacefmtdecfn3(self
, name
):
173 return "%s_outen" % name
# like uart_outen
175 def ifacefmtinfn(self
, name
):
178 def ifacedef2pin(self
, pin
):
179 decfn
= self
.ifacefmtdecfn2
180 outfn
= self
.ifacefmtoutfn
181 # print pin, pin.outenmode
183 decfn
= self
.ifacefmtdecfn3
184 outfn
= self
.ifacefmtoutenfn
185 return pin
.ifacedef2(outfn
, self
.ifacefmtinfn
,
188 def vectorifacedef2(self
, pins
, count
, names
, bitfmt
, *args
):
194 # XXX HACK! assume in, out and inout, create set of indices
195 # that are repeated three times.
197 # ARG even worse hack for LCD *sigh*...
198 if names
[1] is None and names
[2] is None:
199 plens
= range(len(pins
))
201 for i
in range(0, len(pins
), 3):
202 plens
+= [i
/ 3, i
/ 3, i
/ 3]
203 for (typ
, txt
) in map(self
.ifacedef3pin
, plens
, pins
):
208 elif typ
== 'tputen':
210 tput
= '\n'.join(tput
).format(*args
)
211 tget
= '\n'.join(tget
).format(*args
)
212 tputen
= '\n'.join(tputen
).format(*args
)
213 bitfmt
= bitfmt
.format(count
)
215 interface {3} = interface Put#({0})
216 method Action put({2} in);
222 interface {3} = interface Put#({0})
223 method Action put({2} in);
229 interface {3} = interface Get#({0})
230 method ActionValue#({2}) get;
238 tlist
= [tput
, tputen
, tget
]
239 for i
, n
in enumerate(names
):
241 res
+= template
[i
].format(count
, tlist
[i
], bitfmt
, n
)
242 return '\n' + res
+ '\n'
245 class Interface(PeripheralIface
, InterfaceFmt
):
246 """ create an interface from a list of pinspecs.
247 each pinspec is a dictionary, see Pin class arguments
248 single indicates that there is only one of these, and
249 so the name must *not* be extended numerically (see pname)
251 # sample interface object:
253 twiinterface_decl = Interface('twi',
254 [{'name': 'sda', 'outen': True},
255 {'name': 'scl', 'outen': True},
259 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
260 PeripheralIface
.__init
__(self
, ifacename
)
261 InterfaceFmt
.__init
__(self
)
262 self
.ifacename
= ifacename
263 self
.ganged
= ganged
or {}
264 self
.pins
= [] # a list of instances of class Pin
265 self
.pinspecs
= pinspecs
# a list of dictionary
268 for idx
, p
in enumerate(pinspecs
):
273 if p
.get('outen') is True: # special case, generate 3 pins
275 for psuffix
in ['out', 'outen', 'in']:
276 # changing the name (like sda) to (twi_sda_out)
277 _p
['name_'] = "%s_%s" % (p
['name'], psuffix
)
278 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
279 _p
['action'] = psuffix
!= 'in'
281 self
.pins
.append(Pin(**_p
))
282 # will look like {'name': 'twi_sda_out', 'action': True}
283 # {'name': 'twi_sda_outen', 'action': True}
284 #{'name': 'twi_sda_in', 'action': False}
285 # NOTice - outen key is removed
288 if name
.isdigit(): # HACK! deals with EINT case
289 name
= self
.pname(name
)
292 _p
['name'] = self
.pname(p
['name'])
293 self
.pins
.append(Pin(**_p
))
295 # sample interface object:
297 uartinterface_decl = Interface('uart',
299 {'name': 'tx', 'action': True},
303 getifacetype is called multiple times in actual_pinmux.py
304 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
305 Purpose is to identify is function : input/output/inout
308 def getifacetype(self
, name
):
309 for p
in self
.pinspecs
:
310 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
311 # print "search", self.ifacename, name, fname
321 """ generates the interface spec e.g. flexbus_ale
322 if there is only one flexbus interface, or
323 sd{0}_cmd if there are several. string format
324 function turns this into sd0_cmd, sd1_cmd as
325 appropriate. single mode stops the numerical extension.
328 return self
.ifacename
329 return '%s{0}' % self
.ifacename
331 def pname(self
, name
):
332 """ generates the interface spec e.g. flexbus_ale
333 if there is only one flexbus interface, or
334 sd{0}_cmd if there are several. string format
335 function turns this into sd0_cmd, sd1_cmd as
336 appropriate. single mode stops the numerical extension.
338 return "%s_%s" % (self
.iname(), name
)
340 def busfmt(self
, *args
):
341 """ this function creates a bus "ganging" system based
342 on input from the {interfacename}.txt file.
343 only inout pins that are under the control of the
344 interface may be "ganged" together.
347 return '' # when self.ganged is None
350 for (k
, pnames
) in self
.ganged
.items():
351 name
= self
.pname('%senable' % k
).format(*args
)
352 decl
= 'Bit#(1) %s = 0;' % name
355 for p
in self
.pinspecs
:
356 if p
['name'] not in pnames
:
358 pname
= self
.pname(p
['name']).format(*args
)
359 if p
.get('outen') is True:
360 outname
= self
.ifacefmtoutfn(pname
)
361 ganged
.append("%s_outen" % outname
) # match wirefmt
363 gangedfmt
= '{%s} = duplicate(%s);'
364 res
.append(gangedfmt
% (',\n '.join(ganged
), name
))
365 return '\n'.join(res
) + '\n\n'
367 def wirefmt(self
, *args
):
368 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
372 def ifacepfmt(self
, *args
):
373 res
= '\n'.join(map(self
.ifacepfmtdecpin
, self
.pins
)).format(*args
)
374 return '\n' + res
# pins is a list
376 def ifacefmt(self
, *args
):
377 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
378 return '\n' + res
# pins is a list
380 def ifacefmtdecfn(self
, name
):
381 return name
# like: uart
383 def wirefmtpin(self
, pin
):
384 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
387 def ifacefmtdecpin(self
, pin
):
388 return pin
.ifacefmt(self
.ifacefmtdecfn
)
390 def ifacefmtpin(self
, pin
):
391 decfn
= self
.ifacefmtdecfn2
392 outfn
= self
.ifacefmtoutfn
393 # print pin, pin.outenmode
395 decfn
= self
.ifacefmtdecfn3
396 outfn
= self
.ifacefmtoutenfn
397 return pin
.ifacedef(outfn
, self
.ifacefmtinfn
,
400 def ifacedef(self
, *args
):
401 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
402 res
= res
.format(*args
)
403 return '\n' + res
+ '\n'
405 def ifacedef2(self
, *args
):
406 res
= '\n'.join(map(self
.ifacedef2pin
, self
.pins
))
407 res
= res
.format(*args
)
408 return '\n' + res
+ '\n'
411 class MuxInterface(Interface
):
413 def wirefmt(self
, *args
):
414 return muxwire
.format(*args
)
417 class IOInterface(Interface
):
419 def ifacefmtoutenfn(self
, name
):
420 return "cell{0}_mux_outen"
422 def ifacefmtoutfn(self
, name
):
423 """ for now strip off io{0}_ part """
424 return "cell{0}_mux_out"
426 def ifacefmtinfn(self
, name
):
427 return "cell{0}_mux_in"
429 def wirefmt(self
, *args
):
430 return generic_io
.format(*args
)
433 class InterfaceBus(InterfaceFmt
):
435 def __init__(self
, pins
, is_inout
, namelist
, bitspec
, filterbus
):
436 InterfaceFmt
.__init
__(self
)
437 self
.namelist
= namelist
438 self
.bitspec
= bitspec
439 self
.fbus
= filterbus
# filter identifying which are bus pins
441 self
.is_inout
= is_inout
442 self
.buspins
= filter(lambda x
: x
.name_
.startswith(self
.fbus
),
444 self
.nonbuspins
= filter(lambda x
: not x
.name_
.startswith(self
.fbus
),
447 def get_nonbuspins(self
):
448 return self
.nonbuspins
450 def get_buspins(self
):
453 def get_n_iopinsdiv(self
):
454 return 3 if self
.is_inout
else 1
456 def ifacepfmt(self
, *args
):
457 pins
= self
.get_nonbuspins()
458 res
= '\n'.join(map(self
.ifacepfmtdecpin
, pins
)).format(*args
)
459 res
= res
.format(*args
)
461 pins
= self
.get_buspins()
462 plen
= len(pins
) / self
.get_n_iopinsdiv()
465 template
= " interface {1}#(%s) {2};\n" % self
.bitspec
466 for i
, n
in enumerate(self
.namelist
):
469 ftype
= 'Get' if i
== 2 else "Put"
470 res
+= template
.format(plen
, ftype
, n
)
474 def ifacedef2(self
, *args
):
475 pins
= self
.get_nonbuspins()
476 res
= '\n'.join(map(self
.ifacedef2pin
, pins
))
477 res
= res
.format(*args
)
479 pins
= self
.get_buspins()
480 plen
= len(pins
) / self
.get_n_iopinsdiv()
482 print "ifbus pins", pin
.name_
, plen
483 bitspec
= self
.bitspec
.format(plen
)
484 return '\n' + res
+ self
.vectorifacedef2(
485 pins
, plen
, self
.namelist
, bitspec
, *args
)
487 def ifacedef3pin(self
, idx
, pin
):
488 decfn
= self
.ifacefmtdecfn2
489 outfn
= self
.ifacefmtoutfn
490 # print pin, pin.outenmode
492 decfn
= self
.ifacefmtdecfn3
493 outfn
= self
.ifacefmtoutenfn
494 return pin
.ifacedef3(idx
, outfn
, self
.ifacefmtinfn
,
498 class InterfaceMultiBus(object):
500 def __init__(self
, pins
):
501 self
.multibus_specs
= []
502 self
.nonbuspins
= pins
503 self
.nonb
= self
.add_bus(False, [], '', "xxxxxxxnofilter")
505 def add_bus(self
, is_inout
, namelist
, bitspec
, filterbus
):
506 pins
= self
.nonbuspins
507 buspins
= filter(lambda x
: x
.name_
.startswith(filterbus
), pins
)
508 nbuspins
= filter(lambda x
: not x
.name_
.startswith(filterbus
), pins
)
509 self
.nonbuspins
= nbuspins
510 b
= InterfaceBus(buspins
, is_inout
,
511 namelist
, bitspec
, filterbus
)
512 print "add bus", is_inout
, namelist
, filterbus
, \
513 map(lambda x
: x
.name_
, buspins
), \
514 map(lambda x
: x
.name_
, nbuspins
)
515 self
.multibus_specs
.append(b
)
516 self
.multibus_specs
[0].pins_
= nbuspins
517 self
.multibus_specs
[0].nonbuspins
= nbuspins
518 #self.nonbuspins = nbuspins
520 def ifacepfmt(self
, *args
):
522 #res = Interface.ifacepfmt(self, *args)
523 for b
in self
.multibus_specs
:
524 res
+= b
.ifacepfmt(*args
)
527 def ifacedef2(self
, *args
):
529 #res = Interface.ifacedef2(self, *args)
530 for b
in self
.multibus_specs
:
531 res
+= b
.ifacedef2(*args
)
535 class InterfaceLCD(InterfaceBus
, Interface
):
537 def __init__(self
, *args
):
538 Interface
.__init
__(self
, *args
)
539 InterfaceBus
.__init
__(self
, self
.pins
, False, ['data_out', None, None],
543 class InterfaceSDRAM(InterfaceMultiBus
, Interface
):
545 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
546 Interface
.__init
__(self
, ifacename
, pinspecs
, ganged
, single
)
547 InterfaceMultiBus
.__init
__(self
, self
.pins
)
548 self
.add_bus(False, ['dqm', None, None],
549 "Bit#({0})", "sdrdqm")
550 self
.add_bus(True, ['d_out', 'd_out_en', 'd_in'],
552 self
.add_bus(False, ['ad', None, None],
553 "Bit#({0})", "sdrad")
554 self
.add_bus(False, ['ba', None, None],
555 "Bit#({0})", "sdrba")
557 def ifacedef2(self
, *args
):
558 return InterfaceMultiBus
.ifacedef2(self
, *args
)
561 class InterfaceFlexBus(InterfaceMultiBus
, Interface
):
563 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
564 Interface
.__init
__(self
, ifacename
, pinspecs
, ganged
, single
)
565 InterfaceMultiBus
.__init
__(self
, self
.pins
)
566 self
.add_bus(True, ['ad_out', 'ad_out_en', 'ad_in'],
568 self
.add_bus(False, ['bwe', None, None],
570 self
.add_bus(False, ['tsiz', None, None],
572 self
.add_bus(False, ['cs', None, None],
575 def ifacedef2(self
, *args
):
576 return InterfaceMultiBus
.ifacedef2(self
, *args
)
579 class InterfaceSD(InterfaceMultiBus
, Interface
):
581 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
582 Interface
.__init
__(self
, ifacename
, pinspecs
, ganged
, single
)
583 InterfaceMultiBus
.__init
__(self
, self
.pins
)
584 self
.add_bus(True, ['out', 'out_en', 'in'],
587 def ifacedef2(self
, *args
):
588 return InterfaceMultiBus
.ifacedef2(self
, *args
)
591 class InterfaceNSPI(InterfaceBus
, Interface
):
593 def __init__(self
, *args
):
594 Interface
.__init
__(self
, *args
)
595 InterfaceBus
.__init
__(self
, self
.pins
, True,
596 ['io_out', 'io_out_en', 'io_in'],
600 class InterfaceEINT(Interface
):
601 """ uses old-style (non-get/put) for now
604 def ifacepfmt(self
, *args
):
605 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
606 return '\n' + res
# pins is a list
608 def ifacedef2(self
, *args
):
609 return self
.ifacedef(*args
)
612 class InterfaceGPIO(InterfaceBus
, Interface
):
613 """ note: the busfilter cuts out everything as the entire set of pins
614 is a bus, but it's less code. get_nonbuspins returns empty list.
617 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
618 Interface
.__init
__(self
, ifacename
, pinspecs
, ganged
, single
)
619 InterfaceBus
.__init
__(self
, self
.pins
, True, ['out', 'out_en', 'in'],
620 "Vector#({0},Bit#(1))", ifacename
[-1])
623 class Interfaces(InterfacesBase
, PeripheralInterfaces
):
624 """ contains a list of interface definitions
627 def __init__(self
, pth
=None):
628 InterfacesBase
.__init
__(self
, Interface
, pth
,
629 {'gpio': InterfaceGPIO
,
630 'spi': InterfaceNSPI
,
631 'mspi': InterfaceNSPI
,
635 'fb': InterfaceFlexBus
,
636 'sdr': InterfaceSDRAM
,
637 'qspi': InterfaceNSPI
,
638 'mqspi': InterfaceNSPI
,
639 'eint': InterfaceEINT
})
640 PeripheralInterfaces
.__init
__(self
)
642 def ifacedef(self
, f
, *args
):
643 for (name
, count
) in self
.ifacecount
:
644 for i
in range(count
):
645 f
.write(self
.data
[name
].ifacedef(i
))
647 def ifacedef2(self
, f
, *args
):
648 c
= " interface {0} = interface PeripheralSide{1}"
649 for (name
, count
) in self
.ifacecount
:
650 for i
in range(count
):
651 iname
= self
.data
[name
].iname().format(i
)
652 f
.write(c
.format(iname
, name
.upper()))
653 f
.write(self
.data
[name
].ifacedef2(i
))
654 f
.write(" endinterface;\n\n")
656 def busfmt(self
, f
, *args
):
657 f
.write("import BUtils::*;\n\n")
658 for (name
, count
) in self
.ifacecount
:
659 for i
in range(count
):
660 bf
= self
.data
[name
].busfmt(i
)
663 def ifacepfmt(self
, f
, *args
):
665 // interface declaration between {0} and pinmux
666 (*always_ready,always_enabled*)
667 interface PeripheralSide{0};'''
668 for (name
, count
) in self
.ifacecount
:
669 f
.write(comment
.format(name
.upper()))
670 f
.write(self
.data
[name
].ifacepfmt(0))
671 f
.write("\n endinterface\n")
673 def ifacefmt(self
, f
, *args
):
675 // interface declaration between %s-{0} and pinmux'''
676 for (name
, count
) in self
.ifacecount
:
677 for i
in range(count
):
678 c
= comment
% name
.upper()
680 f
.write(self
.data
[name
].ifacefmt(i
))
682 def ifacefmt2(self
, f
, *args
):
684 interface PeripheralSide{0} {1};'''
685 for (name
, count
) in self
.ifacecount
:
686 for i
in range(count
):
687 iname
= self
.data
[name
].iname().format(i
)
688 f
.write(comment
.format(name
.upper(), iname
))
690 def wirefmt(self
, f
, *args
):
691 comment
= '\n // following wires capture signals ' \
692 'to IO CELL if %s-{0} is\n' \
694 for (name
, count
) in self
.ifacecount
:
695 for i
in range(count
):
698 f
.write(self
.data
[name
].wirefmt(i
))
701 # ========= Interface declarations ================ #
703 mux_interface
= MuxInterface('cell',
704 [{'name': 'mux', 'ready': False, 'enabled': False,
705 'bitspec': '{1}', 'action': True}])
707 io_interface
= IOInterface(
709 [{'name': 'cell_out', 'enabled': True, },
710 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
711 {'name': 'cell_in', 'action': True, 'io': True}, ])
713 # == Peripheral Interface definitions == #
714 # these are the interface of the peripherals to the pin mux
715 # Outputs from the peripherals will be inputs to the pinmux
716 # module. Hence the change in direction for most pins
718 # ======================================= #
721 if __name__
== '__main__':
723 uartinterface_decl
= Interface('uart',
725 {'name': 'tx', 'action': True},
728 twiinterface_decl
= Interface('twi',
729 [{'name': 'sda', 'outen': True},
730 {'name': 'scl', 'outen': True},
733 def _pinmunge(p
, sep
, repl
, dedupe
=True):
734 """ munges the text so it's easier to compare.
735 splits by separator, strips out blanks, re-joins.
740 p
= filter(lambda x
: x
, p
) # filter out blanks
744 """ munges the text so it's easier to compare.
746 # first join lines by semicolons, strip out returns
748 p
= map(lambda x
: x
.replace('\n', ''), p
)
750 # now split first by brackets, then spaces (deduping on spaces)
751 p
= _pinmunge(p
, "(", " ( ", False)
752 p
= _pinmunge(p
, ")", " ) ", False)
753 p
= _pinmunge(p
, " ", " ")
759 for p1
, p2
in zip(l1
, l2
):
765 ifaces
= Interfaces()
767 ifaceuart
= ifaces
['uart']
768 print (ifaceuart
.ifacedef(0))
769 print (uartinterface_decl
.ifacedef(0))
770 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
772 ifacetwi
= ifaces
['twi']
773 print (ifacetwi
.ifacedef(0))
774 print (twiinterface_decl
.ifacedef(0))
775 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)