3 from UserDict
import UserDict
5 from wire_def
import generic_io
# special case
6 from wire_def
import muxwire
# special case
10 """ pin interface declaration.
11 * name is the name of the pin
12 * ready, enabled and io all create a (* .... *) prefix
13 * action changes it to an "in" if true
16 def __init__(self
, name
,
24 self
.enabled
= enabled
27 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
29 def ifacefmt(self
, fmtfn
=None):
33 status
.append('always_ready')
35 status
.append('always_enabled')
37 status
.append('result="io"')
40 res
+= ','.join(status
)
45 name
= fmtfn(self
.name
)
49 res
+= ' (%s in)' % self
.bitspec
51 res
+= " %s " % self
.bitspec
56 def ifacedef(self
, fmtoutfn
=None, fmtinfn
=None, fmtdecfn
=None):
59 fmtname
= fmtinfn(self
.name
)
61 res
+= fmtdecfn(self
.name
)
62 res
+= '(%s in);\n' % self
.bitspec
63 res
+= ' %s<=in;\n' % fmtname
66 fmtname
= fmtoutfn(self
.name
)
67 res
+= "%s=%s;" % (self
.name
, fmtname
)
70 def wirefmt(self
, fmtoutfn
=None, fmtinfn
=None, fmtdecfn
=None):
71 res
= ' Wire#(%s) ' % self
.bitspec
73 res
+= '%s' % fmtinfn(self
.name
)
75 res
+= '%s' % fmtoutfn(self
.name
)
76 res
+= "<-mkDWire(0);"
80 class Interface(object):
81 """ create an interface from a list of pinspecs.
82 each pinspec is a dictionary, see Pin class arguments
83 single indicates that there is only one of these, and
84 so the name must *not* be extended numerically (see pname)
87 def __init__(self
, ifacename
, pinspecs
, single
=False):
88 self
.ifacename
= ifacename
90 self
.pinspecs
= pinspecs
95 if p
.get('outen') is True: # special case, generate 3 pins
97 for psuffix
in ['out', 'outen', 'in']:
98 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
99 _p
['action'] = psuffix
!= 'in'
100 self
.pins
.append(Pin(**_p
))
102 _p
['name'] = self
.pname(p
['name'])
103 self
.pins
.append(Pin(**_p
))
105 def getifacetype(self
, name
):
106 for p
in self
.pinspecs
:
107 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
108 print "search", self
.ifacename
, name
, fname
117 def pname(self
, name
):
118 """ generates the interface spec e.g. flexbus_ale
119 if there is only one flexbus interface, or
120 sd{0}_cmd if there are several. string format
121 function turns this into sd0_cmd, sd1_cmd as
122 appropriate. single mode stops the numerical extension.
125 return '%s_%s' % (self
.ifacename
, name
)
126 return '%s{0}_%s' % (self
.ifacename
, name
)
128 def wirefmt(self
, *args
):
129 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
131 for p
in self
.pinspecs
:
132 name
= self
.pname(p
['name']).format(*args
)
133 res
+= " GenericIOType %s_io = GenericIOType{\n" % name
135 if p
.get('outen') is True:
136 outname
= self
.ifacefmtoutfn(name
)
137 params
.append('outputval:%s_out,' % outname
)
138 params
.append('output_en:%s_outen,' % outname
)
139 params
.append('input_en:~%s_outen,' % outname
)
140 elif p
.get('action'):
141 outname
= self
.ifacefmtoutfn(name
)
142 params
.append('outputval:%s,' % outname
)
143 params
.append('output_en:1,')
144 params
.append('input_en:0,')
146 params
.append('outputval:0,')
147 params
.append('output_en:0,')
148 params
.append('input_en:1,')
149 params
+= ['pullup_en:0,', 'pulldown_en:0,',
150 'pushpull_en:0,', 'drivestrength:0,',
153 res
+= ' %s\n' % param
157 def ifacefmt(self
, *args
):
158 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
161 def ifacefmtdecfn(self
, name
):
164 def ifacefmtdecfn2(self
, name
):
167 def ifacefmtoutfn(self
, name
):
170 def ifacefmtinfn(self
, name
):
173 def wirefmtpin(self
, pin
):
174 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
177 def ifacefmtdecpin(self
, pin
):
178 return pin
.ifacefmt(self
.ifacefmtdecfn
)
180 def ifacefmtpin(self
, pin
):
181 return pin
.ifacedef(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
184 def ifacedef(self
, *args
):
185 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
186 res
= res
.format(*args
)
187 return '\n' + res
+ '\n'
190 class MuxInterface(Interface
):
192 def wirefmt(self
, *args
):
193 return muxwire
.format(*args
)
196 class IOInterface(Interface
):
198 def ifacefmtoutfn(self
, name
):
199 """ for now strip off io{0}_ part """
200 return "cell{0}_mux_out"
202 def ifacefmtinfn(self
, name
):
203 return "cell{0}_mux_in"
205 def wirefmt(self
, *args
):
206 return generic_io
.format(*args
)
209 class Interfaces(UserDict
):
210 """ contains a list of interface definitions
213 def __init__(self
, pth
):
216 UserDict
.__init
__(self
, {})
217 ift
= 'interfaces.txt'
219 ift
= os
.path
.join(pth
, ift
)
220 with
open(ift
, 'r') as ifile
:
221 for ln
in ifile
.readlines():
226 spec
= self
.read_spec(pth
, name
)
227 self
.ifaceadd(name
, count
, Interface(name
, spec
, count
==1))
229 def getifacetype(self
, fname
):
230 # finds the interface type, e.g sd_d0 returns "inout"
231 for iface
in self
.values():
232 typ
= iface
.getifacetype(fname
)
237 def ifaceadd(self
, name
, count
, iface
, at
=None):
239 at
= len(self
.ifacecount
)
240 self
.ifacecount
.insert(at
, (name
, count
))
243 def read_spec(self
, pth
, name
):
245 fname
= '%s.txt' % name
247 ift
= os
.path
.join(pth
, fname
)
248 with
open(ift
, 'r') as sfile
:
249 for ln
in sfile
.readlines():
255 elif ln
[1] == 'inout':
260 def ifacedef(self
, f
, *args
):
261 for (name
, count
) in self
.ifacecount
:
262 for i
in range(count
):
263 f
.write(self
.data
[name
].ifacedef(i
))
265 def ifacefmt(self
, f
, *args
):
267 // interface declaration between %s-{0} and pinmux'''
268 for (name
, count
) in self
.ifacecount
:
269 for i
in range(count
):
270 c
= comment
% name
.upper()
272 f
.write(self
.data
[name
].ifacefmt(i
))
274 def wirefmt(self
, f
, *args
):
275 comment
= '\n // following wires capture signals ' \
276 'to IO CELL if %s-{0} is\n' \
278 for (name
, count
) in self
.ifacecount
:
279 for i
in range(count
):
282 f
.write(self
.data
[name
].wirefmt(i
))
285 # ========= Interface declarations ================ #
287 mux_interface
= MuxInterface('cell', [{'name': 'mux', 'ready': False,
289 'bitspec': '{1}', 'action': True}])
291 io_interface
= IOInterface('io',
292 [{'name': 'cell', 'enabled': False, 'bitspec': 'GenericIOType'},
293 {'name': 'inputval', 'action': True, 'io': True},
296 # == Peripheral Interface definitions == #
297 # these are the interface of the peripherals to the pin mux
298 # Outputs from the peripherals will be inputs to the pinmux
299 # module. Hence the change in direction for most pins
301 # ======================================= #
304 if __name__
== '__main__':
306 uartinterface_decl
= Interface('uart',
308 {'name': 'tx', 'action': True},
311 twiinterface_decl
= Interface('twi',
312 [{'name': 'sda', 'outen': True},
313 {'name': 'scl', 'outen': True},
316 def _pinmunge(p
, sep
, repl
, dedupe
=True):
317 """ munges the text so it's easier to compare.
318 splits by separator, strips out blanks, re-joins.
323 p
= filter(lambda x
: x
, p
) # filter out blanks
327 """ munges the text so it's easier to compare.
329 # first join lines by semicolons, strip out returns
331 p
= map(lambda x
: x
.replace('\n', ''), p
)
333 # now split first by brackets, then spaces (deduping on spaces)
334 p
= _pinmunge(p
, "(", " ( ", False)
335 p
= _pinmunge(p
, ")", " ) ", False)
336 p
= _pinmunge(p
, " ", " ")
342 for p1
, p2
in zip(l1
, l2
):
348 ifaces
= Interfaces()
350 ifaceuart
= ifaces
['uart']
351 print ifaceuart
.ifacedef(0)
352 print uartinterface_decl
.ifacedef(0)
353 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
355 ifacetwi
= ifaces
['twi']
356 print ifacetwi
.ifacedef(0)
357 print twiinterface_decl
.ifacedef(0)
358 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)