4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
10 from ifacebase
import InterfacesBase
11 from bsv
.peripheral_gen
import PeripheralIface
12 from bsv
.peripheral_gen
import PeripheralInterfaces
16 """ pin interface declaration.
17 * name is the name of the pin
18 * ready, enabled and io all create a (* .... *) prefix
19 * action changes it to an "in" if true
22 def __init__(self
, name
,
35 self
.enabled
= enabled
38 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
39 self
.outenmode
= outenmode
41 # bsv will look like this (method declaration):
43 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
44 (*always_ready,always_enabled,result="io"*) method
45 Action io0_inputval (Bit#(1) in);
48 def ifacepfmt(self
, fmtfn
):
52 name
= fmtfn(self
.name_
)
57 res
+= "#(%s) %s;" % (self
.bitspec
, name
)
60 def ifacefmt(self
, fmtfn
):
64 status
.append('always_ready')
66 status
.append('always_enabled')
68 status
.append('result="io"')
71 res
+= ','.join(status
)
76 name
= fmtfn(self
.name
)
80 res
+= ' (%s in)' % self
.bitspec
82 res
+= " %s " % self
.bitspec
87 def ifacedef(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
90 fmtname
= fmtinfn(self
.name
)
92 res
+= fmtdecfn(self
.name
)
93 res
+= '(%s in);\n' % self
.bitspec
94 res
+= ' %s<=in;\n' % fmtname
97 fmtname
= fmtoutfn(self
.name
)
98 res
+= "%s=%s;" % (self
.name
, fmtname
)
100 # sample bsv method definition :
102 method Action cell0_mux(Bit#(2) in);
107 # sample bsv wire (wire definiton):
109 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
112 def wirefmt(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
113 res
= ' Wire#(%s) ' % self
.bitspec
115 res
+= '%s' % fmtinfn(self
.name
)
117 res
+= '%s' % fmtoutfn(self
.name
)
118 res
+= "<-mkDWire(0);"
121 def ifacedef2(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
123 fmtname
= fmtinfn(self
.name
)
124 res
= " interface %s = interface Put\n" % self
.name_
127 #res += fmtdecfn(self.name)
128 res
+= '(%s in);\n' % self
.bitspec
129 res
+= ' %s<=in;\n' % fmtname
130 res
+= ' endmethod\n'
131 res
+= ' endinterface;'
133 fmtname
= fmtoutfn(self
.name
)
134 res
= " interface %s = interface Get\n" % self
.name_
135 res
+= ' method ActionValue#'
136 res
+= '(%s) get;\n' % self
.bitspec
137 res
+= " return %s;\n" % (fmtname
)
138 res
+= ' endmethod\n'
139 res
+= ' endinterface;'
142 def ifacedef3(self
, idx
, fmtoutfn
, fmtinfn
, fmtdecfn
):
144 fmtname
= fmtinfn(self
.name
)
145 if self
.name
.endswith('outen'):
149 res
= " %s <= in[%d];" % (fmtname
, idx
)
151 fmtname
= fmtoutfn(self
.name
)
152 res
= " tget[%d] = %s;" % (idx
, fmtname
)
157 class InterfaceFmt(object):
159 def ifacepfmtdecpin(self
, pin
):
160 return pin
.ifacepfmt(self
.ifacepfmtdecfn
)
162 def ifacepfmtdecfn(self
, name
):
165 def ifacefmtoutfn(self
, name
):
166 return "wr%s" % name
# like wruart
168 def ifacefmtdecfn2(self
, name
):
169 return name
# like: uart
171 def ifacefmtdecfn3(self
, name
):
173 return "%s_outen" % name
# like uart_outen
175 def ifacefmtinfn(self
, name
):
178 def ifacedef2pin(self
, pin
):
179 decfn
= self
.ifacefmtdecfn2
180 outfn
= self
.ifacefmtoutfn
181 # print pin, pin.outenmode
183 decfn
= self
.ifacefmtdecfn3
184 outfn
= self
.ifacefmtoutenfn
185 return pin
.ifacedef2(outfn
, self
.ifacefmtinfn
,
188 def vectorifacedef2(self
, pins
, count
, names
, bitfmt
, *args
):
194 # XXX HACK! assume in, out and inout, create set of indices
195 # that are repeated three times.
197 # ARG even worse hack for LCD *sigh*...
198 if names
[1] is None and names
[2] is None:
199 plens
= range(len(pins
))
201 for i
in range(0, len(pins
), 3):
202 plens
+= [i
/ 3, i
/ 3, i
/ 3]
203 for (typ
, txt
) in map(self
.ifacedef3pin
, plens
, pins
):
208 elif typ
== 'tputen':
210 tput
= '\n'.join(tput
).format(*args
)
211 tget
= '\n'.join(tget
).format(*args
)
212 tputen
= '\n'.join(tputen
).format(*args
)
213 bitfmt
= bitfmt
.format(count
)
215 interface {3} = interface Put#({0})
216 method Action put({2} in);
222 interface {3} = interface Put#({0})
223 method Action put({2} in);
229 interface {3} = interface Get#({0})
230 method ActionValue#({2}) get;
238 tlist
= [tput
, tputen
, tget
]
239 for i
, n
in enumerate(names
):
241 res
+= template
[i
].format(count
, tlist
[i
], bitfmt
, n
)
242 return '\n' + res
+ '\n'
246 class Interface(PeripheralIface
, InterfaceFmt
):
247 """ create an interface from a list of pinspecs.
248 each pinspec is a dictionary, see Pin class arguments
249 single indicates that there is only one of these, and
250 so the name must *not* be extended numerically (see pname)
252 # sample interface object:
254 twiinterface_decl = Interface('twi',
255 [{'name': 'sda', 'outen': True},
256 {'name': 'scl', 'outen': True},
260 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
261 PeripheralIface
.__init
__(self
, ifacename
)
262 InterfaceFmt
.__init
__(self
)
263 self
.ifacename
= ifacename
264 self
.ganged
= ganged
or {}
265 self
.pins
= [] # a list of instances of class Pin
266 self
.pinspecs
= pinspecs
# a list of dictionary
269 for idx
, p
in enumerate(pinspecs
):
274 if p
.get('outen') is True: # special case, generate 3 pins
276 for psuffix
in ['out', 'outen', 'in']:
277 # changing the name (like sda) to (twi_sda_out)
278 _p
['name_'] = "%s_%s" % (p
['name'], psuffix
)
279 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
280 _p
['action'] = psuffix
!= 'in'
282 self
.pins
.append(Pin(**_p
))
283 # will look like {'name': 'twi_sda_out', 'action': True}
284 # {'name': 'twi_sda_outen', 'action': True}
285 #{'name': 'twi_sda_in', 'action': False}
286 # NOTice - outen key is removed
289 if name
.isdigit(): # HACK! deals with EINT case
290 name
= self
.pname(name
)
293 _p
['name'] = self
.pname(p
['name'])
294 self
.pins
.append(Pin(**_p
))
296 # sample interface object:
298 uartinterface_decl = Interface('uart',
300 {'name': 'tx', 'action': True},
304 getifacetype is called multiple times in actual_pinmux.py
305 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
306 Purpose is to identify is function : input/output/inout
309 def getifacetype(self
, name
):
310 for p
in self
.pinspecs
:
311 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
312 # print "search", self.ifacename, name, fname
322 """ generates the interface spec e.g. flexbus_ale
323 if there is only one flexbus interface, or
324 sd{0}_cmd if there are several. string format
325 function turns this into sd0_cmd, sd1_cmd as
326 appropriate. single mode stops the numerical extension.
329 return self
.ifacename
330 return '%s{0}' % self
.ifacename
332 def pname(self
, name
):
333 """ generates the interface spec e.g. flexbus_ale
334 if there is only one flexbus interface, or
335 sd{0}_cmd if there are several. string format
336 function turns this into sd0_cmd, sd1_cmd as
337 appropriate. single mode stops the numerical extension.
339 return "%s_%s" % (self
.iname(), name
)
341 def busfmt(self
, *args
):
342 """ this function creates a bus "ganging" system based
343 on input from the {interfacename}.txt file.
344 only inout pins that are under the control of the
345 interface may be "ganged" together.
348 return '' # when self.ganged is None
351 for (k
, pnames
) in self
.ganged
.items():
352 name
= self
.pname('%senable' % k
).format(*args
)
353 decl
= 'Bit#(1) %s = 0;' % name
356 for p
in self
.pinspecs
:
357 if p
['name'] not in pnames
:
359 pname
= self
.pname(p
['name']).format(*args
)
360 if p
.get('outen') is True:
361 outname
= self
.ifacefmtoutfn(pname
)
362 ganged
.append("%s_outen" % outname
) # match wirefmt
364 gangedfmt
= '{%s} = duplicate(%s);'
365 res
.append(gangedfmt
% (',\n '.join(ganged
), name
))
366 return '\n'.join(res
) + '\n\n'
368 def wirefmt(self
, *args
):
369 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
373 def ifacepfmt(self
, *args
):
374 res
= '\n'.join(map(self
.ifacepfmtdecpin
, self
.pins
)).format(*args
)
375 return '\n' + res
# pins is a list
377 def ifacefmt(self
, *args
):
378 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
379 return '\n' + res
# pins is a list
381 def ifacefmtdecfn(self
, name
):
382 return name
# like: uart
384 def wirefmtpin(self
, pin
):
385 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
388 def ifacefmtdecpin(self
, pin
):
389 return pin
.ifacefmt(self
.ifacefmtdecfn
)
391 def ifacefmtpin(self
, pin
):
392 decfn
= self
.ifacefmtdecfn2
393 outfn
= self
.ifacefmtoutfn
394 # print pin, pin.outenmode
396 decfn
= self
.ifacefmtdecfn3
397 outfn
= self
.ifacefmtoutenfn
398 return pin
.ifacedef(outfn
, self
.ifacefmtinfn
,
401 def ifacedef(self
, *args
):
402 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
403 res
= res
.format(*args
)
404 return '\n' + res
+ '\n'
406 def ifacedef2(self
, *args
):
407 res
= '\n'.join(map(self
.ifacedef2pin
, self
.pins
))
408 res
= res
.format(*args
)
409 return '\n' + res
+ '\n'
412 class MuxInterface(Interface
):
414 def wirefmt(self
, *args
):
415 return muxwire
.format(*args
)
418 class IOInterface(Interface
):
420 def ifacefmtoutenfn(self
, name
):
421 return "cell{0}_mux_outen"
423 def ifacefmtoutfn(self
, name
):
424 """ for now strip off io{0}_ part """
425 return "cell{0}_mux_out"
427 def ifacefmtinfn(self
, name
):
428 return "cell{0}_mux_in"
430 def wirefmt(self
, *args
):
431 return generic_io
.format(*args
)
434 class InterfaceBus(InterfaceFmt
):
436 def __init__(self
, pins
, is_inout
, namelist
, bitspec
, filterbus
):
437 InterfaceFmt
.__init
__(self
)
438 self
.namelist
= namelist
439 self
.bitspec
= bitspec
440 self
.fbus
= filterbus
# filter identifying which are bus pins
442 self
.is_inout
= is_inout
443 self
.buspins
= filter(lambda x
: x
.name_
.startswith(self
.fbus
),
445 self
.nonbuspins
= filter(lambda x
: not x
.name_
.startswith(self
.fbus
),
448 def get_nonbuspins(self
):
449 return self
.nonbuspins
451 def get_buspins(self
):
454 def get_n_iopinsdiv(self
):
455 return 3 if self
.is_inout
else 1
457 def ifacepfmt(self
, *args
):
458 pins
= self
.get_nonbuspins()
459 res
= '\n'.join(map(self
.ifacepfmtdecpin
, pins
)).format(*args
)
460 res
= res
.format(*args
)
462 pins
= self
.get_buspins()
463 plen
= len(pins
) / self
.get_n_iopinsdiv()
465 template
= " interface {1}#(%s) {2};\n" % self
.bitspec
466 for i
, n
in enumerate(self
.namelist
):
469 ftype
= 'Get' if i
== 2 else "Put"
470 res
+= template
.format(plen
, ftype
, n
)
474 def ifacedef2(self
, *args
):
475 pins
= self
.get_nonbuspins()
476 res
= '\n'.join(map(self
.ifacedef2pin
, pins
))
477 res
= res
.format(*args
)
479 pins
= self
.get_buspins()
480 plen
= len(pins
) / self
.get_n_iopinsdiv()
482 print "ifbus pins", pin
.name_
, plen
483 bitspec
= self
.bitspec
.format(plen
)
485 return '\n' + res
+ self
.vectorifacedef2(
486 pins
, plen
, self
.namelist
, bitspec
, *args
) + '\n'
488 def ifacedef3pin(self
, idx
, pin
):
489 decfn
= self
.ifacefmtdecfn2
490 outfn
= self
.ifacefmtoutfn
491 # print pin, pin.outenmode
493 decfn
= self
.ifacefmtdecfn3
494 outfn
= self
.ifacefmtoutenfn
495 return pin
.ifacedef3(idx
, outfn
, self
.ifacefmtinfn
,
499 class InterfaceMultiBus(object):
501 def __init__(self
, pins
):
502 self
.multibus_specs
= []
503 self
.nonbuspins
= pins
504 self
.nonb
= self
.add_bus(False, [], '', "xxxxxxxnofilter")
506 def add_bus(self
, is_inout
, namelist
, bitspec
, filterbus
):
507 pins
= self
.nonbuspins
508 buspins
= filter(lambda x
: x
.name_
.startswith(filterbus
), pins
)
509 nbuspins
= filter(lambda x
: not x
.name_
.startswith(filterbus
), pins
)
510 self
.nonbuspins
= nbuspins
511 b
= InterfaceBus(buspins
, is_inout
,
512 namelist
, bitspec
, filterbus
)
513 print is_inout
, namelist
, filterbus
, buspins
514 self
.multibus_specs
.append(b
)
515 self
.multibus_specs
[0].pins_
= nbuspins
516 self
.multibus_specs
[0].nonbuspins
= nbuspins
518 def ifacepfmt(self
, *args
):
520 #res = Interface.ifacepfmt(self, *args)
521 for b
in self
.multibus_specs
:
522 res
+= b
.ifacepfmt(*args
)
525 def ifacedef2(self
, *args
):
527 #res = Interface.ifacedef2(self, *args)
528 for b
in self
.multibus_specs
:
529 res
+= b
.ifacedef2(*args
)
533 class InterfaceLCD(InterfaceBus
, Interface
):
535 def __init__(self
, *args
):
536 Interface
.__init
__(self
, *args
)
537 InterfaceBus
.__init
__(self
, self
.pins
, False, ['data_out', None, None],
540 class InterfaceFlexBus(InterfaceMultiBus
, Interface
):
542 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
543 Interface
.__init
__(self
, ifacename
, pinspecs
, ganged
, single
)
544 InterfaceMultiBus
.__init
__(self
, self
.pins
)
545 self
.add_bus(True, ['ad_out', 'ad_out_en', 'ad_in'],
547 self
.add_bus(False, ['bwe', None, None],
549 self
.add_bus(False, ['tsiz', None, None],
551 self
.add_bus(False, ['cs', None, None],
554 def ifacedef2(self
, *args
):
555 return InterfaceMultiBus
.ifacedef2(self
, *args
)
557 class InterfaceSD(InterfaceBus
, Interface
):
559 def __init__(self
, *args
):
560 Interface
.__init
__(self
, *args
)
561 InterfaceBus
.__init
__(self
, self
.pins
, True, ['out', 'out_en', 'in'],
564 class InterfaceNSPI(InterfaceBus
, Interface
):
566 def __init__(self
, *args
):
567 Interface
.__init
__(self
, *args
)
568 InterfaceBus
.__init
__(self
, self
.pins
, True,
569 ['io_out', 'io_out_en', 'io_in'],
572 class InterfaceEINT(Interface
):
573 """ uses old-style (non-get/put) for now
576 def ifacepfmt(self
, *args
):
577 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
578 return '\n' + res
# pins is a list
580 def ifacedef2(self
, *args
):
581 return self
.ifacedef(*args
)
584 class InterfaceGPIO(InterfaceBus
, Interface
):
585 """ note: the busfilter cuts out everything as the entire set of pins
586 is a bus, but it's less code. get_nonbuspins returns empty list.
589 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
590 Interface
.__init
__(self
, ifacename
, pinspecs
, ganged
, single
)
591 InterfaceBus
.__init
__(self
, self
.pins
, True, ['out', 'out_en', 'in'],
592 "Vector#({0},Bit#(1))", ifacename
[-1])
594 class Interfaces(InterfacesBase
, PeripheralInterfaces
):
595 """ contains a list of interface definitions
598 def __init__(self
, pth
=None):
599 InterfacesBase
.__init
__(self
, Interface
, pth
,
600 {'gpio': InterfaceGPIO
,
601 'spi': InterfaceNSPI
,
602 'mspi': InterfaceNSPI
,
605 'fb': InterfaceFlexBus
,
606 'qspi': InterfaceNSPI
,
607 'mqspi': InterfaceNSPI
,
608 'eint': InterfaceEINT
})
609 PeripheralInterfaces
.__init
__(self
)
611 def ifacedef(self
, f
, *args
):
612 for (name
, count
) in self
.ifacecount
:
613 for i
in range(count
):
614 f
.write(self
.data
[name
].ifacedef(i
))
616 def ifacedef2(self
, f
, *args
):
617 c
= " interface {0} = interface PeripheralSide{1}"
618 for (name
, count
) in self
.ifacecount
:
619 for i
in range(count
):
620 iname
= self
.data
[name
].iname().format(i
)
621 f
.write(c
.format(iname
, name
.upper()))
622 f
.write(self
.data
[name
].ifacedef2(i
))
623 f
.write(" endinterface;\n\n")
625 def busfmt(self
, f
, *args
):
626 f
.write("import BUtils::*;\n\n")
627 for (name
, count
) in self
.ifacecount
:
628 for i
in range(count
):
629 bf
= self
.data
[name
].busfmt(i
)
632 def ifacepfmt(self
, f
, *args
):
634 // interface declaration between {0} and pinmux
635 (*always_ready,always_enabled*)
636 interface PeripheralSide{0};'''
637 for (name
, count
) in self
.ifacecount
:
638 f
.write(comment
.format(name
.upper()))
639 f
.write(self
.data
[name
].ifacepfmt(0))
640 f
.write("\n endinterface\n")
642 def ifacefmt(self
, f
, *args
):
644 // interface declaration between %s-{0} and pinmux'''
645 for (name
, count
) in self
.ifacecount
:
646 for i
in range(count
):
647 c
= comment
% name
.upper()
649 f
.write(self
.data
[name
].ifacefmt(i
))
651 def ifacefmt2(self
, f
, *args
):
653 interface PeripheralSide{0} {1};'''
654 for (name
, count
) in self
.ifacecount
:
655 for i
in range(count
):
656 iname
= self
.data
[name
].iname().format(i
)
657 f
.write(comment
.format(name
.upper(), iname
))
659 def wirefmt(self
, f
, *args
):
660 comment
= '\n // following wires capture signals ' \
661 'to IO CELL if %s-{0} is\n' \
663 for (name
, count
) in self
.ifacecount
:
664 for i
in range(count
):
667 f
.write(self
.data
[name
].wirefmt(i
))
670 # ========= Interface declarations ================ #
672 mux_interface
= MuxInterface('cell',
673 [{'name': 'mux', 'ready': False, 'enabled': False,
674 'bitspec': '{1}', 'action': True}])
676 io_interface
= IOInterface(
678 [{'name': 'cell_out', 'enabled': True, },
679 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
680 {'name': 'cell_in', 'action': True, 'io': True}, ])
682 # == Peripheral Interface definitions == #
683 # these are the interface of the peripherals to the pin mux
684 # Outputs from the peripherals will be inputs to the pinmux
685 # module. Hence the change in direction for most pins
687 # ======================================= #
690 if __name__
== '__main__':
692 uartinterface_decl
= Interface('uart',
694 {'name': 'tx', 'action': True},
697 twiinterface_decl
= Interface('twi',
698 [{'name': 'sda', 'outen': True},
699 {'name': 'scl', 'outen': True},
702 def _pinmunge(p
, sep
, repl
, dedupe
=True):
703 """ munges the text so it's easier to compare.
704 splits by separator, strips out blanks, re-joins.
709 p
= filter(lambda x
: x
, p
) # filter out blanks
713 """ munges the text so it's easier to compare.
715 # first join lines by semicolons, strip out returns
717 p
= map(lambda x
: x
.replace('\n', ''), p
)
719 # now split first by brackets, then spaces (deduping on spaces)
720 p
= _pinmunge(p
, "(", " ( ", False)
721 p
= _pinmunge(p
, ")", " ) ", False)
722 p
= _pinmunge(p
, " ", " ")
728 for p1
, p2
in zip(l1
, l2
):
734 ifaces
= Interfaces()
736 ifaceuart
= ifaces
['uart']
737 print (ifaceuart
.ifacedef(0))
738 print (uartinterface_decl
.ifacedef(0))
739 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
741 ifacetwi
= ifaces
['twi']
742 print (ifacetwi
.ifacedef(0))
743 print (twiinterface_decl
.ifacedef(0))
744 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)