7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
):
90 return "%(name)s%(ifacenum)dBase" % locals()
92 def axiend(self
, name
, ifacenum
):
94 return "%(name)s%(ifacenum)dEnd" % locals()
96 def axi_reg_def(self
, start
, name
, ifacenum
):
98 offs
= self
.num_axi_regs32() * 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
)
103 bend
= self
.axiend(name
, ifacenum
)
104 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_master_name(self
, name
, ifacenum
, typ
=''):
111 return "{0}{1}_master_num".format(name
, ifacenum
)
113 def axi_slave_name(self
, name
, ifacenum
, typ
=''):
115 return "{0}{1}_{2}slave_num".format(name
, ifacenum
, typ
)
117 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
118 name
= self
.axi_master_name(name
, ifacenum
, typ
)
119 return ("typedef {0} {1};".format(idx
, name
), 1)
121 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
122 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
123 return ("typedef {0} {1};".format(idx
, name
), 1)
125 def axi_fastaddr_map(self
, name
, ifacenum
):
126 return self
.axi_addr_map(name
, ifacenum
, 'fast')
128 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
129 bname
= self
.axibase(name
, ifacenum
)
130 bend
= self
.axiend(name
, ifacenum
)
131 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
133 if(addr>=`{0} && addr<=`{1})
134 return tuple2(True,fromInteger(valueOf({2})));
136 return template
.format(bname
, bend
, name
)
138 def _mk_pincon(self
, name
, count
, ptyp
):
139 # TODO: really should be using bsv.interface_decl.Interfaces
140 # pin-naming rules.... logic here is hard-coded to duplicate
141 # it (see Interface.__init__ outen)
143 for p
in self
.peripheral
.pinspecs
:
146 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
147 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
148 ret
.append("//%s %s" % (n
, str(p
)))
150 sname
= self
.get_iname(count
)
151 sname
= "{0}.{1}".format(sname
, pname
)
152 ps
= "slow_peripherals.%s" % sname
154 sname
= self
.peripheral
.iname().format(count
)
155 sname
= "{0}.{1}".format(sname
, pname
)
156 ps
= "pinmux.peripheral_side.%s" % sname
157 if typ
== 'out' or typ
== 'inout':
158 fname
= self
.pinname_out(pname
)
159 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
160 n_
= "{0}{1}".format(n
, count
)
168 cn
= self
._mk
_actual
_connection
('out', name
,
170 pname
, ps_
, n_
, fname
)
174 fname
= self
.pinname_outen(pname
)
176 if isinstance(fname
, str):
177 fname
= "{0}.{1}".format(n_
, fname
)
178 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
179 cn
= self
._mk
_actual
_connection
('outen', name
,
183 if typ
== 'in' or typ
== 'inout':
184 fname
= self
.pinname_in(pname
)
190 n_
= "{0}{1}".format(n
, count
)
191 n_
= '{0}.{1}'.format(n_
, fname
)
192 n_
= self
.ifname_tweak(pname
, 'in', n_
)
193 cn
= self
._mk
_actual
_connection
('in', name
,
195 pname
, ps_
, n_
, fname
)
197 return '\n'.join(ret
)
199 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
200 pname
, ps
, n
, fname
):
202 ck
= self
.get_clock_reset(name
, count
)
204 if ck
== PBase
.get_clock_reset(self
, name
, count
):
205 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
206 .format(ps
, n
, fname
))
208 n2
= "{0}{1}".format(name
, count
)
209 sync
= '{0}_{1}_sync'.format(n2
, pname
)
210 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
212 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
213 .format(sync
, n
, fname
))
214 elif ctype
== 'outen':
215 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
218 if ck
== PBase
.get_clock_reset(self
, name
, count
):
219 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
222 n2
= "{0}{1}".format(name
, count
)
223 sync
= '{0}_{1}_sync'.format(n2
, pname
)
224 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
226 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
230 def _mk_clk_con(self
, name
, count
, ctype
):
232 ck
= self
.get_clock_reset(name
, count
)
233 if ck
== PBase
.get_clock_reset(self
, name
, count
):
236 spc
= "sp_clock, sp_reset"
239 ck
= "core_clock, core_reset"
241 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
243 for p
in self
.peripheral
.pinspecs
:
247 if typ
== 'out' or typ
== 'inout':
248 fname
= self
.pinname_out(pname
)
251 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
252 n_
= "{0}{1}".format(n
, count
)
255 n_
= '{0}_{1}'.format(n_
, pname
)
256 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
257 if typ
== 'in' or typ
== 'inout':
258 fname
= self
.pinname_in(pname
)
261 #fname = self.pinname_in(pname)
262 n_
= "{0}{1}".format(n
, count
)
263 n_
= '{0}_{1}'.format(n_
, pname
)
264 #n_ = self.ifname_tweak(pname, 'in', n_)
265 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
266 return '\n'.join(ret
)
269 def mk_cellconn(self
, *args
):
272 def mkfast_peripheral(self
, size
=0):
275 def mkslow_peripheral(self
, size
=0):
278 def mksuffix(self
, name
, i
):
281 def __mk_connection(self
, con
, aname
, fabricname
):
282 txt
= "mkConnection ({2}.v_to_slaves\n" + \
283 " [fromInteger(valueOf({1}))],\n" + \
286 print "PBase __mk_connection", self
.name
, aname
289 return txt
.format(con
, aname
, fabricname
)
291 def __mk_master_connection(self
, con
, aname
):
292 txt
= "mkConnection (slow_fabric.v_to_slaves\n" + \
293 " [fromInteger(valueOf({1}))],\n" + \
296 print "PBase __mk_connection", self
.name
, aname
299 return txt
.format(con
, aname
)
301 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
304 print "PBase mk_conn", self
.name
, count
305 aname
= self
.axi_slave_name(name
, count
, typ
)
306 #dname = self.mksuffix(name, count)
307 #dname = "{0}{1}".format(name, dname)
308 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
309 return self
.__mk
_connection
(con
, aname
, fabricname
)
311 def _mk_connection(self
, name
=None, count
=0):
314 def pinname_out(self
, pname
):
317 def pinname_in(self
, pname
):
320 def pinname_outen(self
, pname
):
323 def ifname_tweak(self
, pname
, typ
, txt
):
326 def pinname_tweak(self
, pname
, typ
, txt
):
332 def mk_plic(self
, inum
, irq_offs
):
334 print "mk_plic", self
.name
, inum
, irq_offs
335 niq
= self
.num_irqs()
337 return ('', irq_offs
)
338 name
= self
.get_iname(inum
)
339 res
.append("// PLIC rules for {0}".format(name
))
340 for idx
in range(niq
):
341 plic_obj
= self
.plic_object(name
, idx
)
342 print "plic_obj", name
, idx
, plic_obj
343 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
345 irq_offs
+= 1 # increment to next irq
346 return ('\n'.join(res
), irq_offs
)
348 def mk_ext_ifacedef(self
, iname
, inum
):
351 def extfastifinstance(self
, name
, count
):
354 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
358 pname
= self
.get_iname(count
)
362 sname
= self
.peripheral
.iname().format(count
)
363 template
= "interface {0}{3} = {2}{1}{4};"
364 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
366 def extifinstance2(self
, name
, count
):
369 def extifinstance(self
, name
, count
):
370 return self
._extifinstance
(name
, count
, "",
371 "pinmux.peripheral_side.")
375 rule rl_connect_{0}_to_plic_{2};
376 if({1} == 1'b1) begin
377 ff_gateway_queue[{2}].enq(1);
378 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
383 axi_master_declarations
= """\
384 typedef 0 Dmem_master_num;
385 typedef 1 Imem_master_num;
387 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
389 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
391 typedef TAdd#(DMA_master_num,1)
395 axi_fastslave_declarations
= """\
397 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
398 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
400 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
402 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
404 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
406 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
408 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
409 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
411 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
414 axi_slave_declarations
= """\
415 typedef 0 SlowMaster;
417 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
419 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
421 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
423 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
426 pinmux_cellrule
= """\
427 rule connect_select_lines_pinmux;
433 class CallFn(object):
434 def __init__(self
, peripheral
, name
):
435 self
.peripheral
= peripheral
438 def __call__(self
, *args
):
439 #print "__call__", self.name, self.peripheral.slow, args
440 if not self
.peripheral
.slow
:
442 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
445 class PeripheralIface(object):
446 def __init__(self
, ifacename
):
448 slow
= slowfactory
.getcls(ifacename
)
449 print "Iface", ifacename
, slow
451 self
.slow
= slow(ifacename
)
452 self
.slow
.peripheral
= self
453 for fname
in ['slowimport',
455 'extifinstance2', 'extifinstance', 'extifdecl',
456 'slowifdecl', 'slowifdeclmux',
459 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
461 'mk_plic', 'mk_ext_ifacedef',
462 '_mk_clk_con', 'mk_ext_ifacedef',
463 'mk_connection', 'mk_cellconn', '_mk_pincon']:
464 fn
= CallFn(self
, fname
)
465 setattr(self
, fname
, types
.MethodType(fn
, self
))
467 #print "PeripheralIface"
470 def mksuffix(self
, name
, i
):
471 if self
.slow
is None:
473 return self
.slow
.mksuffix(name
, i
)
475 def axi_reg_def(self
, start
, count
):
478 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
480 def axi_master_idx(self
, start
, count
, typ
):
481 if not self
.slow
or not self
.slow
.has_axi_master():
483 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
485 def axi_slave_idx(self
, start
, count
, typ
):
488 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
490 def axi_fastaddr_map(self
, count
):
493 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
495 def axi_addr_map(self
, count
):
498 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
501 class PeripheralInterfaces(object):
503 self
.fastbusmode
= False
505 def slowimport(self
, *args
):
507 for (name
, count
) in self
.ifacecount
:
508 #print "slowimport", name, self.data[name].slowimport
509 ret
.append(self
.data
[name
].slowimport())
510 return '\n'.join(li(list(filter(None, ret
)), 4))
512 def extfastifinstance(self
, *args
):
514 for (name
, count
) in self
.ifacecount
:
515 for i
in range(count
):
516 iname
= self
.data
[name
].iname().format(i
)
517 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
518 if self
.is_on_fastbus(name
, i
):
520 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
521 return '\n'.join(li(list(filter(None, ret
)), 8))
523 def extifinstance2(self
, *args
):
525 for (name
, count
) in self
.ifacecount
:
526 for i
in range(count
):
527 iname
= self
.data
[name
].iname().format(i
)
528 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
529 return '\n'.join(li(list(filter(None, ret
)), 8))
531 def extifinstance(self
, *args
):
533 for (name
, count
) in self
.ifacecount
:
534 for i
in range(count
):
535 iname
= self
.data
[name
].iname().format(i
)
536 if not self
.is_on_fastbus(name
, i
):
538 ret
.append(self
.data
[name
].extifinstance(name
, i
))
539 return '\n'.join(li(list(filter(None, ret
)), 8))
541 def extifdecl(self
, *args
):
543 for (name
, count
) in self
.ifacecount
:
544 for i
in range(count
):
545 if not self
.is_on_fastbus(name
, i
):
547 ret
.append(self
.data
[name
].extifdecl(name
, i
))
548 return '\n'.join(li(list(filter(None, ret
)), 8))
550 def slowifdeclmux(self
, *args
):
552 for (name
, count
) in self
.ifacecount
:
553 for i
in range(count
):
554 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
555 return '\n'.join(li(list(filter(None, ret
)), 8))
557 def fastifdecl(self
, *args
):
559 for (name
, count
) in self
.ifacecount
:
560 for i
in range(count
):
561 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
562 if self
.is_on_fastbus(name
, i
):
564 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
565 return '\n'.join(li(list(filter(None, ret
)), 4))
567 def slowifdecl(self
, *args
):
569 for (name
, count
) in self
.ifacecount
:
570 for i
in range(count
):
571 if self
.is_on_fastbus(name
, i
):
573 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
574 return '\n'.join(list(filter(None, ret
)))
576 def axi_fastmem_def(self
, *args
):
577 return self
._axi
_reg
_def
(0x50000000, *args
)
579 def axi_reg_def(self
, *args
):
580 return self
._axi
_reg
_def
(0x00011100, *args
)
582 def _axi_reg_def(self
, start
, *args
):
584 for (name
, count
) in self
.ifacecount
:
585 for i
in range(count
):
586 if self
.is_on_fastbus(name
, i
):
588 x
= self
.data
[name
].axi_reg_def(start
, i
)
589 #print ("ifc", name, x)
593 return '\n'.join(list(filter(None, ret
)))
595 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
597 for (name
, count
) in self
.ifacecount
:
598 for i
in range(count
):
599 if self
.is_on_fastbus(name
, i
):
602 fn
= self
.data
[name
].axi_master_idx
604 fn
= self
.data
[name
].axi_slave_idx
605 (rdef
, offs
) = fn(start
, i
, idxtype
)
606 #print ("ifc", name, rdef, offs)
609 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
610 decls
= '\n'.join(list(filter(None, ret
)))
611 return template
.format(decls
)
613 def axi_slave_idx(self
, *args
):
614 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
617 def axi_fastslave_idx(self
, *args
):
618 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
621 def axi_master_idx(self
, *args
):
622 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
625 def axi_fastslave_idx(self
, *args
):
626 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
629 def axi_fastaddr_map(self
, *args
):
631 for (name
, count
) in self
.ifacecount
:
632 for i
in range(count
):
633 if self
.is_on_fastbus(name
, i
):
635 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
636 return '\n'.join(li(list(filter(None, ret
)), 8))
638 def axi_addr_map(self
, *args
):
640 for (name
, count
) in self
.ifacecount
:
641 for i
in range(count
):
642 if self
.is_on_fastbus(name
, i
):
644 ret
.append(self
.data
[name
].axi_addr_map(i
))
645 return '\n'.join(li(list(filter(None, ret
)), 8))
647 def mkfast_peripheral(self
, *args
):
649 for (name
, count
) in self
.ifacecount
:
650 for i
in range(count
):
651 if self
.is_on_fastbus(name
, i
):
653 #print "mkfast", name, count
654 x
= self
.data
[name
].mkfast_peripheral()
656 suffix
= self
.data
[name
].mksuffix(name
, i
)
657 ret
.append(x
.format(suffix
))
658 return '\n'.join(li(list(filter(None, ret
)), 8))
660 def mkslow_peripheral(self
, *args
):
662 for (name
, count
) in self
.ifacecount
:
663 for i
in range(count
):
664 if self
.is_on_fastbus(name
, i
):
666 #print "mkslow", name, count
667 x
= self
.data
[name
].mkslow_peripheral()
669 suffix
= self
.data
[name
].mksuffix(name
, i
)
670 ret
.append(x
.format(suffix
))
671 return '\n'.join(li(list(filter(None, ret
)), 8))
673 def mk_fast_connection(self
, *args
):
675 for (name
, count
) in self
.ifacecount
:
676 for i
in range(count
):
677 if self
.is_on_fastbus(name
, i
):
679 txt
= self
.data
[name
].mk_connection(i
, "fabric", "fast")
682 print self
.data
[name
].mk_connection
684 return '\n'.join(li(list(filter(None, ret
)), 12))
686 def mk_connection(self
, *args
):
688 for (name
, count
) in self
.ifacecount
:
689 for i
in range(count
):
690 if self
.is_on_fastbus(name
, i
):
692 txt
= self
.data
[name
].mk_connection(i
, "slow_fabric", "")
695 print self
.data
[name
].mk_connection
697 return '\n'.join(li(list(filter(None, ret
)), 8))
699 def mk_cellconn(self
):
702 for (name
, count
) in self
.ifacecount
:
703 for i
in range(count
):
704 if self
.is_on_fastbus(name
, i
):
706 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
709 (txt
, cellcount
) = res
711 ret
= li('\n'.join(list(filter(None, ret
))), 4)
712 return li(pinmux_cellrule
.format(ret
), 4)
715 return self
._mk
_pincon
("slow")
717 def mk_fast_pincon(self
):
718 return self
._mk
_pincon
("fast")
720 def _mk_pincon(self
, typ
):
722 for (name
, count
) in self
.ifacecount
:
723 for i
in range(count
):
724 if self
.is_on_fastbus(name
, i
):
726 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
728 return '\n'.join(li(list(filter(None, ret
)), 4))
730 def mk_dma_irq(self
):
738 for (name
, count
) in self
.ifacecount
:
740 for i
in range(count
):
741 if not self
.is_on_fastbus(name
, i
):
743 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
747 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
748 ifacerules
.append(txt
)
749 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
751 ifacerules
= list(filter(None, ifacerules
))
753 txt
= "rule synchronize_%s_interrupts;" % name
756 rules
.append("endrule")
758 cnct
= list(filter(None, cnct
))
760 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
761 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
764 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
766 cnct
.append(" dma.interrupt_from_peripherals(\n" +
767 " lv_interrupt_to_DMA);")
768 cnct
.append("endrule;")
770 ret
= list(filter(None, sync
+ rules
+ cnct
))
772 return '\n'.join(ret
)
774 def num_dmachannels(self
):
775 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
777 def mk_ext_ifacedef(self
):
779 for (name
, count
) in self
.ifacecount
:
780 for i
in range(count
):
781 if self
.is_on_fastbus(name
, i
):
783 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
785 return '\n'.join(li(list(filter(None, ret
)), 8))
789 irq_offs
= 8 # XXX: DMA scovers 0-7?
790 for (name
, count
) in self
.ifacecount
:
791 for i
in range(count
):
792 if self
.is_on_fastbus(name
, i
):
794 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
797 (txt
, irq_offs
) = res
799 self
.num_slow_irqs
= irq_offs
800 return '\n'.join(li(list(filter(None, ret
)), 4))
802 def mk_sloirqsdef(self
):
803 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
805 def mk_fastclk_con(self
):
806 return self
._mk
_clk
_con
("fast")
808 def mk_slowclk_con(self
):
809 return self
._mk
_clk
_con
("slow")
811 def _mk_clk_con(self
, ctype
):
813 for (name
, count
) in self
.ifacecount
:
814 for i
in range(count
):
815 if self
.is_on_fastbus(name
, i
):
817 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
819 return '\n'.join(li(list(filter(None, ret
)), 8))
821 def is_on_fastbus(self
, name
, i
):
822 #print "fastbus mode", self.fastbusmode, name, i
823 iname
= self
.data
[name
].iname().format(i
)
825 return iname
not in self
.fastbus
826 return iname
in self
.fastbus
829 class PFactory(object):
830 def getcls(self
, name
):
831 from uart
import uart
832 from quart
import quart
833 from sdmmc
import sdmmc
835 from eint
import eint
836 from rs232
import rs232
838 from eint
import eint
839 from jtag
import jtag
840 from spi
import spi
, mspi
841 from qspi
import qspi
, mqspi
842 from gpio
import gpio
843 from rgbttl
import rgbttl
844 from flexbus
import flexbus
846 for k
, v
in {'uart': uart
,
862 if name
.startswith(k
):
867 slowfactory
= PFactory()
869 if __name__
== '__main__':
873 i
= PeripheralIface('uart')
875 i
= PeripheralIface('gpioa')