7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
):
90 return "%(name)s%(ifacenum)dBase" % locals()
92 def axiend(self
, name
, ifacenum
):
94 return "%(name)s%(ifacenum)dEnd" % locals()
96 def axi_reg_def(self
, start
, name
, ifacenum
):
98 offs
= self
.num_axi_regs32() * 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
)
103 bend
= self
.axiend(name
, ifacenum
)
104 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_master_name(self
, name
, ifacenum
, typ
=''):
111 return "{0}{1}_master_num".format(name
, ifacenum
)
113 def axi_slave_name(self
, name
, ifacenum
, typ
=''):
115 return "{0}{1}_{2}slave_num".format(name
, ifacenum
, typ
)
117 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
118 name
= self
.axi_master_name(name
, ifacenum
, typ
)
119 return ("typedef {0} {1};".format(idx
, name
), 1)
121 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
122 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
123 return ("typedef {0} {1};".format(idx
, name
), 1)
125 def axi_fastaddr_map(self
, name
, ifacenum
):
126 return self
.axi_addr_map(name
, ifacenum
, 'fast')
128 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
129 bname
= self
.axibase(name
, ifacenum
)
130 bend
= self
.axiend(name
, ifacenum
)
131 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
133 if(addr>=`{0} && addr<=`{1})
134 return tuple2(True,fromInteger(valueOf({2})));
136 return template
.format(bname
, bend
, name
)
138 def _mk_pincon(self
, name
, count
, ptyp
):
139 # TODO: really should be using bsv.interface_decl.Interfaces
140 # pin-naming rules.... logic here is hard-coded to duplicate
141 # it (see Interface.__init__ outen)
143 for p
in self
.peripheral
.pinspecs
:
146 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
147 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
148 ret
.append("//%s %s" % (n
, str(p
)))
150 sname
= self
.get_iname(count
)
151 sname
= "{0}.{1}".format(sname
, pname
)
152 ps
= "slow_peripherals.%s" % sname
154 sname
= self
.peripheral
.iname().format(count
)
155 sname
= "{0}.{1}".format(sname
, pname
)
156 ps
= "pinmux.peripheral_side.%s" % sname
157 if typ
== 'out' or typ
== 'inout':
158 fname
= self
.pinname_out(pname
)
159 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
160 n_
= "{0}{1}".format(n
, count
)
168 cn
= self
._mk
_actual
_connection
('out', name
,
170 pname
, ps_
, n_
, fname
)
174 fname
= self
.pinname_outen(pname
)
176 if isinstance(fname
, str):
177 fname
= "{0}.{1}".format(n_
, fname
)
178 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
179 cn
= self
._mk
_actual
_connection
('outen', name
,
183 if typ
== 'in' or typ
== 'inout':
184 fname
= self
.pinname_in(pname
)
190 n_
= "{0}{1}".format(n
, count
)
191 n_
= '{0}.{1}'.format(n_
, fname
)
192 n_
= self
.ifname_tweak(pname
, 'in', n_
)
193 cn
= self
._mk
_actual
_connection
('in', name
,
195 pname
, ps_
, n_
, fname
)
197 return '\n'.join(ret
)
199 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
204 sname
= self
.get_iname(count
)
205 ps
= "slow_peripherals.%s" % sname
207 sname
= self
.peripheral
.iname().format(count
)
208 ps
= "pinmux.peripheral_side.%s" % sname
209 n
= self
.get_iname(count
)
211 n
= "{0}.{1}".format(n
, stype
)
212 ps_
= "{0}.{1}".format(ps
, pname
)
213 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
214 pname
, ps_
, n
, stype
)
215 return '\n'.join(ret
)
217 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
218 pname
, ps
, n
, fname
):
220 ck
= self
.get_clock_reset(name
, count
)
222 if ck
== PBase
.get_clock_reset(self
, name
, count
):
223 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
224 .format(ps
, n
, fname
))
226 n2
= "{0}{1}".format(name
, count
)
227 sync
= '{0}_{1}_sync'.format(n2
, pname
)
228 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
230 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
231 .format(sync
, n
, fname
))
232 elif ctype
== 'outen':
233 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
236 if ck
== PBase
.get_clock_reset(self
, name
, count
):
237 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
240 n2
= "{0}{1}".format(name
, count
)
241 sync
= '{0}_{1}_sync'.format(n2
, pname
)
242 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
244 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
249 def _mk_clk_con(self
, name
, count
, ctype
):
251 ck
= self
.get_clock_reset(name
, count
)
252 if ck
== PBase
.get_clock_reset(self
, name
, count
):
255 spc
= "sp_clock, sp_reset"
258 ck
= "core_clock, core_reset"
260 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
262 for p
in self
.peripheral
.pinspecs
:
266 if typ
== 'out' or typ
== 'inout':
267 fname
= self
.pinname_out(pname
)
270 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
271 n_
= "{0}{1}".format(n
, count
)
274 n_
= '{0}_{1}'.format(n_
, pname
)
275 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
276 if typ
== 'in' or typ
== 'inout':
277 fname
= self
.pinname_in(pname
)
280 #fname = self.pinname_in(pname)
281 n_
= "{0}{1}".format(n
, count
)
282 n_
= '{0}_{1}'.format(n_
, pname
)
283 #n_ = self.ifname_tweak(pname, 'in', n_)
284 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
285 return '\n'.join(ret
)
287 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
288 ck
= self
.get_clock_reset(name
, count
)
289 if ck
== PBase
.get_clock_reset(self
, name
, count
):
292 spc
= "sp_clock, sp_reset"
295 ck
= "core_clock, core_reset"
297 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
300 n_
= "{0}{1}".format(name
, count
)
301 n_
= '{0}_{1}'.format(n_
, pname
)
302 return template
.format(bitspec
, n_
, ck
, spc
)
305 def mk_cellconn(self
, *args
):
308 def mkfast_peripheral(self
, size
=0):
311 def mkslow_peripheral(self
, size
=0):
314 def mksuffix(self
, name
, i
):
317 def __mk_connection(self
, con
, aname
, fabricname
):
318 txt
= "mkConnection ({2}.v_to_slaves\n" + \
319 " [fromInteger(valueOf({1}))],\n" + \
322 print "PBase __mk_connection", self
.name
, aname
325 return txt
.format(con
, aname
, fabricname
)
327 def __mk_master_connection(self
, con
, aname
):
328 txt
= "mkConnection (slow_fabric.v_to_slaves\n" + \
329 " [fromInteger(valueOf({1}))],\n" + \
332 print "PBase __mk_connection", self
.name
, aname
335 return txt
.format(con
, aname
)
337 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
340 print "PBase mk_conn", self
.name
, count
341 aname
= self
.axi_slave_name(name
, count
, typ
)
342 #dname = self.mksuffix(name, count)
343 #dname = "{0}{1}".format(name, dname)
344 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
345 return self
.__mk
_connection
(con
, aname
, fabricname
)
347 def _mk_connection(self
, name
=None, count
=0):
350 def pinname_out(self
, pname
):
353 def pinname_in(self
, pname
):
356 def pinname_outen(self
, pname
):
359 def ifname_tweak(self
, pname
, typ
, txt
):
362 def pinname_tweak(self
, pname
, typ
, txt
):
368 def mk_plic(self
, inum
, irq_offs
):
370 print "mk_plic", self
.name
, inum
, irq_offs
371 niq
= self
.num_irqs()
373 return ('', irq_offs
)
374 name
= self
.get_iname(inum
)
375 res
.append("// PLIC rules for {0}".format(name
))
376 for idx
in range(niq
):
377 plic_obj
= self
.plic_object(name
, idx
)
378 print "plic_obj", name
, idx
, plic_obj
379 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
381 irq_offs
+= 1 # increment to next irq
382 return ('\n'.join(res
), irq_offs
)
384 def mk_ext_ifacedef(self
, iname
, inum
):
387 def extfastifinstance(self
, name
, count
):
390 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
394 pname
= self
.get_iname(count
)
398 sname
= self
.peripheral
.iname().format(count
)
399 template
= "interface {0}{3} = {2}{1}{4};"
400 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
402 def extifinstance2(self
, name
, count
):
405 def extifinstance(self
, name
, count
):
406 return self
._extifinstance
(name
, count
, "",
407 "pinmux.peripheral_side.")
411 rule rl_connect_{0}_to_plic_{2};
412 if({1} == 1'b1) begin
413 ff_gateway_queue[{2}].enq(1);
414 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
419 axi_master_declarations
= """\
420 typedef 0 Dmem_master_num;
421 typedef 1 Imem_master_num;
423 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
425 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
427 typedef TAdd#(DMA_master_num,1)
431 axi_fastslave_declarations
= """\
433 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
434 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
436 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
438 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
440 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
442 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
444 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
445 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
447 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
450 axi_slave_declarations
= """\
451 typedef 0 SlowMaster;
453 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
455 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
457 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
459 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
462 pinmux_cellrule
= """\
463 rule connect_select_lines_pinmux;
469 class CallFn(object):
470 def __init__(self
, peripheral
, name
):
471 self
.peripheral
= peripheral
474 def __call__(self
, *args
):
475 #print "__call__", self.name, self.peripheral.slow, args
476 if not self
.peripheral
.slow
:
478 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
481 class PeripheralIface(object):
482 def __init__(self
, ifacename
):
484 slow
= slowfactory
.getcls(ifacename
)
485 print "Iface", ifacename
, slow
487 self
.slow
= slow(ifacename
)
488 self
.slow
.peripheral
= self
489 for fname
in ['slowimport',
491 'extifinstance2', 'extifinstance', 'extifdecl',
492 'slowifdecl', 'slowifdeclmux',
495 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
497 'mk_plic', 'mk_ext_ifacedef',
498 '_mk_clk_con', 'mk_ext_ifacedef',
499 'mk_connection', 'mk_cellconn', '_mk_pincon']:
500 fn
= CallFn(self
, fname
)
501 setattr(self
, fname
, types
.MethodType(fn
, self
))
503 #print "PeripheralIface"
506 def mksuffix(self
, name
, i
):
507 if self
.slow
is None:
509 return self
.slow
.mksuffix(name
, i
)
511 def axi_reg_def(self
, start
, count
):
514 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
516 def axi_master_idx(self
, start
, count
, typ
):
517 if not self
.slow
or not self
.slow
.has_axi_master():
519 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
521 def axi_slave_idx(self
, start
, count
, typ
):
524 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
526 def axi_fastaddr_map(self
, count
):
529 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
531 def axi_addr_map(self
, count
):
534 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
537 class PeripheralInterfaces(object):
539 self
.fastbusmode
= False
541 def slowimport(self
, *args
):
543 for (name
, count
) in self
.ifacecount
:
544 #print "slowimport", name, self.data[name].slowimport
545 ret
.append(self
.data
[name
].slowimport())
546 return '\n'.join(li(list(filter(None, ret
)), 4))
548 def extfastifinstance(self
, *args
):
550 for (name
, count
) in self
.ifacecount
:
551 for i
in range(count
):
552 iname
= self
.data
[name
].iname().format(i
)
553 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
554 if self
.is_on_fastbus(name
, i
):
556 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
557 return '\n'.join(li(list(filter(None, ret
)), 8))
559 def extifinstance2(self
, *args
):
561 for (name
, count
) in self
.ifacecount
:
562 for i
in range(count
):
563 iname
= self
.data
[name
].iname().format(i
)
564 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
565 return '\n'.join(li(list(filter(None, ret
)), 8))
567 def extifinstance(self
, *args
):
569 for (name
, count
) in self
.ifacecount
:
570 for i
in range(count
):
571 iname
= self
.data
[name
].iname().format(i
)
572 if not self
.is_on_fastbus(name
, i
):
574 ret
.append(self
.data
[name
].extifinstance(name
, i
))
575 return '\n'.join(li(list(filter(None, ret
)), 8))
577 def extifdecl(self
, *args
):
579 for (name
, count
) in self
.ifacecount
:
580 for i
in range(count
):
581 if not self
.is_on_fastbus(name
, i
):
583 ret
.append(self
.data
[name
].extifdecl(name
, i
))
584 return '\n'.join(li(list(filter(None, ret
)), 8))
586 def slowifdeclmux(self
, *args
):
588 for (name
, count
) in self
.ifacecount
:
589 for i
in range(count
):
590 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
591 return '\n'.join(li(list(filter(None, ret
)), 8))
593 def fastifdecl(self
, *args
):
595 for (name
, count
) in self
.ifacecount
:
596 for i
in range(count
):
597 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
598 if self
.is_on_fastbus(name
, i
):
600 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
601 return '\n'.join(li(list(filter(None, ret
)), 4))
603 def slowifdecl(self
, *args
):
605 for (name
, count
) in self
.ifacecount
:
606 for i
in range(count
):
607 if self
.is_on_fastbus(name
, i
):
609 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
610 return '\n'.join(list(filter(None, ret
)))
612 def axi_fastmem_def(self
, *args
):
613 return self
._axi
_reg
_def
(0x50000000, *args
)
615 def axi_reg_def(self
, *args
):
616 return self
._axi
_reg
_def
(0x00011100, *args
)
618 def _axi_reg_def(self
, start
, *args
):
620 for (name
, count
) in self
.ifacecount
:
621 for i
in range(count
):
622 if self
.is_on_fastbus(name
, i
):
624 x
= self
.data
[name
].axi_reg_def(start
, i
)
625 #print ("ifc", name, x)
629 return '\n'.join(list(filter(None, ret
)))
631 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
633 for (name
, count
) in self
.ifacecount
:
634 for i
in range(count
):
635 if self
.is_on_fastbus(name
, i
):
638 fn
= self
.data
[name
].axi_master_idx
640 fn
= self
.data
[name
].axi_slave_idx
641 (rdef
, offs
) = fn(start
, i
, idxtype
)
642 #print ("ifc", name, rdef, offs)
645 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
646 decls
= '\n'.join(list(filter(None, ret
)))
647 return template
.format(decls
)
649 def axi_slave_idx(self
, *args
):
650 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
653 def axi_fastslave_idx(self
, *args
):
654 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
657 def axi_master_idx(self
, *args
):
658 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
661 def axi_fastslave_idx(self
, *args
):
662 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
665 def axi_fastaddr_map(self
, *args
):
667 for (name
, count
) in self
.ifacecount
:
668 for i
in range(count
):
669 if self
.is_on_fastbus(name
, i
):
671 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
672 return '\n'.join(li(list(filter(None, ret
)), 8))
674 def axi_addr_map(self
, *args
):
676 for (name
, count
) in self
.ifacecount
:
677 for i
in range(count
):
678 if self
.is_on_fastbus(name
, i
):
680 ret
.append(self
.data
[name
].axi_addr_map(i
))
681 return '\n'.join(li(list(filter(None, ret
)), 8))
683 def mkfast_peripheral(self
, *args
):
685 for (name
, count
) in self
.ifacecount
:
686 for i
in range(count
):
687 if self
.is_on_fastbus(name
, i
):
689 #print "mkfast", name, count
690 x
= self
.data
[name
].mkfast_peripheral()
692 suffix
= self
.data
[name
].mksuffix(name
, i
)
693 ret
.append(x
.format(suffix
))
694 return '\n'.join(li(list(filter(None, ret
)), 8))
696 def mkslow_peripheral(self
, *args
):
698 for (name
, count
) in self
.ifacecount
:
699 for i
in range(count
):
700 if self
.is_on_fastbus(name
, i
):
702 #print "mkslow", name, count
703 x
= self
.data
[name
].mkslow_peripheral()
705 suffix
= self
.data
[name
].mksuffix(name
, i
)
706 ret
.append(x
.format(suffix
))
707 return '\n'.join(li(list(filter(None, ret
)), 8))
709 def mk_fast_connection(self
, *args
):
711 for (name
, count
) in self
.ifacecount
:
712 for i
in range(count
):
713 if self
.is_on_fastbus(name
, i
):
715 txt
= self
.data
[name
].mk_connection(i
, "fabric", "fast")
718 print self
.data
[name
].mk_connection
720 return '\n'.join(li(list(filter(None, ret
)), 12))
722 def mk_connection(self
, *args
):
724 for (name
, count
) in self
.ifacecount
:
725 for i
in range(count
):
726 if self
.is_on_fastbus(name
, i
):
728 txt
= self
.data
[name
].mk_connection(i
, "slow_fabric", "")
731 print self
.data
[name
].mk_connection
733 return '\n'.join(li(list(filter(None, ret
)), 8))
735 def mk_cellconn(self
):
738 for (name
, count
) in self
.ifacecount
:
739 for i
in range(count
):
740 if self
.is_on_fastbus(name
, i
):
742 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
745 (txt
, cellcount
) = res
747 ret
= li('\n'.join(list(filter(None, ret
))), 4)
748 return li(pinmux_cellrule
.format(ret
), 4)
751 return self
._mk
_pincon
("slow")
753 def mk_fast_pincon(self
):
754 return self
._mk
_pincon
("fast")
756 def _mk_pincon(self
, typ
):
758 for (name
, count
) in self
.ifacecount
:
759 for i
in range(count
):
760 if self
.is_on_fastbus(name
, i
):
762 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
764 return '\n'.join(li(list(filter(None, ret
)), 4))
766 def mk_dma_irq(self
):
774 for (name
, count
) in self
.ifacecount
:
776 for i
in range(count
):
777 if not self
.is_on_fastbus(name
, i
):
779 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
783 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
784 ifacerules
.append(txt
)
785 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
787 ifacerules
= list(filter(None, ifacerules
))
789 txt
= "rule synchronize_%s_interrupts;" % name
792 rules
.append("endrule")
794 cnct
= list(filter(None, cnct
))
796 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
797 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
800 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
802 cnct
.append(" dma.interrupt_from_peripherals(\n" +
803 " lv_interrupt_to_DMA);")
804 cnct
.append("endrule;")
806 ret
= list(filter(None, sync
+ rules
+ cnct
))
808 return '\n'.join(ret
)
810 def num_dmachannels(self
):
811 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
813 def mk_ext_ifacedef(self
):
815 for (name
, count
) in self
.ifacecount
:
816 for i
in range(count
):
817 if self
.is_on_fastbus(name
, i
):
819 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
821 return '\n'.join(li(list(filter(None, ret
)), 8))
825 irq_offs
= 8 # XXX: DMA scovers 0-7?
826 for (name
, count
) in self
.ifacecount
:
827 for i
in range(count
):
828 if self
.is_on_fastbus(name
, i
):
830 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
833 (txt
, irq_offs
) = res
835 self
.num_slow_irqs
= irq_offs
836 return '\n'.join(li(list(filter(None, ret
)), 4))
838 def mk_sloirqsdef(self
):
839 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
841 def mk_fastclk_con(self
):
842 return self
._mk
_clk
_con
("fast")
844 def mk_slowclk_con(self
):
845 return self
._mk
_clk
_con
("slow")
847 def _mk_clk_con(self
, ctype
):
849 for (name
, count
) in self
.ifacecount
:
850 for i
in range(count
):
851 if self
.is_on_fastbus(name
, i
):
853 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
855 return '\n'.join(li(list(filter(None, ret
)), 8))
857 def is_on_fastbus(self
, name
, i
):
858 #print "fastbus mode", self.fastbusmode, name, i
859 iname
= self
.data
[name
].iname().format(i
)
861 return iname
not in self
.fastbus
862 return iname
in self
.fastbus
865 class PFactory(object):
866 def getcls(self
, name
):
867 from uart
import uart
868 from quart
import quart
869 from sdmmc
import sdmmc
871 from eint
import eint
872 from rs232
import rs232
874 from eint
import eint
875 from jtag
import jtag
876 from spi
import spi
, mspi
877 from qspi
import qspi
, mqspi
878 from gpio
import gpio
879 from rgbttl
import rgbttl
880 from flexbus
import flexbus
882 for k
, v
in {'uart': uart
,
898 if name
.startswith(k
):
903 slowfactory
= PFactory()
905 if __name__
== '__main__':
909 i
= PeripheralIface('uart')
911 i
= PeripheralIface('gpioa')