1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
26 from parse
import Parse
27 from bsv
.actual_pinmux
import init
28 from bsv
.bus_transactors
import axi4_lite
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time
.strftime("%c") + '''
39 header
= copyright
+ '''
49 def pinmuxgen(pth
=None, verify
=True):
50 """ populating the file with the code
53 p
= Parse(pth
, verify
)
54 iocells
= Interfaces()
55 iocells
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
56 ifaces
= Interfaces(pth
)
57 #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
62 bp
= os
.path
.join(pth
, bp
)
63 if not os
.path
.exists(bp
):
65 bl
= os
.path
.join(bp
, 'bsv_lib')
66 if not os
.path
.exists(bl
):
69 cwd
= os
.path
.split(__file__
)[0]
71 # copy over template and library files
72 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
73 os
.path
.join(bp
, 'Makefile'))
74 cwd
= os
.path
.join(cwd
, 'bsv_lib')
75 for fname
in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
76 'gpio.bsv', 'mux.bsv']:
77 shutil
.copyfile(os
.path
.join(cwd
, fname
),
78 os
.path
.join(bl
, fname
))
80 bus
= os
.path
.join(bp
, 'busenable.bsv')
81 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
82 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
83 bvp
= os
.path
.join(bp
, 'bus.bsv')
84 idef
= os
.path
.join(bp
, 'instance_defines.bsv')
85 slow
= os
.path
.join(bp
, 'slow_peripherals.bsv')
86 slowt
= os
.path
.join(cwd
, 'slow_peripherals_template.bsv')
88 write_pmp(pmp
, p
, ifaces
, iocells
)
89 write_ptp(ptp
, p
, ifaces
)
90 write_bvp(bvp
, p
, ifaces
)
91 write_bus(bus
, p
, ifaces
)
92 write_instances(idef
, p
, ifaces
)
93 write_slow(slow
, slowt
, p
, ifaces
, iocells
)
96 def write_slow(slow
, template
, p
, ifaces
, iocells
):
97 """ write out the slow_peripherals.bsv file.
98 joins all the peripherals together into one AXI Lite interface
100 with
open(template
) as bsv_file
:
101 template
= bsv_file
.read()
102 imports
= ifaces
.slowimport()
103 ifdecl
= ifaces
.slowifdecl()
104 regdef
= ifaces
.axi_reg_def()
105 slavedecl
= ifaces
.axi_slave_idx()
106 fnaddrmap
= ifaces
.axi_addr_map()
107 mkslow
= ifaces
.mkslow_peripheral()
108 mkcon
= ifaces
.mk_connection()
109 mkcellcon
= iocells
.mk_cellconn()
110 with
open(slow
, "w") as bsv_file
:
111 bsv_file
.write(template
.format(imports
, ifdecl
, regdef
, slavedecl
,
112 fnaddrmap
, mkslow
, mkcon
, mkcellcon
))
115 def write_bus(bus
, p
, ifaces
):
116 # package and interface declaration followed by
117 # the generic io_cell definition
118 with
open(bus
, "w") as bsv_file
:
119 ifaces
.busfmt(bsv_file
)
122 def write_pmp(pmp
, p
, ifaces
, iocells
):
123 # package and interface declaration followed by
124 # the generic io_cell definition
125 with
open(pmp
, "w") as bsv_file
:
126 bsv_file
.write(header
)
128 cell_bit_width
= 'Bit#(%d)' % p
.cell_bitwidth
130 interface MuxSelectionLines;
132 // declare the method which will capture the user pin-mux
133 // selection values.The width of the input is dependent on the number
134 // of muxes happening per IO. For now we have a generalized width
135 // where each IO will have the same number of muxes.''')
137 for cell
in p
.muxed_cells
:
138 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cell_bit_width
))
140 bsv_file
.write("\n endinterface\n")
144 interface IOCellSide;
145 // declare the interface to the IO cells.
146 // Each IO cell will have 1 input field (output from pin mux)
147 // and an output and out-enable field (input to pinmux)''')
149 # == create method definitions for all iocell interfaces ==#
150 iocells
.ifacefmt(bsv_file
)
152 # ===== finish interface definition and start module definition=======
153 bsv_file
.write("\n endinterface\n")
155 # ===== io cell definition =======
158 interface PeripheralSide;
159 // declare the interface to the peripherals
160 // Each peripheral's function will be either an input, output
161 // or be bi-directional. an input field will be an output from the
162 // peripheral and an output field will be an input to the peripheral.
163 // Bi-directional functions also have an output-enable (which
164 // again comes *in* from the peripheral)''')
165 # ==============================================================
167 # == create method definitions for all peripheral interfaces ==#
168 ifaces
.ifacefmt(bsv_file
)
169 bsv_file
.write("\n endinterface\n")
171 # ===== finish interface definition and start module definition=======
174 interface Ifc_pinmux;
175 // this interface controls how each IO cell is routed. setting
176 // any given IO cell's mux control value will result in redirection
177 // of not just the input or output to different peripheral functions
178 // but also the *direction* control - if appropriate - as well.
179 interface MuxSelectionLines mux_lines;
181 // this interface contains the inputs, outputs and direction-control
182 // lines for all peripherals. GPIO is considered to also be just
183 // a peripheral because it also has in, out and direction-control.
184 interface PeripheralSide peripheral_side;
186 // this interface is to be linked to the individual IO cells.
187 // if looking at a "non-muxed" GPIO design, basically the
188 // IO cell input, output and direction-control wires are cut
189 // (giving six pairs of dangling wires, named left and right)
190 // these iocells are routed in their place on one side ("left")
191 // and the matching *GPIO* peripheral interfaces in/out/dir
192 // connect to the OTHER side ("right"). the result is that
193 // the muxer settings end up controlling the routing of where
194 // the I/O from the IOcell actually goes.
195 interface IOCellSide iocell_side;
198 module mkpinmux(Ifc_pinmux);
200 # ====================================================================
202 # ======================= create wire and registers =================#
204 // the followins wires capture the pin-mux selection
205 // values for each mux assigned to a CELL
207 for cell
in p
.muxed_cells
:
208 bsv_file
.write(mux_interface
.wirefmt(
209 cell
[0], cell_bit_width
))
211 iocells
.wirefmt(bsv_file
)
212 ifaces
.wirefmt(bsv_file
)
215 # ====================================================================
216 # ========================= Actual pinmuxing ========================#
218 /*====== This where the muxing starts for each io-cell======*/
219 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
221 bsv_file
.write(p
.pinmux
)
223 /*============================================================*/
225 # ====================================================================
226 # ================= interface definitions for each method =============#
228 interface mux_lines = interface MuxSelectionLines
230 for cell
in p
.muxed_cells
:
232 mux_interface
.ifacedef(
233 cell
[0], cell_bit_width
))
234 bsv_file
.write("\n endinterface;")
237 interface iocell_side = interface IOCellSide
239 iocells
.ifacedef(bsv_file
)
240 bsv_file
.write("\n endinterface;")
243 interface peripheral_side = interface PeripheralSide
245 ifaces
.ifacedef(bsv_file
)
246 bsv_file
.write("\n endinterface;")
248 bsv_file
.write(footer
)
249 print("BSV file successfully generated: bsv_src/pinmux.bsv")
250 # ======================================================================
253 def write_ptp(ptp
, p
, ifaces
):
254 with
open(ptp
, 'w') as bsv_file
:
255 bsv_file
.write(copyright
+ '''
258 interface Ifc_PintTop;
259 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
260 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
261 interface PeripheralSide peripheral_side;
264 module mkPinTop(Ifc_PintTop);
265 // instantiate the pin-mux module here
266 Ifc_pinmux pinmux <-mkpinmux;
268 // declare the registers which will be used to mux the IOs
269 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
271 cell_bit_width
= str(p
.cell_bitwidth
)
272 for cell
in p
.muxed_cells
:
274 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
275 cell_bit_width
, cell
[0]))
278 // rule to connect the registers to the selection lines of the
280 rule connect_selection_registers;''')
282 for cell
in p
.muxed_cells
:
284 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
288 // method definitions for the write user interface
289 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
291 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
292 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
294 for cell
in p
.muxed_cells
:
296 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
306 // method definitions for the read user interface
307 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
310 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
311 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
313 for cell
in p
.muxed_cells
:
315 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
321 return tuple2(err,data);
323 interface peripheral_side=pinmux.peripheral_side;
329 def write_bvp(bvp
, p
, ifaces
):
330 # ######## Generate bus transactors ################
331 gpiocfg
= '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
332 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
333 muxcfg
= '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
334 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
336 gpiodec
= '\tGPIO#({0}) mygpio{1} <- mkgpio();'
337 muxdec
= '\tMUX#({0}) mymux{1} <- mkmux();'
338 gpioifc
= '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
339 '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
340 muxifc
= '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
341 '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
342 with
open(bvp
, 'w') as bsv_file
:
343 # assume here that all muxes have a 1:1 gpio
347 iks
= sorted(ifaces
.keys())
349 if not iname
.startswith('gpio'): # TODO: declare other interfaces
353 npins
= len(ifc
.pinspecs
)
354 cfg
.append(gpiocfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
357 cfg
.append(muxcfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
360 decl
.append(gpiodec
.format(npins
, bank
))
361 decl
.append(muxdec
.format(npins
, bank
))
362 idec
.append(gpioifc
.format(bank
))
363 idec
.append(muxifc
.format(bank
))
366 print dir(ifaces
['gpioa'])
367 print ifaces
['gpioa'].pinspecs
368 gpiodecl
= '\n'.join(decl
) + '\n' + '\n'.join(idec
)
369 gpiocfg
= '\n'.join(cfg
)
370 bsv_file
.write(axi4_lite
.format(gpiodecl
, gpiocfg
))
371 # ##################################################
374 def write_instances(idef
, p
, ifaces
):
375 with
open(idef
, 'w') as bsv_file
:
381 bsv_file
.write(txt
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))