2 * The implementations contained in this file are heavily based on the
3 * implementations found in the Berkeley SoftFloat library. As such, they are
4 * licensed under the same 3-clause BSD license:
6 * License for Berkeley SoftFloat Release 3e
11 * The following applies to the whole of SoftFloat Release 3e as well as to
12 * each source file individually.
14 * Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
15 * University of California. All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are met:
20 * 1. Redistributions of source code must retain the above copyright notice,
21 * this list of conditions, and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions, and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
27 * 3. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
32 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
34 * DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #extension GL_ARB_gpu_shader_int64 : enable
45 #extension GL_ARB_shader_bit_encoding : enable
46 #extension GL_EXT_shader_integer_mix : enable
47 #extension GL_MESA_shader_integer_functions : enable
51 /* Software IEEE floating-point rounding mode.
52 * GLSL spec section "4.7.1 Range and Precision":
53 * The rounding mode cannot be set and is undefined.
54 * But here, we are able to define the rounding mode at the compilation time.
56 #define FLOAT_ROUND_NEAREST_EVEN 0
57 #define FLOAT_ROUND_TO_ZERO 1
58 #define FLOAT_ROUND_DOWN 2
59 #define FLOAT_ROUND_UP 3
60 #define FLOAT_ROUNDING_MODE FLOAT_ROUND_NEAREST_EVEN
62 /* Absolute value of a Float64 :
66 __fabs64(uint64_t __a)
68 uvec2 a = unpackUint2x32(__a);
70 return packUint2x32(a);
73 /* Returns 1 if the double-precision floating-point value `a' is a NaN;
74 * otherwise returns 0.
77 __is_nan(uint64_t __a)
79 uvec2 a = unpackUint2x32(__a);
80 return (0xFFE00000u <= (a.y<<1)) &&
81 ((a.x != 0u) || ((a.y & 0x000FFFFFu) != 0u));
84 /* Negate value of a Float64 :
88 __fneg64(uint64_t __a)
90 uvec2 a = unpackUint2x32(__a);
92 return packUint2x32(a);
96 __fsign64(uint64_t __a)
98 uvec2 a = unpackUint2x32(__a);
101 retval.y = mix((a.y & 0x80000000u) | 0x3FF00000u, 0u, (a.y << 1 | a.x) == 0u);
102 return packUint2x32(retval);
105 /* Returns the fraction bits of the double-precision floating-point value `a'.*/
107 __extractFloat64FracLo(uint64_t a)
109 return unpackUint2x32(a).x;
113 __extractFloat64FracHi(uint64_t a)
115 return unpackUint2x32(a).y & 0x000FFFFFu;
118 /* Returns the exponent bits of the double-precision floating-point value `a'.*/
120 __extractFloat64Exp(uint64_t __a)
122 uvec2 a = unpackUint2x32(__a);
123 return int((a.y>>20) & 0x7FFu);
127 __feq64_nonnan(uint64_t __a, uint64_t __b)
129 uvec2 a = unpackUint2x32(__a);
130 uvec2 b = unpackUint2x32(__b);
131 return (a.x == b.x) &&
132 ((a.y == b.y) || ((a.x == 0u) && (((a.y | b.y)<<1) == 0u)));
135 /* Returns true if the double-precision floating-point value `a' is equal to the
136 * corresponding value `b', and false otherwise. The comparison is performed
137 * according to the IEEE Standard for Floating-Point Arithmetic.
140 __feq64(uint64_t a, uint64_t b)
142 if (__is_nan(a) || __is_nan(b))
145 return __feq64_nonnan(a, b);
148 /* Returns true if the double-precision floating-point value `a' is not equal
149 * to the corresponding value `b', and false otherwise. The comparison is
150 * performed according to the IEEE Standard for Floating-Point Arithmetic.
153 __fne64(uint64_t a, uint64_t b)
155 if (__is_nan(a) || __is_nan(b))
158 return !__feq64_nonnan(a, b);
161 /* Returns the sign bit of the double-precision floating-point value `a'.*/
163 __extractFloat64Sign(uint64_t a)
165 return unpackUint2x32(a).y & 0x80000000u;
168 /* Returns true if the signed 64-bit value formed by concatenating `a0' and
169 * `a1' is less than the signed 64-bit value formed by concatenating `b0' and
170 * `b1'. Otherwise, returns false.
173 ilt64(uint a0, uint a1, uint b0, uint b1)
175 return (int(a0) < int(b0)) || ((a0 == b0) && (a1 < b1));
179 __flt64_nonnan(uint64_t __a, uint64_t __b)
181 uvec2 a = unpackUint2x32(__a);
182 uvec2 b = unpackUint2x32(__b);
184 /* IEEE 754 floating point numbers are specifically designed so that, with
185 * two exceptions, values can be compared by bit-casting to signed integers
186 * with the same number of bits.
188 * From https://en.wikipedia.org/wiki/IEEE_754-1985#Comparing_floating-point_numbers:
190 * When comparing as 2's-complement integers: If the sign bits differ,
191 * the negative number precedes the positive number, so 2's complement
192 * gives the correct result (except that negative zero and positive zero
193 * should be considered equal). If both values are positive, the 2's
194 * complement comparison again gives the correct result. Otherwise (two
195 * negative numbers), the correct FP ordering is the opposite of the 2's
196 * complement ordering.
198 * The logic implied by the above quotation is:
200 * !both_are_zero(a, b) && (both_negative(a, b) ? a > b : a < b)
202 * This is equivalent to
204 * fne(a, b) && (both_negative(a, b) ? a >= b : a < b)
206 * fne(a, b) && (both_negative(a, b) ? !(a < b) : a < b)
208 * fne(a, b) && ((both_negative(a, b) && !(a < b)) ||
209 * (!both_negative(a, b) && (a < b)))
211 * (A!|B)&(A|!B) is (A xor B) which is implemented here using !=.
213 * fne(a, b) && (both_negative(a, b) != (a < b))
215 bool lt = ilt64(a.y, a.x, b.y, b.x);
216 bool both_negative = (a.y & b.y & 0x80000000u) != 0;
218 return !__feq64_nonnan(__a, __b) && (lt != both_negative);
221 /* Returns true if the double-precision floating-point value `a' is less than
222 * the corresponding value `b', and false otherwise. The comparison is performed
223 * according to the IEEE Standard for Floating-Point Arithmetic.
226 __flt64(uint64_t a, uint64_t b)
228 /* This weird layout matters. Doing the "obvious" thing results in extra
229 * flow control being inserted to implement the short-circuit evaluation
230 * rules. Flow control is bad!
232 bool x = !__is_nan(a);
233 bool y = !__is_nan(b);
234 bool z = __flt64_nonnan(a, b);
236 return (x && y && z);
239 /* Returns true if the double-precision floating-point value `a' is greater
240 * than or equal to * the corresponding value `b', and false otherwise. The
241 * comparison is performed * according to the IEEE Standard for Floating-Point
245 __fge64(uint64_t a, uint64_t b)
247 /* This weird layout matters. Doing the "obvious" thing results in extra
248 * flow control being inserted to implement the short-circuit evaluation
249 * rules. Flow control is bad!
251 bool x = !__is_nan(a);
252 bool y = !__is_nan(b);
253 bool z = !__flt64_nonnan(a, b);
255 return (x && y && z);
259 __fsat64(uint64_t __a)
261 /* fsat(NaN) should be zero. */
262 if (__is_nan(__a) || __flt64_nonnan(__a, 0ul))
265 if (!__flt64_nonnan(__a, 0x3FF0000000000000ul /* 1.0 */))
266 return 0x3FF0000000000000ul;
271 /* Adds the 64-bit value formed by concatenating `a0' and `a1' to the 64-bit
272 * value formed by concatenating `b0' and `b1'. Addition is modulo 2^64, so
273 * any carry out is lost. The result is broken into two 32-bit pieces which
274 * are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
277 __add64(uint a0, uint a1, uint b0, uint b1,
283 z0Ptr = a0 + b0 + uint(z1 < a1);
287 /* Subtracts the 64-bit value formed by concatenating `b0' and `b1' from the
288 * 64-bit value formed by concatenating `a0' and `a1'. Subtraction is modulo
289 * 2^64, so any borrow out (carry out) is lost. The result is broken into two
290 * 32-bit pieces which are stored at the locations pointed to by `z0Ptr' and
294 __sub64(uint a0, uint a1, uint b0, uint b1,
299 z0Ptr = a0 - b0 - uint(a1 < b1);
302 /* Shifts the 64-bit value formed by concatenating `a0' and `a1' right by the
303 * number of bits given in `count'. If any nonzero bits are shifted off, they
304 * are "jammed" into the least significant bit of the result by setting the
305 * least significant bit to 1. The value of `count' can be arbitrarily large;
306 * in particular, if `count' is greater than 64, the result will be either 0
307 * or 1, depending on whether the concatenation of `a0' and `a1' is zero or
308 * nonzero. The result is broken into two 32-bit pieces which are stored at
309 * the locations pointed to by `z0Ptr' and `z1Ptr'.
312 __shift64RightJamming(uint a0,
320 int negCount = (-count) & 31;
322 z0 = mix(0u, a0, count == 0);
323 z0 = mix(z0, (a0 >> count), count < 32);
325 z1 = uint((a0 | a1) != 0u); /* count >= 64 */
326 uint z1_lt64 = (a0>>(count & 31)) | uint(((a0<<negCount) | a1) != 0u);
327 z1 = mix(z1, z1_lt64, count < 64);
328 z1 = mix(z1, (a0 | uint(a1 != 0u)), count == 32);
329 uint z1_lt32 = (a0<<negCount) | (a1>>count) | uint ((a1<<negCount) != 0u);
330 z1 = mix(z1, z1_lt32, count < 32);
331 z1 = mix(z1, a1, count == 0);
336 /* Shifts the 96-bit value formed by concatenating `a0', `a1', and `a2' right
337 * by 32 _plus_ the number of bits given in `count'. The shifted result is
338 * at most 64 nonzero bits; these are broken into two 32-bit pieces which are
339 * stored at the locations pointed to by `z0Ptr' and `z1Ptr'. The bits shifted
340 * off form a third 32-bit result as follows: The _last_ bit shifted off is
341 * the most-significant bit of the extra result, and the other 31 bits of the
342 * extra result are all zero if and only if _all_but_the_last_ bits shifted off
343 * were all zero. This extra result is stored in the location pointed to by
344 * `z2Ptr'. The value of `count' can be arbitrarily large.
345 * (This routine makes more sense if `a0', `a1', and `a2' are considered
346 * to form a fixed-point value with binary point between `a1' and `a2'. This
347 * fixed-point value is shifted right by the number of bits given in `count',
348 * and the integer part of the result is returned at the locations pointed to
349 * by `z0Ptr' and `z1Ptr'. The fractional part of the result may be slightly
350 * corrupted as described above, and is returned at the location pointed to by
354 __shift64ExtraRightJamming(uint a0, uint a1, uint a2,
363 int negCount = (-count) & 31;
365 z2 = mix(uint(a0 != 0u), a0, count == 64);
366 z2 = mix(z2, a0 << negCount, count < 64);
367 z2 = mix(z2, a1 << negCount, count < 32);
369 z1 = mix(0u, (a0 >> (count & 31)), count < 64);
370 z1 = mix(z1, (a0<<negCount) | (a1>>count), count < 32);
372 a2 = mix(a2 | a1, a2, count < 32);
373 z0 = mix(z0, a0 >> count, count < 32);
374 z2 |= uint(a2 != 0u);
376 z0 = mix(z0, 0u, (count == 32));
377 z1 = mix(z1, a0, (count == 32));
378 z2 = mix(z2, a1, (count == 32));
379 z0 = mix(z0, a0, (count == 0));
380 z1 = mix(z1, a1, (count == 0));
381 z2 = mix(z2, a2, (count == 0));
387 /* Shifts the 64-bit value formed by concatenating `a0' and `a1' left by the
388 * number of bits given in `count'. Any bits shifted off are lost. The value
389 * of `count' must be less than 32. The result is broken into two 32-bit
390 * pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
393 __shortShift64Left(uint a0, uint a1,
399 z0Ptr = mix((a0 << count | (a1 >> ((-count) & 31))), a0, count == 0);
402 /* Packs the sign `zSign', the exponent `zExp', and the significand formed by
403 * the concatenation of `zFrac0' and `zFrac1' into a double-precision floating-
404 * point value, returning the result. After being shifted into the proper
405 * positions, the three fields `zSign', `zExp', and `zFrac0' are simply added
406 * together to form the most significant 32 bits of the result. This means
407 * that any integer portion of `zFrac0' will be added into the exponent. Since
408 * a properly normalized significand will have an integer portion equal to 1,
409 * the `zExp' input should be 1 less than the desired result exponent whenever
410 * `zFrac0' and `zFrac1' concatenated form a complete, normalized significand.
413 __packFloat64(uint zSign, int zExp, uint zFrac0, uint zFrac1)
417 z.y = zSign + (uint(zExp) << 20) + zFrac0;
419 return packUint2x32(z);
422 /* Takes an abstract floating-point value having sign `zSign', exponent `zExp',
423 * and extended significand formed by the concatenation of `zFrac0', `zFrac1',
424 * and `zFrac2', and returns the proper double-precision floating-point value
425 * corresponding to the abstract input. Ordinarily, the abstract value is
426 * simply rounded and packed into the double-precision format, with the inexact
427 * exception raised if the abstract input cannot be represented exactly.
428 * However, if the abstract value is too large, the overflow and inexact
429 * exceptions are raised and an infinity or maximal finite value is returned.
430 * If the abstract value is too small, the input value is rounded to a
431 * subnormal number, and the underflow and inexact exceptions are raised if the
432 * abstract input cannot be represented exactly as a subnormal double-precision
433 * floating-point number.
434 * The input significand must be normalized or smaller. If the input
435 * significand is not normalized, `zExp' must be 0; in that case, the result
436 * returned is a subnormal number, and it must not require rounding. In the
437 * usual case that the input significand is normalized, `zExp' must be 1 less
438 * than the "true" floating-point exponent. The handling of underflow and
439 * overflow follows the IEEE Standard for Floating-Point Arithmetic.
442 __roundAndPackFloat64(uint zSign,
448 bool roundNearestEven;
451 roundNearestEven = FLOAT_ROUNDING_MODE == FLOAT_ROUND_NEAREST_EVEN;
452 increment = int(zFrac2) < 0;
453 if (!roundNearestEven) {
454 if (FLOAT_ROUNDING_MODE == FLOAT_ROUND_TO_ZERO) {
458 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN) &&
461 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP) &&
467 if ((0x7FD < zExp) ||
469 (0x001FFFFFu == zFrac0 && 0xFFFFFFFFu == zFrac1) &&
471 if ((FLOAT_ROUNDING_MODE == FLOAT_ROUND_TO_ZERO) ||
472 ((zSign != 0u) && (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP)) ||
473 ((zSign == 0u) && (FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN))) {
474 return __packFloat64(zSign, 0x7FE, 0x000FFFFFu, 0xFFFFFFFFu);
476 return __packFloat64(zSign, 0x7FF, 0u, 0u);
479 __shift64ExtraRightJamming(
480 zFrac0, zFrac1, zFrac2, -zExp, zFrac0, zFrac1, zFrac2);
482 if (roundNearestEven) {
483 increment = zFrac2 < 0u;
486 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN) &&
489 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP) &&
496 __add64(zFrac0, zFrac1, 0u, 1u, zFrac0, zFrac1);
497 zFrac1 &= ~((zFrac2 + uint(zFrac2 == 0u)) & uint(roundNearestEven));
499 zExp = mix(zExp, 0, (zFrac0 | zFrac1) == 0u);
501 return __packFloat64(zSign, zExp, zFrac0, zFrac1);
505 __roundAndPackUInt64(uint zSign, uint zFrac0, uint zFrac1, uint zFrac2)
507 bool roundNearestEven;
509 uint64_t default_nan = 0xFFFFFFFFFFFFFFFFUL;
511 roundNearestEven = FLOAT_ROUNDING_MODE == FLOAT_ROUND_NEAREST_EVEN;
513 if (zFrac2 >= 0x80000000u)
516 if (!roundNearestEven) {
518 if ((FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN) && (zFrac2 != 0u)) {
522 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP) &&
528 __add64(zFrac0, zFrac1, 0u, 1u, zFrac0, zFrac1);
529 if ((zFrac0 | zFrac1) != 0u)
530 zFrac1 &= ~(1u) + uint(zFrac2 == 0u) & uint(roundNearestEven);
532 return mix(packUint2x32(uvec2(zFrac1, zFrac0)), default_nan,
533 (zSign != 0u && (zFrac0 | zFrac1) != 0u));
537 __roundAndPackInt64(uint zSign, uint zFrac0, uint zFrac1, uint zFrac2)
539 bool roundNearestEven;
541 int64_t default_NegNaN = -0x7FFFFFFFFFFFFFFEL;
542 int64_t default_PosNaN = 0xFFFFFFFFFFFFFFFFL;
544 roundNearestEven = FLOAT_ROUNDING_MODE == FLOAT_ROUND_NEAREST_EVEN;
546 if (zFrac2 >= 0x80000000u)
549 if (!roundNearestEven) {
551 increment = ((FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN) &&
554 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP) &&
560 __add64(zFrac0, zFrac1, 0u, 1u, zFrac0, zFrac1);
561 if ((zFrac0 | zFrac1) != 0u)
562 zFrac1 &= ~(1u) + uint(zFrac2 == 0u) & uint(roundNearestEven);
565 int64_t absZ = mix(int64_t(packUint2x32(uvec2(zFrac1, zFrac0))),
566 -int64_t(packUint2x32(uvec2(zFrac1, zFrac0))),
568 int64_t nan = mix(default_PosNaN, default_NegNaN, zSign != 0u);
569 return mix(absZ, nan, ((zSign != 0u) != (absZ < 0)) && bool(absZ));
572 /* Returns the number of leading 0 bits before the most-significant 1 bit of
573 * `a'. If `a' is zero, 32 is returned.
576 __countLeadingZeros32(uint a)
578 return 31 - findMSB(a);
581 /* Takes an abstract floating-point value having sign `zSign', exponent `zExp',
582 * and significand formed by the concatenation of `zSig0' and `zSig1', and
583 * returns the proper double-precision floating-point value corresponding
584 * to the abstract input. This routine is just like `__roundAndPackFloat64'
585 * except that the input significand has fewer bits and does not have to be
586 * normalized. In all cases, `zExp' must be 1 less than the "true" floating-
590 __normalizeRoundAndPackFloat64(uint zSign,
604 shiftCount = __countLeadingZeros32(zFrac0) - 11;
605 if (0 <= shiftCount) {
607 __shortShift64Left(zFrac0, zFrac1, shiftCount, zFrac0, zFrac1);
609 __shift64ExtraRightJamming(
610 zFrac0, zFrac1, 0u, -shiftCount, zFrac0, zFrac1, zFrac2);
613 return __roundAndPackFloat64(zSign, zExp, zFrac0, zFrac1, zFrac2);
616 /* Takes two double-precision floating-point values `a' and `b', one of which
617 * is a NaN, and returns the appropriate NaN result.
620 __propagateFloat64NaN(uint64_t __a, uint64_t __b)
622 bool aIsNaN = __is_nan(__a);
623 bool bIsNaN = __is_nan(__b);
624 uvec2 a = unpackUint2x32(__a);
625 uvec2 b = unpackUint2x32(__b);
629 return packUint2x32(mix(b, mix(a, b, bvec2(bIsNaN, bIsNaN)), bvec2(aIsNaN, aIsNaN)));
632 /* Returns the result of adding the double-precision floating-point values
633 * `a' and `b'. The operation is performed according to the IEEE Standard for
634 * Floating-Point Arithmetic.
637 __fadd64(uint64_t a, uint64_t b)
639 uint aSign = __extractFloat64Sign(a);
640 uint bSign = __extractFloat64Sign(b);
641 uint aFracLo = __extractFloat64FracLo(a);
642 uint aFracHi = __extractFloat64FracHi(a);
643 uint bFracLo = __extractFloat64FracLo(b);
644 uint bFracHi = __extractFloat64FracHi(b);
645 int aExp = __extractFloat64Exp(a);
646 int bExp = __extractFloat64Exp(b);
649 int expDiff = aExp - bExp;
650 if (aSign == bSign) {
653 bool orig_exp_diff_is_zero = (expDiff == 0);
655 if (orig_exp_diff_is_zero) {
657 bool propagate = (aFracHi | aFracLo | bFracHi | bFracLo) != 0u;
658 return mix(a, __propagateFloat64NaN(a, b), propagate);
660 __add64(aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1);
662 return __packFloat64(aSign, 0, zFrac0, zFrac1);
664 zFrac0 |= 0x00200000u;
666 __shift64ExtraRightJamming(
667 zFrac0, zFrac1, zFrac2, 1, zFrac0, zFrac1, zFrac2);
668 } else if (0 < expDiff) {
670 bool propagate = (aFracHi | aFracLo) != 0u;
671 return mix(a, __propagateFloat64NaN(a, b), propagate);
674 expDiff = mix(expDiff, expDiff - 1, bExp == 0);
675 bFracHi = mix(bFracHi | 0x00100000u, bFracHi, bExp == 0);
676 __shift64ExtraRightJamming(
677 bFracHi, bFracLo, 0u, expDiff, bFracHi, bFracLo, zFrac2);
679 } else if (expDiff < 0) {
681 bool propagate = (bFracHi | bFracLo) != 0u;
682 return mix(__packFloat64(aSign, 0x7ff, 0u, 0u), __propagateFloat64NaN(a, b), propagate);
684 expDiff = mix(expDiff, expDiff + 1, aExp == 0);
685 aFracHi = mix(aFracHi | 0x00100000u, aFracHi, aExp == 0);
686 __shift64ExtraRightJamming(
687 aFracHi, aFracLo, 0u, - expDiff, aFracHi, aFracLo, zFrac2);
690 if (!orig_exp_diff_is_zero) {
691 aFracHi |= 0x00100000u;
692 __add64(aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1);
694 if (!(zFrac0 < 0x00200000u)) {
695 __shift64ExtraRightJamming(zFrac0, zFrac1, zFrac2, 1, zFrac0, zFrac1, zFrac2);
699 return __roundAndPackFloat64(aSign, zExp, zFrac0, zFrac1, zFrac2);
704 __shortShift64Left(aFracHi, aFracLo, 10, aFracHi, aFracLo);
705 __shortShift64Left(bFracHi, bFracLo, 10, bFracHi, bFracLo);
708 bool propagate = (aFracHi | aFracLo) != 0u;
709 return mix(a, __propagateFloat64NaN(a, b), propagate);
711 expDiff = mix(expDiff, expDiff - 1, bExp == 0);
712 bFracHi = mix(bFracHi | 0x40000000u, bFracHi, bExp == 0);
713 __shift64RightJamming(bFracHi, bFracLo, expDiff, bFracHi, bFracLo);
714 aFracHi |= 0x40000000u;
715 __sub64(aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1);
718 return __normalizeRoundAndPackFloat64(aSign, zExp - 10, zFrac0, zFrac1);
722 bool propagate = (bFracHi | bFracLo) != 0u;
723 return mix(__packFloat64(aSign ^ 0x80000000u, 0x7ff, 0u, 0u), __propagateFloat64NaN(a, b), propagate);
725 expDiff = mix(expDiff, expDiff + 1, aExp == 0);
726 aFracHi = mix(aFracHi | 0x40000000u, aFracHi, aExp == 0);
727 __shift64RightJamming(aFracHi, aFracLo, - expDiff, aFracHi, aFracLo);
728 bFracHi |= 0x40000000u;
729 __sub64(bFracHi, bFracLo, aFracHi, aFracLo, zFrac0, zFrac1);
731 aSign ^= 0x80000000u;
733 return __normalizeRoundAndPackFloat64(aSign, zExp - 10, zFrac0, zFrac1);
736 bool propagate = (aFracHi | aFracLo | bFracHi | bFracLo) != 0u;
737 return mix(0xFFFFFFFFFFFFFFFFUL, __propagateFloat64NaN(a, b), propagate);
739 bExp = mix(bExp, 1, aExp == 0);
740 aExp = mix(aExp, 1, aExp == 0);
741 bool zexp_normal = false;
743 if (bFracHi < aFracHi) {
744 __sub64(aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1);
747 else if (aFracHi < bFracHi) {
748 __sub64(bFracHi, bFracLo, aFracHi, aFracLo, zFrac0, zFrac1);
752 else if (bFracLo < aFracLo) {
753 __sub64(aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1);
756 else if (aFracLo < bFracLo) {
757 __sub64(bFracHi, bFracLo, aFracHi, aFracLo, zFrac0, zFrac1);
761 zExp = mix(bExp, aExp, blta);
762 aSign = mix(aSign ^ 0x80000000u, aSign, blta);
763 uint64_t retval_0 = __packFloat64(uint(FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN) << 31, 0, 0u, 0u);
764 uint64_t retval_1 = __normalizeRoundAndPackFloat64(aSign, zExp - 11, zFrac0, zFrac1);
765 return mix(retval_0, retval_1, zexp_normal);
769 /* Multiplies the 64-bit value formed by concatenating `a0' and `a1' to the
770 * 64-bit value formed by concatenating `b0' and `b1' to obtain a 128-bit
771 * product. The product is broken into four 32-bit pieces which are stored at
772 * the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.
775 __mul64To128(uint a0, uint a1, uint b0, uint b1,
788 umulExtended(a1, b1, z2, z3);
789 umulExtended(a1, b0, z1, more2);
790 __add64(z1, more2, 0u, z2, z1, z2);
791 umulExtended(a0, b0, z0, more1);
792 __add64(z0, more1, 0u, z1, z0, z1);
793 umulExtended(a0, b1, more1, more2);
794 __add64(more1, more2, 0u, z2, more1, z2);
795 __add64(z0, z1, 0u, more1, z0, z1);
802 /* Normalizes the subnormal double-precision floating-point value represented
803 * by the denormalized significand formed by the concatenation of `aFrac0' and
804 * `aFrac1'. The normalized exponent is stored at the location pointed to by
805 * `zExpPtr'. The most significant 21 bits of the normalized significand are
806 * stored at the location pointed to by `zFrac0Ptr', and the least significant
807 * 32 bits of the normalized significand are stored at the location pointed to
811 __normalizeFloat64Subnormal(uint aFrac0, uint aFrac1,
817 uint temp_zfrac0, temp_zfrac1;
818 shiftCount = __countLeadingZeros32(mix(aFrac0, aFrac1, aFrac0 == 0u)) - 11;
819 zExpPtr = mix(1 - shiftCount, -shiftCount - 31, aFrac0 == 0u);
821 temp_zfrac0 = mix(aFrac1<<shiftCount, aFrac1>>(-shiftCount), shiftCount < 0);
822 temp_zfrac1 = mix(0u, aFrac1<<(shiftCount & 31), shiftCount < 0);
824 __shortShift64Left(aFrac0, aFrac1, shiftCount, zFrac0Ptr, zFrac1Ptr);
826 zFrac0Ptr = mix(zFrac0Ptr, temp_zfrac0, aFrac0 == 0);
827 zFrac1Ptr = mix(zFrac1Ptr, temp_zfrac1, aFrac0 == 0);
830 /* Returns the result of multiplying the double-precision floating-point values
831 * `a' and `b'. The operation is performed according to the IEEE Standard for
832 * Floating-Point Arithmetic.
835 __fmul64(uint64_t a, uint64_t b)
843 uint aFracLo = __extractFloat64FracLo(a);
844 uint aFracHi = __extractFloat64FracHi(a);
845 uint bFracLo = __extractFloat64FracLo(b);
846 uint bFracHi = __extractFloat64FracHi(b);
847 int aExp = __extractFloat64Exp(a);
848 uint aSign = __extractFloat64Sign(a);
849 int bExp = __extractFloat64Exp(b);
850 uint bSign = __extractFloat64Sign(b);
851 uint zSign = aSign ^ bSign;
853 if (((aFracHi | aFracLo) != 0u) ||
854 ((bExp == 0x7FF) && ((bFracHi | bFracLo) != 0u))) {
855 return __propagateFloat64NaN(a, b);
857 if ((uint(bExp) | bFracHi | bFracLo) == 0u)
858 return 0xFFFFFFFFFFFFFFFFUL;
859 return __packFloat64(zSign, 0x7FF, 0u, 0u);
862 if ((bFracHi | bFracLo) != 0u)
863 return __propagateFloat64NaN(a, b);
864 if ((uint(aExp) | aFracHi | aFracLo) == 0u)
865 return 0xFFFFFFFFFFFFFFFFUL;
866 return __packFloat64(zSign, 0x7FF, 0u, 0u);
869 if ((aFracHi | aFracLo) == 0u)
870 return __packFloat64(zSign, 0, 0u, 0u);
871 __normalizeFloat64Subnormal(aFracHi, aFracLo, aExp, aFracHi, aFracLo);
874 if ((bFracHi | bFracLo) == 0u)
875 return __packFloat64(zSign, 0, 0u, 0u);
876 __normalizeFloat64Subnormal(bFracHi, bFracLo, bExp, bFracHi, bFracLo);
878 zExp = aExp + bExp - 0x400;
879 aFracHi |= 0x00100000u;
880 __shortShift64Left(bFracHi, bFracLo, 12, bFracHi, bFracLo);
882 aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1, zFrac2, zFrac3);
883 __add64(zFrac0, zFrac1, aFracHi, aFracLo, zFrac0, zFrac1);
884 zFrac2 |= uint(zFrac3 != 0u);
885 if (0x00200000u <= zFrac0) {
886 __shift64ExtraRightJamming(
887 zFrac0, zFrac1, zFrac2, 1, zFrac0, zFrac1, zFrac2);
890 return __roundAndPackFloat64(zSign, zExp, zFrac0, zFrac1, zFrac2);
894 __ffma64(uint64_t a, uint64_t b, uint64_t c)
896 return __fadd64(__fmul64(a, b), c);
899 /* Shifts the 64-bit value formed by concatenating `a0' and `a1' right by the
900 * number of bits given in `count'. Any bits shifted off are lost. The value
901 * of `count' can be arbitrarily large; in particular, if `count' is greater
902 * than 64, the result will be 0. The result is broken into two 32-bit pieces
903 * which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
906 __shift64Right(uint a0, uint a1,
913 int negCount = (-count) & 31;
916 z0 = mix(z0, (a0 >> count), count < 32);
917 z0 = mix(z0, a0, count == 0);
919 z1 = mix(0u, (a0 >> (count & 31)), count < 64);
920 z1 = mix(z1, (a0<<negCount) | (a1>>count), count < 32);
921 z1 = mix(z1, a0, count == 0);
927 /* Returns the result of converting the double-precision floating-point value
928 * `a' to the unsigned integer format. The conversion is performed according
929 * to the IEEE Standard for Floating-Point Arithmetic.
932 __fp64_to_uint(uint64_t a)
934 uint aFracLo = __extractFloat64FracLo(a);
935 uint aFracHi = __extractFloat64FracHi(a);
936 int aExp = __extractFloat64Exp(a);
937 uint aSign = __extractFloat64Sign(a);
939 if ((aExp == 0x7FF) && ((aFracHi | aFracLo) != 0u))
942 aFracHi |= mix(0u, 0x00100000u, aExp != 0);
944 int shiftDist = 0x427 - aExp;
946 __shift64RightJamming(aFracHi, aFracLo, shiftDist, aFracHi, aFracLo);
948 if ((aFracHi & 0xFFFFF000u) != 0u)
949 return mix(~0u, 0u, aSign != 0u);
953 __shift64Right(aFracHi, aFracLo, 12, zero, z);
955 uint expt = mix(~0u, 0u, aSign != 0u);
957 return mix(z, expt, (aSign != 0u) && (z != 0u));
961 __uint_to_fp64(uint a)
966 int shiftDist = __countLeadingZeros32(a) + 21;
970 int negCount = (- shiftDist) & 31;
972 aHigh = mix(0u, a<< shiftDist - 32, shiftDist < 64);
974 aHigh = mix(aHigh, 0u, shiftDist == 0);
975 aLow = mix(aLow, a, shiftDist ==0);
976 aHigh = mix(aHigh, a >> negCount, shiftDist < 32);
977 aLow = mix(aLow, a << shiftDist, shiftDist < 32);
979 return __packFloat64(0u, 0x432 - shiftDist, aHigh, aLow);
983 __uint64_to_fp64(uint64_t a)
988 uvec2 aFrac = unpackUint2x32(a);
989 uint aFracLo = __extractFloat64FracLo(a);
990 uint aFracHi = __extractFloat64FracHi(a);
992 if ((aFracHi & 0x80000000u) != 0u) {
993 __shift64RightJamming(aFracHi, aFracLo, 1, aFracHi, aFracLo);
994 return __roundAndPackFloat64(0, 0x433, aFracHi, aFracLo, 0u);
996 return __normalizeRoundAndPackFloat64(0, 0x432, aFrac.y, aFrac.x);
1001 __fp64_to_uint64(uint64_t a)
1003 uint aFracLo = __extractFloat64FracLo(a);
1004 uint aFracHi = __extractFloat64FracHi(a);
1005 int aExp = __extractFloat64Exp(a);
1006 uint aSign = __extractFloat64Sign(a);
1008 uint64_t default_nan = 0xFFFFFFFFFFFFFFFFUL;
1010 aFracHi = mix(aFracHi, aFracHi | 0x00100000u, aExp != 0);
1011 int shiftCount = 0x433 - aExp;
1013 if ( shiftCount <= 0 ) {
1014 if (shiftCount < -11 && aExp == 0x7FF) {
1015 if ((aFracHi | aFracLo) != 0u)
1016 return __propagateFloat64NaN(a, a);
1017 return mix(default_nan, a, aSign == 0u);
1019 __shortShift64Left(aFracHi, aFracLo, -shiftCount, aFracHi, aFracLo);
1021 __shift64ExtraRightJamming(aFracHi, aFracLo, zFrac2, shiftCount,
1022 aFracHi, aFracLo, zFrac2);
1024 return __roundAndPackUInt64(aSign, aFracHi, aFracLo, zFrac2);
1028 __fp64_to_int64(uint64_t a)
1031 uint aFracLo = __extractFloat64FracLo(a);
1032 uint aFracHi = __extractFloat64FracHi(a);
1033 int aExp = __extractFloat64Exp(a);
1034 uint aSign = __extractFloat64Sign(a);
1035 int64_t default_NegNaN = -0x7FFFFFFFFFFFFFFEL;
1036 int64_t default_PosNaN = 0xFFFFFFFFFFFFFFFFL;
1038 aFracHi = mix(aFracHi, aFracHi | 0x00100000u, aExp != 0);
1039 int shiftCount = 0x433 - aExp;
1041 if (shiftCount <= 0) {
1042 if (shiftCount < -11 && aExp == 0x7FF) {
1043 if ((aFracHi | aFracLo) != 0u)
1044 return default_NegNaN;
1045 return mix(default_NegNaN, default_PosNaN, aSign == 0u);
1047 __shortShift64Left(aFracHi, aFracLo, -shiftCount, aFracHi, aFracLo);
1049 __shift64ExtraRightJamming(aFracHi, aFracLo, zFrac2, shiftCount,
1050 aFracHi, aFracLo, zFrac2);
1053 return __roundAndPackInt64(aSign, aFracHi, aFracLo, zFrac2);
1057 __fp32_to_uint64(float f)
1059 uint a = floatBitsToUint(f);
1060 uint aFrac = a & 0x007FFFFFu;
1061 int aExp = int((a>>23) & 0xFFu);
1062 uint aSign = a & 0x80000000u;
1066 uint64_t default_nan = 0xFFFFFFFFFFFFFFFFUL;
1067 int shiftCount = 0xBE - aExp;
1069 if (shiftCount <0) {
1074 aFrac = mix(aFrac, aFrac | 0x00800000u, aExp != 0);
1075 __shortShift64Left(aFrac, 0, 40, zFrac0, zFrac1);
1077 if (shiftCount != 0) {
1078 __shift64ExtraRightJamming(zFrac0, zFrac1, zFrac2, shiftCount,
1079 zFrac0, zFrac1, zFrac2);
1082 return __roundAndPackUInt64(aSign, zFrac0, zFrac1, zFrac2);
1086 __fp32_to_int64(float f)
1088 uint a = floatBitsToUint(f);
1089 uint aFrac = a & 0x007FFFFFu;
1090 int aExp = int((a>>23) & 0xFFu);
1091 uint aSign = a & 0x80000000u;
1095 int64_t default_NegNaN = -0x7FFFFFFFFFFFFFFEL;
1096 int64_t default_PosNaN = 0xFFFFFFFFFFFFFFFFL;
1097 int shiftCount = 0xBE - aExp;
1099 if (shiftCount <0) {
1100 if (aExp == 0xFF && aFrac != 0u)
1101 return default_NegNaN;
1102 return mix(default_NegNaN, default_PosNaN, aSign == 0u);
1105 aFrac = mix(aFrac, aFrac | 0x00800000u, aExp != 0);
1106 __shortShift64Left(aFrac, 0, 40, zFrac0, zFrac1);
1108 if (shiftCount != 0) {
1109 __shift64ExtraRightJamming(zFrac0, zFrac1, zFrac2, shiftCount,
1110 zFrac0, zFrac1, zFrac2);
1113 return __roundAndPackInt64(aSign, zFrac0, zFrac1, zFrac2);
1117 __int64_to_fp64(int64_t a)
1122 uint64_t absA = mix(uint64_t(a), uint64_t(-a), a < 0);
1123 uint aFracHi = __extractFloat64FracHi(absA);
1124 uvec2 aFrac = unpackUint2x32(absA);
1125 uint zSign = uint(unpackInt2x32(a).y) & 0x80000000u;
1127 if ((aFracHi & 0x80000000u) != 0u) {
1128 return mix(0ul, __packFloat64(0x80000000u, 0x434, 0u, 0u), a < 0);
1131 return __normalizeRoundAndPackFloat64(zSign, 0x432, aFrac.y, aFrac.x);
1134 /* Returns the result of converting the double-precision floating-point value
1135 * `a' to the 32-bit two's complement integer format. The conversion is
1136 * performed according to the IEEE Standard for Floating-Point Arithmetic---
1137 * which means in particular that the conversion is rounded according to the
1138 * current rounding mode. If `a' is a NaN, the largest positive integer is
1139 * returned. Otherwise, if the conversion overflows, the largest integer with
1140 * the same sign as `a' is returned.
1143 __fp64_to_int(uint64_t a)
1145 uint aFracLo = __extractFloat64FracLo(a);
1146 uint aFracHi = __extractFloat64FracHi(a);
1147 int aExp = __extractFloat64Exp(a);
1148 uint aSign = __extractFloat64Sign(a);
1151 uint aFracExtra = 0u;
1152 int shiftCount = aExp - 0x413;
1154 if (0 <= shiftCount) {
1156 if ((aExp == 0x7FF) && bool(aFracHi | aFracLo))
1158 return mix(0x7FFFFFFF, 0x80000000, aSign != 0u);
1160 __shortShift64Left(aFracHi | 0x00100000u, aFracLo, shiftCount, absZ, aFracExtra);
1165 aFracHi |= 0x00100000u;
1166 aFracExtra = ( aFracHi << (shiftCount & 31)) | aFracLo;
1167 absZ = aFracHi >> (- shiftCount);
1170 int z = mix(int(absZ), -int(absZ), aSign != 0u);
1171 int nan = mix(0x7FFFFFFF, 0x80000000, aSign != 0u);
1172 return mix(z, nan, ((aSign != 0u) != (z < 0)) && bool(z));
1175 /* Returns the result of converting the 32-bit two's complement integer `a'
1176 * to the double-precision floating-point format. The conversion is performed
1177 * according to the IEEE Standard for Floating-Point Arithmetic.
1180 __int_to_fp64(int a)
1185 return __packFloat64(0u, 0, 0u, 0u);
1186 uint zSign = uint(a) & 0x80000000u;
1187 uint absA = mix(uint(a), uint(-a), a < 0);
1188 int shiftCount = __countLeadingZeros32(absA) - 11;
1189 if (0 <= shiftCount) {
1190 zFrac0 = absA << shiftCount;
1193 __shift64Right(absA, 0u, -shiftCount, zFrac0, zFrac1);
1195 return __packFloat64(zSign, 0x412 - shiftCount, zFrac0, zFrac1);
1199 __fp64_to_bool(uint64_t a)
1201 return !__feq64_nonnan(__fabs64(a), 0ul);
1205 __bool_to_fp64(bool a)
1207 return packUint2x32(uvec2(0x00000000u, uint(-int(a) & 0x3ff00000)));
1210 /* Packs the sign `zSign', exponent `zExp', and significand `zFrac' into a
1211 * single-precision floating-point value, returning the result. After being
1212 * shifted into the proper positions, the three fields are simply added
1213 * together to form the result. This means that any integer portion of `zSig'
1214 * will be added into the exponent. Since a properly normalized significand
1215 * will have an integer portion equal to 1, the `zExp' input should be 1 less
1216 * than the desired result exponent whenever `zFrac' is a complete, normalized
1220 __packFloat32(uint zSign, int zExp, uint zFrac)
1222 return uintBitsToFloat(zSign + (uint(zExp)<<23) + zFrac);
1225 /* Takes an abstract floating-point value having sign `zSign', exponent `zExp',
1226 * and significand `zFrac', and returns the proper single-precision floating-
1227 * point value corresponding to the abstract input. Ordinarily, the abstract
1228 * value is simply rounded and packed into the single-precision format, with
1229 * the inexact exception raised if the abstract input cannot be represented
1230 * exactly. However, if the abstract value is too large, the overflow and
1231 * inexact exceptions are raised and an infinity or maximal finite value is
1232 * returned. If the abstract value is too small, the input value is rounded to
1233 * a subnormal number, and the underflow and inexact exceptions are raised if
1234 * the abstract input cannot be represented exactly as a subnormal single-
1235 * precision floating-point number.
1236 * The input significand `zFrac' has its binary point between bits 30
1237 * and 29, which is 7 bits to the left of the usual location. This shifted
1238 * significand must be normalized or smaller. If `zFrac' is not normalized,
1239 * `zExp' must be 0; in that case, the result returned is a subnormal number,
1240 * and it must not require rounding. In the usual case that `zFrac' is
1241 * normalized, `zExp' must be 1 less than the "true" floating-point exponent.
1242 * The handling of underflow and overflow follows the IEEE Standard for
1243 * Floating-Point Arithmetic.
1246 __roundAndPackFloat32(uint zSign, int zExp, uint zFrac)
1248 bool roundNearestEven;
1252 roundNearestEven = FLOAT_ROUNDING_MODE == FLOAT_ROUND_NEAREST_EVEN;
1253 roundIncrement = 0x40;
1254 if (!roundNearestEven) {
1255 if (FLOAT_ROUNDING_MODE == FLOAT_ROUND_TO_ZERO) {
1258 roundIncrement = 0x7F;
1260 if (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP)
1263 if (FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN)
1268 roundBits = int(zFrac & 0x7Fu);
1269 if (0xFDu <= uint(zExp)) {
1270 if ((0xFD < zExp) || ((zExp == 0xFD) && (int(zFrac) + roundIncrement) < 0))
1271 return __packFloat32(zSign, 0xFF, 0u) - float(roundIncrement == 0);
1273 bool zexp_lt0 = zExp < 0;
1274 uint zFrac_lt0 = mix(uint(zFrac != 0u), (zFrac>>count) | uint((zFrac<<((-count) & 31)) != 0u), (-zExp) < 32);
1275 zFrac = mix(zFrac, zFrac_lt0, zexp_lt0);
1276 roundBits = mix(roundBits, int(zFrac) & 0x7f, zexp_lt0);
1277 zExp = mix(zExp, 0, zexp_lt0);
1279 zFrac = (zFrac + uint(roundIncrement))>>7;
1280 zFrac &= ~uint(((roundBits ^ 0x40) == 0) && roundNearestEven);
1282 return __packFloat32(zSign, mix(zExp, 0, zFrac == 0u), zFrac);
1285 /* Returns the result of converting the double-precision floating-point value
1286 * `a' to the single-precision floating-point format. The conversion is
1287 * performed according to the IEEE Standard for Floating-Point Arithmetic.
1290 __fp64_to_fp32(uint64_t __a)
1292 uvec2 a = unpackUint2x32(__a);
1296 uint aFracLo = __extractFloat64FracLo(__a);
1297 uint aFracHi = __extractFloat64FracHi(__a);
1298 int aExp = __extractFloat64Exp(__a);
1299 uint aSign = __extractFloat64Sign(__a);
1300 if (aExp == 0x7FF) {
1301 __shortShift64Left(a.y, a.x, 12, a.y, a.x);
1302 float rval = uintBitsToFloat(aSign | 0x7FC00000u | (a.y>>9));
1303 rval = mix(__packFloat32(aSign, 0xFF, 0u), rval, (aFracHi | aFracLo) != 0u);
1306 __shift64RightJamming(aFracHi, aFracLo, 22, allZero, zFrac);
1307 zFrac = mix(zFrac, zFrac | 0x40000000u, aExp != 0);
1308 return __roundAndPackFloat32(aSign, aExp - 0x381, zFrac);
1312 __uint64_to_fp32(uint64_t __a)
1314 uvec2 aFrac = unpackUint2x32(__a);
1315 int shiftCount = mix(__countLeadingZeros32(aFrac.y) - 33,
1316 __countLeadingZeros32(aFrac.x) - 1,
1319 if (0 <= shiftCount)
1320 __shortShift64Left(aFrac.y, aFrac.x, shiftCount, aFrac.y, aFrac.x);
1322 __shift64RightJamming(aFrac.y, aFrac.x, -shiftCount, aFrac.y, aFrac.x);
1324 return __roundAndPackFloat32(0u, 0x9C - shiftCount, aFrac.x);
1328 __int64_to_fp32(int64_t __a)
1330 uint aSign = uint(unpackInt2x32(__a).y) & 0x80000000u;
1331 uint64_t absA = mix(uint64_t(__a), uint64_t(-__a), __a < 0);
1332 uvec2 aFrac = unpackUint2x32(absA);
1333 int shiftCount = mix(__countLeadingZeros32(aFrac.y) - 33,
1334 __countLeadingZeros32(aFrac.x) - 1,
1337 if (0 <= shiftCount)
1338 __shortShift64Left(aFrac.y, aFrac.x, shiftCount, aFrac.y, aFrac.x);
1340 __shift64RightJamming(aFrac.y, aFrac.x, -shiftCount, aFrac.y, aFrac.x);
1342 return __roundAndPackFloat32(aSign, 0x9C - shiftCount, aFrac.x);
1345 /* Returns the result of converting the single-precision floating-point value
1346 * `a' to the double-precision floating-point format.
1349 __fp32_to_fp64(float f)
1351 uint a = floatBitsToUint(f);
1352 uint aFrac = a & 0x007FFFFFu;
1353 int aExp = int((a>>23) & 0xFFu);
1354 uint aSign = a & 0x80000000u;
1362 __shift64Right(nanHi, nanLo, 12, nanHi, nanLo);
1363 nanHi |= aSign | 0x7FF80000u;
1364 return packUint2x32(uvec2(nanLo, nanHi));
1366 return __packFloat64(aSign, 0x7FF, 0u, 0u);
1371 return __packFloat64(aSign, 0, 0u, 0u);
1372 /* Normalize subnormal */
1373 int shiftCount = __countLeadingZeros32(aFrac) - 8;
1374 aFrac <<= shiftCount;
1375 aExp = 1 - shiftCount;
1379 __shift64Right(aFrac, 0u, 3, zFrac0, zFrac1);
1380 return __packFloat64(aSign, aExp + 0x380, zFrac0, zFrac1);
1383 /* Adds the 96-bit value formed by concatenating `a0', `a1', and `a2' to the
1384 * 96-bit value formed by concatenating `b0', `b1', and `b2'. Addition is
1385 * modulo 2^96, so any carry out is lost. The result is broken into three
1386 * 32-bit pieces which are stored at the locations pointed to by `z0Ptr',
1387 * `z1Ptr', and `z2Ptr'.
1390 __add96(uint a0, uint a1, uint a2,
1391 uint b0, uint b1, uint b2,
1397 uint carry1 = uint(z2 < a2);
1399 uint carry0 = uint(z1 < a1);
1402 z0 += uint(z1 < carry1);
1409 /* Subtracts the 96-bit value formed by concatenating `b0', `b1', and `b2' from
1410 * the 96-bit value formed by concatenating `a0', `a1', and `a2'. Subtraction
1411 * is modulo 2^96, so any borrow out (carry out) is lost. The result is broken
1412 * into three 32-bit pieces which are stored at the locations pointed to by
1413 * `z0Ptr', `z1Ptr', and `z2Ptr'.
1416 __sub96(uint a0, uint a1, uint a2,
1417 uint b0, uint b1, uint b2,
1423 uint borrow1 = uint(a2 < b2);
1425 uint borrow0 = uint(a1 < b1);
1427 z0 -= uint(z1 < borrow1);
1435 /* Returns an approximation to the 32-bit integer quotient obtained by dividing
1436 * `b' into the 64-bit value formed by concatenating `a0' and `a1'. The
1437 * divisor `b' must be at least 2^31. If q is the exact quotient truncated
1438 * toward zero, the approximation returned lies between q and q + 2 inclusive.
1439 * If the exact quotient q is larger than 32 bits, the maximum positive 32-bit
1440 * unsigned integer is returned.
1443 __estimateDiv64To32(uint a0, uint a1, uint b)
1456 z = (b0<<16 <= a0) ? 0xFFFF0000u : (a0 / b0)<<16;
1457 umulExtended(b, z, term0, term1);
1458 __sub64(a0, a1, term0, term1, rem0, rem1);
1459 while (int(rem0) < 0) {
1462 __add64(rem0, rem1, b0, b1, rem0, rem1);
1464 rem0 = (rem0<<16) | (rem1>>16);
1465 z |= (b0<<16 <= rem0) ? 0xFFFFu : rem0 / b0;
1470 __sqrtOddAdjustments(int index)
1510 __sqrtEvenAdjustments(int index)
1549 /* Returns an approximation to the square root of the 32-bit significand given
1550 * by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 of
1551 * `aExp' (the least significant bit) is 1, the integer returned approximates
1552 * 2^31*sqrt(`a'/2^31), where `a' is considered an integer. If bit 0 of `aExp'
1553 * is 0, the integer returned approximates 2^31*sqrt(`a'/2^30). In either
1554 * case, the approximation returned lies strictly within +/-2 of the exact
1558 __estimateSqrt32(int aExp, uint a)
1562 int index = int(a>>27 & 15u);
1563 if ((aExp & 1) != 0) {
1564 z = 0x4000u + (a>>17) - __sqrtOddAdjustments(index);
1565 z = ((a / z)<<14) + (z<<15);
1568 z = 0x8000u + (a>>17) - __sqrtEvenAdjustments(index);
1570 z = (0x20000u <= z) ? 0xFFFF8000u : (z<<15);
1572 return uint(int(a)>>1);
1574 return ((__estimateDiv64To32(a, 0u, z))>>1) + (z>>1);
1577 /* Returns the square root of the double-precision floating-point value `a'.
1578 * The operation is performed according to the IEEE Standard for Floating-Point
1582 __fsqrt64(uint64_t a)
1587 uint doubleZFrac0 = 0u;
1596 uint64_t default_nan = 0xFFFFFFFFFFFFFFFFUL;
1598 uint aFracLo = __extractFloat64FracLo(a);
1599 uint aFracHi = __extractFloat64FracHi(a);
1600 int aExp = __extractFloat64Exp(a);
1601 uint aSign = __extractFloat64Sign(a);
1602 if (aExp == 0x7FF) {
1603 if ((aFracHi | aFracLo) != 0u)
1604 return __propagateFloat64NaN(a, a);
1610 if ((uint(aExp) | aFracHi | aFracLo) == 0u)
1615 if ((aFracHi | aFracLo) == 0u)
1616 return __packFloat64(0u, 0, 0u, 0u);
1617 __normalizeFloat64Subnormal(aFracHi, aFracLo, aExp, aFracHi, aFracLo);
1619 int zExp = ((aExp - 0x3FF)>>1) + 0x3FE;
1620 aFracHi |= 0x00100000u;
1621 __shortShift64Left(aFracHi, aFracLo, 11, term0, term1);
1622 zFrac0 = (__estimateSqrt32(aExp, term0)>>1) + 1u;
1624 zFrac0 = 0x7FFFFFFFu;
1625 doubleZFrac0 = zFrac0 + zFrac0;
1626 __shortShift64Left(aFracHi, aFracLo, 9 - (aExp & 1), aFracHi, aFracLo);
1627 umulExtended(zFrac0, zFrac0, term0, term1);
1628 __sub64(aFracHi, aFracLo, term0, term1, rem0, rem1);
1629 while (int(rem0) < 0) {
1632 __add64(rem0, rem1, 0u, doubleZFrac0 | 1u, rem0, rem1);
1634 zFrac1 = __estimateDiv64To32(rem1, 0u, doubleZFrac0);
1635 if ((zFrac1 & 0x1FFu) <= 5u) {
1638 umulExtended(doubleZFrac0, zFrac1, term1, term2);
1639 __sub64(rem1, 0u, term1, term2, rem1, rem2);
1640 umulExtended(zFrac1, zFrac1, term2, term3);
1641 __sub96(rem1, rem2, 0u, 0u, term2, term3, rem1, rem2, rem3);
1642 while (int(rem1) < 0) {
1644 __shortShift64Left(0u, zFrac1, 1, term2, term3);
1646 term2 |= doubleZFrac0;
1647 __add96(rem1, rem2, rem3, 0u, term2, term3, rem1, rem2, rem3);
1649 zFrac1 |= uint((rem1 | rem2 | rem3) != 0u);
1651 __shift64ExtraRightJamming(zFrac0, zFrac1, 0u, 10, zFrac0, zFrac1, zFrac2);
1652 return __roundAndPackFloat64(0u, zExp, zFrac0, zFrac1, zFrac2);
1656 __ftrunc64(uint64_t __a)
1658 uvec2 a = unpackUint2x32(__a);
1659 int aExp = __extractFloat64Exp(__a);
1663 int unbiasedExp = aExp - 1023;
1664 int fracBits = 52 - unbiasedExp;
1665 uint maskLo = mix(~0u << fracBits, 0u, fracBits >= 32);
1666 uint maskHi = mix(~0u << (fracBits - 32), ~0u, fracBits < 33);
1670 zLo = mix(zLo, 0u, unbiasedExp < 0);
1671 zHi = mix(zHi, 0u, unbiasedExp < 0);
1672 zLo = mix(zLo, a.x, unbiasedExp > 52);
1673 zHi = mix(zHi, a.y, unbiasedExp > 52);
1674 return packUint2x32(uvec2(zLo, zHi));
1678 __ffloor64(uint64_t a)
1680 bool is_positive = __fge64(a, 0ul);
1681 uint64_t tr = __ftrunc64(a);
1683 if (is_positive || __feq64(tr, a)) {
1686 return __fadd64(tr, 0xbff0000000000000ul /* -1.0 */);
1691 __fround64(uint64_t __a)
1693 uvec2 a = unpackUint2x32(__a);
1694 int unbiasedExp = __extractFloat64Exp(__a) - 1023;
1698 if (unbiasedExp < 20) {
1699 if (unbiasedExp < 0) {
1700 if ((aHi & 0x80000000u) != 0u && aLo == 0u) {
1704 if ((a.y & 0x000FFFFFu) == 0u && a.x == 0u) {
1706 return packUint2x32(uvec2(aLo, aHi));
1708 aHi = mix(aHi, (aHi | 0x3FF00000u), unbiasedExp == -1);
1711 uint maskExp = 0x000FFFFFu >> unbiasedExp;
1712 uint lastBit = maskExp + 1;
1713 aHi += 0x00080000u >> unbiasedExp;
1714 if ((aHi & maskExp) == 0u)
1719 } else if (unbiasedExp > 51 || unbiasedExp == 1024) {
1722 uint maskExp = 0xFFFFFFFFu >> (unbiasedExp - 20);
1723 if ((aLo & maskExp) == 0u)
1725 uint tmp = aLo + (1u << (51 - unbiasedExp));
1732 return packUint2x32(uvec2(aLo, aHi));
1736 __fmin64(uint64_t a, uint64_t b)
1738 if (__is_nan(a)) return b;
1739 if (__is_nan(b)) return a;
1741 if (__flt64_nonnan(a, b)) return a;
1746 __fmax64(uint64_t a, uint64_t b)
1748 if (__is_nan(a)) return b;
1749 if (__is_nan(b)) return a;
1751 if (__flt64_nonnan(a, b)) return b;
1756 __ffract64(uint64_t a)
1758 return __fadd64(a, __fneg64(__ffloor64(a)));