2 * The implementations contained in this file are heavily based on the
3 * implementations found in the Berkeley SoftFloat library. As such, they are
4 * licensed under the same 3-clause BSD license:
6 * License for Berkeley SoftFloat Release 3e
11 * The following applies to the whole of SoftFloat Release 3e as well as to
12 * each source file individually.
14 * Copyright 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of the
15 * University of California. All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are met:
20 * 1. Redistributions of source code must retain the above copyright notice,
21 * this list of conditions, and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions, and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
27 * 3. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
32 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
34 * DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
35 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
40 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #extension GL_ARB_gpu_shader_int64 : enable
45 #extension GL_ARB_shader_bit_encoding : enable
46 #extension GL_EXT_shader_integer_mix : enable
47 #extension GL_MESA_shader_integer_functions : enable
51 /* Software IEEE floating-point rounding mode.
52 * GLSL spec section "4.7.1 Range and Precision":
53 * The rounding mode cannot be set and is undefined.
54 * But here, we are able to define the rounding mode at the compilation time.
56 #define FLOAT_ROUND_NEAREST_EVEN 0
57 #define FLOAT_ROUND_TO_ZERO 1
58 #define FLOAT_ROUND_DOWN 2
59 #define FLOAT_ROUND_UP 3
60 #define FLOAT_ROUNDING_MODE FLOAT_ROUND_NEAREST_EVEN
62 /* Absolute value of a Float64 :
66 __fabs64(uint64_t __a)
68 uvec2 a = unpackUint2x32(__a);
70 return packUint2x32(a);
73 /* Returns 1 if the double-precision floating-point value `a' is a NaN;
74 * otherwise returns 0.
77 __is_nan(uint64_t __a)
79 uvec2 a = unpackUint2x32(__a);
80 return (0xFFE00000u <= (a.y<<1)) &&
81 ((a.x != 0u) || ((a.y & 0x000FFFFFu) != 0u));
84 /* Negate value of a Float64 :
88 __fneg64(uint64_t __a)
90 uvec2 a = unpackUint2x32(__a);
92 return packUint2x32(a);
96 __fsign64(uint64_t __a)
98 uvec2 a = unpackUint2x32(__a);
101 retval.y = mix((a.y & 0x80000000u) | 0x3FF00000u, 0u, (a.y << 1 | a.x) == 0u);
102 return packUint2x32(retval);
105 /* Returns the fraction bits of the double-precision floating-point value `a'.*/
107 __extractFloat64FracLo(uint64_t a)
109 return unpackUint2x32(a).x;
113 __extractFloat64FracHi(uint64_t a)
115 return unpackUint2x32(a).y & 0x000FFFFFu;
118 /* Returns the exponent bits of the double-precision floating-point value `a'.*/
120 __extractFloat64Exp(uint64_t __a)
122 uvec2 a = unpackUint2x32(__a);
123 return int((a.y>>20) & 0x7FFu);
127 __feq64_nonnan(uint64_t __a, uint64_t __b)
129 uvec2 a = unpackUint2x32(__a);
130 uvec2 b = unpackUint2x32(__b);
131 return (a.x == b.x) &&
132 ((a.y == b.y) || ((a.x == 0u) && (((a.y | b.y)<<1) == 0u)));
135 /* Returns true if the double-precision floating-point value `a' is equal to the
136 * corresponding value `b', and false otherwise. The comparison is performed
137 * according to the IEEE Standard for Floating-Point Arithmetic.
140 __feq64(uint64_t a, uint64_t b)
142 if (__is_nan(a) || __is_nan(b))
145 return __feq64_nonnan(a, b);
148 /* Returns true if the double-precision floating-point value `a' is not equal
149 * to the corresponding value `b', and false otherwise. The comparison is
150 * performed according to the IEEE Standard for Floating-Point Arithmetic.
153 __fne64(uint64_t a, uint64_t b)
155 if (__is_nan(a) || __is_nan(b))
158 return !__feq64_nonnan(a, b);
161 /* Returns the sign bit of the double-precision floating-point value `a'.*/
163 __extractFloat64Sign(uint64_t a)
165 return unpackUint2x32(a).y & 0x80000000u;
168 /* Returns true if the signed 64-bit value formed by concatenating `a0' and
169 * `a1' is less than the signed 64-bit value formed by concatenating `b0' and
170 * `b1'. Otherwise, returns false.
173 ilt64(uint a0, uint a1, uint b0, uint b1)
175 return (int(a0) < int(b0)) || ((a0 == b0) && (a1 < b1));
179 __flt64_nonnan(uint64_t __a, uint64_t __b)
181 uvec2 a = unpackUint2x32(__a);
182 uvec2 b = unpackUint2x32(__b);
184 /* IEEE 754 floating point numbers are specifically designed so that, with
185 * two exceptions, values can be compared by bit-casting to signed integers
186 * with the same number of bits.
188 * From https://en.wikipedia.org/wiki/IEEE_754-1985#Comparing_floating-point_numbers:
190 * When comparing as 2's-complement integers: If the sign bits differ,
191 * the negative number precedes the positive number, so 2's complement
192 * gives the correct result (except that negative zero and positive zero
193 * should be considered equal). If both values are positive, the 2's
194 * complement comparison again gives the correct result. Otherwise (two
195 * negative numbers), the correct FP ordering is the opposite of the 2's
196 * complement ordering.
198 * The logic implied by the above quotation is:
200 * !both_are_zero(a, b) && (both_negative(a, b) ? a > b : a < b)
202 * This is equivalent to
204 * fne(a, b) && (both_negative(a, b) ? a >= b : a < b)
206 * fne(a, b) && (both_negative(a, b) ? !(a < b) : a < b)
208 * fne(a, b) && ((both_negative(a, b) && !(a < b)) ||
209 * (!both_negative(a, b) && (a < b)))
211 * (A!|B)&(A|!B) is (A xor B) which is implemented here using !=.
213 * fne(a, b) && (both_negative(a, b) != (a < b))
215 bool lt = ilt64(a.y, a.x, b.y, b.x);
216 bool both_negative = (a.y & b.y & 0x80000000u) != 0;
218 return !__feq64_nonnan(__a, __b) && (lt != both_negative);
221 /* Returns true if the double-precision floating-point value `a' is less than
222 * the corresponding value `b', and false otherwise. The comparison is performed
223 * according to the IEEE Standard for Floating-Point Arithmetic.
226 __flt64(uint64_t a, uint64_t b)
228 /* This weird layout matters. Doing the "obvious" thing results in extra
229 * flow control being inserted to implement the short-circuit evaluation
230 * rules. Flow control is bad!
232 bool x = !__is_nan(a);
233 bool y = !__is_nan(b);
234 bool z = __flt64_nonnan(a, b);
236 return (x && y && z);
239 /* Returns true if the double-precision floating-point value `a' is greater
240 * than or equal to * the corresponding value `b', and false otherwise. The
241 * comparison is performed * according to the IEEE Standard for Floating-Point
245 __fge64(uint64_t a, uint64_t b)
247 /* This weird layout matters. Doing the "obvious" thing results in extra
248 * flow control being inserted to implement the short-circuit evaluation
249 * rules. Flow control is bad!
251 bool x = !__is_nan(a);
252 bool y = !__is_nan(b);
253 bool z = !__flt64_nonnan(a, b);
255 return (x && y && z);
259 __fsat64(uint64_t __a)
261 uvec2 a = unpackUint2x32(__a);
263 /* fsat(NaN) should be zero. */
264 if (__is_nan(__a) || int(a.y) < 0)
267 if (!__flt64_nonnan(__a, 0x3FF0000000000000ul /* 1.0 */))
268 return 0x3FF0000000000000ul;
273 /* Adds the 64-bit value formed by concatenating `a0' and `a1' to the 64-bit
274 * value formed by concatenating `b0' and `b1'. Addition is modulo 2^64, so
275 * any carry out is lost. The result is broken into two 32-bit pieces which
276 * are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
279 __add64(uint a0, uint a1, uint b0, uint b1,
285 z0Ptr = a0 + b0 + uint(z1 < a1);
289 /* Subtracts the 64-bit value formed by concatenating `b0' and `b1' from the
290 * 64-bit value formed by concatenating `a0' and `a1'. Subtraction is modulo
291 * 2^64, so any borrow out (carry out) is lost. The result is broken into two
292 * 32-bit pieces which are stored at the locations pointed to by `z0Ptr' and
296 __sub64(uint a0, uint a1, uint b0, uint b1,
301 z0Ptr = a0 - b0 - uint(a1 < b1);
304 /* Shifts the 64-bit value formed by concatenating `a0' and `a1' right by the
305 * number of bits given in `count'. If any nonzero bits are shifted off, they
306 * are "jammed" into the least significant bit of the result by setting the
307 * least significant bit to 1. The value of `count' can be arbitrarily large;
308 * in particular, if `count' is greater than 64, the result will be either 0
309 * or 1, depending on whether the concatenation of `a0' and `a1' is zero or
310 * nonzero. The result is broken into two 32-bit pieces which are stored at
311 * the locations pointed to by `z0Ptr' and `z1Ptr'.
314 __shift64RightJamming(uint a0,
322 int negCount = (-count) & 31;
324 z0 = mix(0u, a0, count == 0);
325 z0 = mix(z0, (a0 >> count), count < 32);
327 z1 = uint((a0 | a1) != 0u); /* count >= 64 */
328 uint z1_lt64 = (a0>>(count & 31)) | uint(((a0<<negCount) | a1) != 0u);
329 z1 = mix(z1, z1_lt64, count < 64);
330 z1 = mix(z1, (a0 | uint(a1 != 0u)), count == 32);
331 uint z1_lt32 = (a0<<negCount) | (a1>>count) | uint ((a1<<negCount) != 0u);
332 z1 = mix(z1, z1_lt32, count < 32);
333 z1 = mix(z1, a1, count == 0);
338 /* Shifts the 96-bit value formed by concatenating `a0', `a1', and `a2' right
339 * by 32 _plus_ the number of bits given in `count'. The shifted result is
340 * at most 64 nonzero bits; these are broken into two 32-bit pieces which are
341 * stored at the locations pointed to by `z0Ptr' and `z1Ptr'. The bits shifted
342 * off form a third 32-bit result as follows: The _last_ bit shifted off is
343 * the most-significant bit of the extra result, and the other 31 bits of the
344 * extra result are all zero if and only if _all_but_the_last_ bits shifted off
345 * were all zero. This extra result is stored in the location pointed to by
346 * `z2Ptr'. The value of `count' can be arbitrarily large.
347 * (This routine makes more sense if `a0', `a1', and `a2' are considered
348 * to form a fixed-point value with binary point between `a1' and `a2'. This
349 * fixed-point value is shifted right by the number of bits given in `count',
350 * and the integer part of the result is returned at the locations pointed to
351 * by `z0Ptr' and `z1Ptr'. The fractional part of the result may be slightly
352 * corrupted as described above, and is returned at the location pointed to by
356 __shift64ExtraRightJamming(uint a0, uint a1, uint a2,
365 int negCount = (-count) & 31;
367 z2 = mix(uint(a0 != 0u), a0, count == 64);
368 z2 = mix(z2, a0 << negCount, count < 64);
369 z2 = mix(z2, a1 << negCount, count < 32);
371 z1 = mix(0u, (a0 >> (count & 31)), count < 64);
372 z1 = mix(z1, (a0<<negCount) | (a1>>count), count < 32);
374 a2 = mix(a2 | a1, a2, count < 32);
375 z0 = mix(z0, a0 >> count, count < 32);
376 z2 |= uint(a2 != 0u);
378 z0 = mix(z0, 0u, (count == 32));
379 z1 = mix(z1, a0, (count == 32));
380 z2 = mix(z2, a1, (count == 32));
381 z0 = mix(z0, a0, (count == 0));
382 z1 = mix(z1, a1, (count == 0));
383 z2 = mix(z2, a2, (count == 0));
389 /* Shifts the 64-bit value formed by concatenating `a0' and `a1' left by the
390 * number of bits given in `count'. Any bits shifted off are lost. The value
391 * of `count' must be less than 32. The result is broken into two 32-bit
392 * pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
395 __shortShift64Left(uint a0, uint a1,
401 z0Ptr = mix((a0 << count | (a1 >> ((-count) & 31))), a0, count == 0);
404 /* Packs the sign `zSign', the exponent `zExp', and the significand formed by
405 * the concatenation of `zFrac0' and `zFrac1' into a double-precision floating-
406 * point value, returning the result. After being shifted into the proper
407 * positions, the three fields `zSign', `zExp', and `zFrac0' are simply added
408 * together to form the most significant 32 bits of the result. This means
409 * that any integer portion of `zFrac0' will be added into the exponent. Since
410 * a properly normalized significand will have an integer portion equal to 1,
411 * the `zExp' input should be 1 less than the desired result exponent whenever
412 * `zFrac0' and `zFrac1' concatenated form a complete, normalized significand.
415 __packFloat64(uint zSign, int zExp, uint zFrac0, uint zFrac1)
419 z.y = zSign + (uint(zExp) << 20) + zFrac0;
421 return packUint2x32(z);
424 /* Takes an abstract floating-point value having sign `zSign', exponent `zExp',
425 * and extended significand formed by the concatenation of `zFrac0', `zFrac1',
426 * and `zFrac2', and returns the proper double-precision floating-point value
427 * corresponding to the abstract input. Ordinarily, the abstract value is
428 * simply rounded and packed into the double-precision format, with the inexact
429 * exception raised if the abstract input cannot be represented exactly.
430 * However, if the abstract value is too large, the overflow and inexact
431 * exceptions are raised and an infinity or maximal finite value is returned.
432 * If the abstract value is too small, the input value is rounded to a
433 * subnormal number, and the underflow and inexact exceptions are raised if the
434 * abstract input cannot be represented exactly as a subnormal double-precision
435 * floating-point number.
436 * The input significand must be normalized or smaller. If the input
437 * significand is not normalized, `zExp' must be 0; in that case, the result
438 * returned is a subnormal number, and it must not require rounding. In the
439 * usual case that the input significand is normalized, `zExp' must be 1 less
440 * than the "true" floating-point exponent. The handling of underflow and
441 * overflow follows the IEEE Standard for Floating-Point Arithmetic.
444 __roundAndPackFloat64(uint zSign,
450 bool roundNearestEven;
453 roundNearestEven = FLOAT_ROUNDING_MODE == FLOAT_ROUND_NEAREST_EVEN;
454 increment = int(zFrac2) < 0;
455 if (!roundNearestEven) {
456 if (FLOAT_ROUNDING_MODE == FLOAT_ROUND_TO_ZERO) {
460 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN) &&
463 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP) &&
469 if ((0x7FD < zExp) ||
471 (0x001FFFFFu == zFrac0 && 0xFFFFFFFFu == zFrac1) &&
473 if ((FLOAT_ROUNDING_MODE == FLOAT_ROUND_TO_ZERO) ||
474 ((zSign != 0u) && (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP)) ||
475 ((zSign == 0u) && (FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN))) {
476 return __packFloat64(zSign, 0x7FE, 0x000FFFFFu, 0xFFFFFFFFu);
478 return __packFloat64(zSign, 0x7FF, 0u, 0u);
481 __shift64ExtraRightJamming(
482 zFrac0, zFrac1, zFrac2, -zExp, zFrac0, zFrac1, zFrac2);
484 if (roundNearestEven) {
485 increment = zFrac2 < 0u;
488 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN) &&
491 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP) &&
498 __add64(zFrac0, zFrac1, 0u, 1u, zFrac0, zFrac1);
499 zFrac1 &= ~((zFrac2 + uint(zFrac2 == 0u)) & uint(roundNearestEven));
501 zExp = mix(zExp, 0, (zFrac0 | zFrac1) == 0u);
503 return __packFloat64(zSign, zExp, zFrac0, zFrac1);
507 __roundAndPackUInt64(uint zSign, uint zFrac0, uint zFrac1, uint zFrac2)
509 bool roundNearestEven;
511 uint64_t default_nan = 0xFFFFFFFFFFFFFFFFUL;
513 roundNearestEven = FLOAT_ROUNDING_MODE == FLOAT_ROUND_NEAREST_EVEN;
515 if (zFrac2 >= 0x80000000u)
518 if (!roundNearestEven) {
520 if ((FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN) && (zFrac2 != 0u)) {
524 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP) &&
530 __add64(zFrac0, zFrac1, 0u, 1u, zFrac0, zFrac1);
531 if ((zFrac0 | zFrac1) != 0u)
532 zFrac1 &= ~(1u) + uint(zFrac2 == 0u) & uint(roundNearestEven);
534 return mix(packUint2x32(uvec2(zFrac1, zFrac0)), default_nan,
535 (zSign != 0u && (zFrac0 | zFrac1) != 0u));
539 __roundAndPackInt64(uint zSign, uint zFrac0, uint zFrac1, uint zFrac2)
541 bool roundNearestEven;
543 int64_t default_NegNaN = -0x7FFFFFFFFFFFFFFEL;
544 int64_t default_PosNaN = 0xFFFFFFFFFFFFFFFFL;
546 roundNearestEven = FLOAT_ROUNDING_MODE == FLOAT_ROUND_NEAREST_EVEN;
548 if (zFrac2 >= 0x80000000u)
551 if (!roundNearestEven) {
553 increment = ((FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN) &&
556 increment = (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP) &&
562 __add64(zFrac0, zFrac1, 0u, 1u, zFrac0, zFrac1);
563 if ((zFrac0 | zFrac1) != 0u)
564 zFrac1 &= ~(1u) + uint(zFrac2 == 0u) & uint(roundNearestEven);
567 int64_t absZ = mix(int64_t(packUint2x32(uvec2(zFrac1, zFrac0))),
568 -int64_t(packUint2x32(uvec2(zFrac1, zFrac0))),
570 int64_t nan = mix(default_PosNaN, default_NegNaN, zSign != 0u);
571 return mix(absZ, nan, ((zSign != 0u) != (absZ < 0)) && bool(absZ));
574 /* Returns the number of leading 0 bits before the most-significant 1 bit of
575 * `a'. If `a' is zero, 32 is returned.
578 __countLeadingZeros32(uint a)
580 return 31 - findMSB(a);
583 /* Takes an abstract floating-point value having sign `zSign', exponent `zExp',
584 * and significand formed by the concatenation of `zSig0' and `zSig1', and
585 * returns the proper double-precision floating-point value corresponding
586 * to the abstract input. This routine is just like `__roundAndPackFloat64'
587 * except that the input significand has fewer bits and does not have to be
588 * normalized. In all cases, `zExp' must be 1 less than the "true" floating-
592 __normalizeRoundAndPackFloat64(uint zSign,
606 shiftCount = __countLeadingZeros32(zFrac0) - 11;
607 if (0 <= shiftCount) {
609 __shortShift64Left(zFrac0, zFrac1, shiftCount, zFrac0, zFrac1);
611 __shift64ExtraRightJamming(
612 zFrac0, zFrac1, 0u, -shiftCount, zFrac0, zFrac1, zFrac2);
615 return __roundAndPackFloat64(zSign, zExp, zFrac0, zFrac1, zFrac2);
618 /* Takes two double-precision floating-point values `a' and `b', one of which
619 * is a NaN, and returns the appropriate NaN result.
622 __propagateFloat64NaN(uint64_t __a, uint64_t __b)
624 bool aIsNaN = __is_nan(__a);
625 bool bIsNaN = __is_nan(__b);
626 uvec2 a = unpackUint2x32(__a);
627 uvec2 b = unpackUint2x32(__b);
631 return packUint2x32(mix(b, mix(a, b, bvec2(bIsNaN, bIsNaN)), bvec2(aIsNaN, aIsNaN)));
634 /* Returns the result of adding the double-precision floating-point values
635 * `a' and `b'. The operation is performed according to the IEEE Standard for
636 * Floating-Point Arithmetic.
639 __fadd64(uint64_t a, uint64_t b)
641 uint aSign = __extractFloat64Sign(a);
642 uint bSign = __extractFloat64Sign(b);
643 uint aFracLo = __extractFloat64FracLo(a);
644 uint aFracHi = __extractFloat64FracHi(a);
645 uint bFracLo = __extractFloat64FracLo(b);
646 uint bFracHi = __extractFloat64FracHi(b);
647 int aExp = __extractFloat64Exp(a);
648 int bExp = __extractFloat64Exp(b);
651 int expDiff = aExp - bExp;
652 if (aSign == bSign) {
655 bool orig_exp_diff_is_zero = (expDiff == 0);
657 if (orig_exp_diff_is_zero) {
659 bool propagate = (aFracHi | aFracLo | bFracHi | bFracLo) != 0u;
660 return mix(a, __propagateFloat64NaN(a, b), propagate);
662 __add64(aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1);
664 return __packFloat64(aSign, 0, zFrac0, zFrac1);
666 zFrac0 |= 0x00200000u;
668 __shift64ExtraRightJamming(
669 zFrac0, zFrac1, zFrac2, 1, zFrac0, zFrac1, zFrac2);
670 } else if (0 < expDiff) {
672 bool propagate = (aFracHi | aFracLo) != 0u;
673 return mix(a, __propagateFloat64NaN(a, b), propagate);
676 expDiff = mix(expDiff, expDiff - 1, bExp == 0);
677 bFracHi = mix(bFracHi | 0x00100000u, bFracHi, bExp == 0);
678 __shift64ExtraRightJamming(
679 bFracHi, bFracLo, 0u, expDiff, bFracHi, bFracLo, zFrac2);
681 } else if (expDiff < 0) {
683 bool propagate = (bFracHi | bFracLo) != 0u;
684 return mix(__packFloat64(aSign, 0x7ff, 0u, 0u), __propagateFloat64NaN(a, b), propagate);
686 expDiff = mix(expDiff, expDiff + 1, aExp == 0);
687 aFracHi = mix(aFracHi | 0x00100000u, aFracHi, aExp == 0);
688 __shift64ExtraRightJamming(
689 aFracHi, aFracLo, 0u, - expDiff, aFracHi, aFracLo, zFrac2);
692 if (!orig_exp_diff_is_zero) {
693 aFracHi |= 0x00100000u;
694 __add64(aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1);
696 if (!(zFrac0 < 0x00200000u)) {
697 __shift64ExtraRightJamming(zFrac0, zFrac1, zFrac2, 1, zFrac0, zFrac1, zFrac2);
701 return __roundAndPackFloat64(aSign, zExp, zFrac0, zFrac1, zFrac2);
706 __shortShift64Left(aFracHi, aFracLo, 10, aFracHi, aFracLo);
707 __shortShift64Left(bFracHi, bFracLo, 10, bFracHi, bFracLo);
710 bool propagate = (aFracHi | aFracLo) != 0u;
711 return mix(a, __propagateFloat64NaN(a, b), propagate);
713 expDiff = mix(expDiff, expDiff - 1, bExp == 0);
714 bFracHi = mix(bFracHi | 0x40000000u, bFracHi, bExp == 0);
715 __shift64RightJamming(bFracHi, bFracLo, expDiff, bFracHi, bFracLo);
716 aFracHi |= 0x40000000u;
717 __sub64(aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1);
720 return __normalizeRoundAndPackFloat64(aSign, zExp - 10, zFrac0, zFrac1);
724 bool propagate = (bFracHi | bFracLo) != 0u;
725 return mix(__packFloat64(aSign ^ 0x80000000u, 0x7ff, 0u, 0u), __propagateFloat64NaN(a, b), propagate);
727 expDiff = mix(expDiff, expDiff + 1, aExp == 0);
728 aFracHi = mix(aFracHi | 0x40000000u, aFracHi, aExp == 0);
729 __shift64RightJamming(aFracHi, aFracLo, - expDiff, aFracHi, aFracLo);
730 bFracHi |= 0x40000000u;
731 __sub64(bFracHi, bFracLo, aFracHi, aFracLo, zFrac0, zFrac1);
733 aSign ^= 0x80000000u;
735 return __normalizeRoundAndPackFloat64(aSign, zExp - 10, zFrac0, zFrac1);
738 bool propagate = (aFracHi | aFracLo | bFracHi | bFracLo) != 0u;
739 return mix(0xFFFFFFFFFFFFFFFFUL, __propagateFloat64NaN(a, b), propagate);
741 bExp = mix(bExp, 1, aExp == 0);
742 aExp = mix(aExp, 1, aExp == 0);
743 bool zexp_normal = false;
745 if (bFracHi < aFracHi) {
746 __sub64(aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1);
749 else if (aFracHi < bFracHi) {
750 __sub64(bFracHi, bFracLo, aFracHi, aFracLo, zFrac0, zFrac1);
754 else if (bFracLo < aFracLo) {
755 __sub64(aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1);
758 else if (aFracLo < bFracLo) {
759 __sub64(bFracHi, bFracLo, aFracHi, aFracLo, zFrac0, zFrac1);
763 zExp = mix(bExp, aExp, blta);
764 aSign = mix(aSign ^ 0x80000000u, aSign, blta);
765 uint64_t retval_0 = __packFloat64(uint(FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN) << 31, 0, 0u, 0u);
766 uint64_t retval_1 = __normalizeRoundAndPackFloat64(aSign, zExp - 11, zFrac0, zFrac1);
767 return mix(retval_0, retval_1, zexp_normal);
771 /* Multiplies the 64-bit value formed by concatenating `a0' and `a1' to the
772 * 64-bit value formed by concatenating `b0' and `b1' to obtain a 128-bit
773 * product. The product is broken into four 32-bit pieces which are stored at
774 * the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.
777 __mul64To128(uint a0, uint a1, uint b0, uint b1,
790 umulExtended(a1, b1, z2, z3);
791 umulExtended(a1, b0, z1, more2);
792 __add64(z1, more2, 0u, z2, z1, z2);
793 umulExtended(a0, b0, z0, more1);
794 __add64(z0, more1, 0u, z1, z0, z1);
795 umulExtended(a0, b1, more1, more2);
796 __add64(more1, more2, 0u, z2, more1, z2);
797 __add64(z0, z1, 0u, more1, z0, z1);
804 /* Normalizes the subnormal double-precision floating-point value represented
805 * by the denormalized significand formed by the concatenation of `aFrac0' and
806 * `aFrac1'. The normalized exponent is stored at the location pointed to by
807 * `zExpPtr'. The most significant 21 bits of the normalized significand are
808 * stored at the location pointed to by `zFrac0Ptr', and the least significant
809 * 32 bits of the normalized significand are stored at the location pointed to
813 __normalizeFloat64Subnormal(uint aFrac0, uint aFrac1,
819 uint temp_zfrac0, temp_zfrac1;
820 shiftCount = __countLeadingZeros32(mix(aFrac0, aFrac1, aFrac0 == 0u)) - 11;
821 zExpPtr = mix(1 - shiftCount, -shiftCount - 31, aFrac0 == 0u);
823 temp_zfrac0 = mix(aFrac1<<shiftCount, aFrac1>>(-shiftCount), shiftCount < 0);
824 temp_zfrac1 = mix(0u, aFrac1<<(shiftCount & 31), shiftCount < 0);
826 __shortShift64Left(aFrac0, aFrac1, shiftCount, zFrac0Ptr, zFrac1Ptr);
828 zFrac0Ptr = mix(zFrac0Ptr, temp_zfrac0, aFrac0 == 0);
829 zFrac1Ptr = mix(zFrac1Ptr, temp_zfrac1, aFrac0 == 0);
832 /* Returns the result of multiplying the double-precision floating-point values
833 * `a' and `b'. The operation is performed according to the IEEE Standard for
834 * Floating-Point Arithmetic.
837 __fmul64(uint64_t a, uint64_t b)
845 uint aFracLo = __extractFloat64FracLo(a);
846 uint aFracHi = __extractFloat64FracHi(a);
847 uint bFracLo = __extractFloat64FracLo(b);
848 uint bFracHi = __extractFloat64FracHi(b);
849 int aExp = __extractFloat64Exp(a);
850 uint aSign = __extractFloat64Sign(a);
851 int bExp = __extractFloat64Exp(b);
852 uint bSign = __extractFloat64Sign(b);
853 uint zSign = aSign ^ bSign;
855 if (((aFracHi | aFracLo) != 0u) ||
856 ((bExp == 0x7FF) && ((bFracHi | bFracLo) != 0u))) {
857 return __propagateFloat64NaN(a, b);
859 if ((uint(bExp) | bFracHi | bFracLo) == 0u)
860 return 0xFFFFFFFFFFFFFFFFUL;
861 return __packFloat64(zSign, 0x7FF, 0u, 0u);
864 if ((bFracHi | bFracLo) != 0u)
865 return __propagateFloat64NaN(a, b);
866 if ((uint(aExp) | aFracHi | aFracLo) == 0u)
867 return 0xFFFFFFFFFFFFFFFFUL;
868 return __packFloat64(zSign, 0x7FF, 0u, 0u);
871 if ((aFracHi | aFracLo) == 0u)
872 return __packFloat64(zSign, 0, 0u, 0u);
873 __normalizeFloat64Subnormal(aFracHi, aFracLo, aExp, aFracHi, aFracLo);
876 if ((bFracHi | bFracLo) == 0u)
877 return __packFloat64(zSign, 0, 0u, 0u);
878 __normalizeFloat64Subnormal(bFracHi, bFracLo, bExp, bFracHi, bFracLo);
880 zExp = aExp + bExp - 0x400;
881 aFracHi |= 0x00100000u;
882 __shortShift64Left(bFracHi, bFracLo, 12, bFracHi, bFracLo);
884 aFracHi, aFracLo, bFracHi, bFracLo, zFrac0, zFrac1, zFrac2, zFrac3);
885 __add64(zFrac0, zFrac1, aFracHi, aFracLo, zFrac0, zFrac1);
886 zFrac2 |= uint(zFrac3 != 0u);
887 if (0x00200000u <= zFrac0) {
888 __shift64ExtraRightJamming(
889 zFrac0, zFrac1, zFrac2, 1, zFrac0, zFrac1, zFrac2);
892 return __roundAndPackFloat64(zSign, zExp, zFrac0, zFrac1, zFrac2);
896 __ffma64(uint64_t a, uint64_t b, uint64_t c)
898 return __fadd64(__fmul64(a, b), c);
901 /* Shifts the 64-bit value formed by concatenating `a0' and `a1' right by the
902 * number of bits given in `count'. Any bits shifted off are lost. The value
903 * of `count' can be arbitrarily large; in particular, if `count' is greater
904 * than 64, the result will be 0. The result is broken into two 32-bit pieces
905 * which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
908 __shift64Right(uint a0, uint a1,
915 int negCount = (-count) & 31;
918 z0 = mix(z0, (a0 >> count), count < 32);
919 z0 = mix(z0, a0, count == 0);
921 z1 = mix(0u, (a0 >> (count & 31)), count < 64);
922 z1 = mix(z1, (a0<<negCount) | (a1>>count), count < 32);
923 z1 = mix(z1, a0, count == 0);
929 /* Returns the result of converting the double-precision floating-point value
930 * `a' to the unsigned integer format. The conversion is performed according
931 * to the IEEE Standard for Floating-Point Arithmetic.
934 __fp64_to_uint(uint64_t a)
936 uint aFracLo = __extractFloat64FracLo(a);
937 uint aFracHi = __extractFloat64FracHi(a);
938 int aExp = __extractFloat64Exp(a);
939 uint aSign = __extractFloat64Sign(a);
941 if ((aExp == 0x7FF) && ((aFracHi | aFracLo) != 0u))
944 aFracHi |= mix(0u, 0x00100000u, aExp != 0);
946 int shiftDist = 0x427 - aExp;
948 __shift64RightJamming(aFracHi, aFracLo, shiftDist, aFracHi, aFracLo);
950 if ((aFracHi & 0xFFFFF000u) != 0u)
951 return mix(~0u, 0u, aSign != 0u);
955 __shift64Right(aFracHi, aFracLo, 12, zero, z);
957 uint expt = mix(~0u, 0u, aSign != 0u);
959 return mix(z, expt, (aSign != 0u) && (z != 0u));
963 __uint_to_fp64(uint a)
968 int shiftDist = __countLeadingZeros32(a) + 21;
972 int negCount = (- shiftDist) & 31;
974 aHigh = mix(0u, a<< shiftDist - 32, shiftDist < 64);
976 aHigh = mix(aHigh, 0u, shiftDist == 0);
977 aLow = mix(aLow, a, shiftDist ==0);
978 aHigh = mix(aHigh, a >> negCount, shiftDist < 32);
979 aLow = mix(aLow, a << shiftDist, shiftDist < 32);
981 return __packFloat64(0u, 0x432 - shiftDist, aHigh, aLow);
985 __uint64_to_fp64(uint64_t a)
990 uvec2 aFrac = unpackUint2x32(a);
991 uint aFracLo = __extractFloat64FracLo(a);
992 uint aFracHi = __extractFloat64FracHi(a);
994 if ((aFracHi & 0x80000000u) != 0u) {
995 __shift64RightJamming(aFracHi, aFracLo, 1, aFracHi, aFracLo);
996 return __roundAndPackFloat64(0, 0x433, aFracHi, aFracLo, 0u);
998 return __normalizeRoundAndPackFloat64(0, 0x432, aFrac.y, aFrac.x);
1003 __fp64_to_uint64(uint64_t a)
1005 uint aFracLo = __extractFloat64FracLo(a);
1006 uint aFracHi = __extractFloat64FracHi(a);
1007 int aExp = __extractFloat64Exp(a);
1008 uint aSign = __extractFloat64Sign(a);
1010 uint64_t default_nan = 0xFFFFFFFFFFFFFFFFUL;
1012 aFracHi = mix(aFracHi, aFracHi | 0x00100000u, aExp != 0);
1013 int shiftCount = 0x433 - aExp;
1015 if ( shiftCount <= 0 ) {
1016 if (shiftCount < -11 && aExp == 0x7FF) {
1017 if ((aFracHi | aFracLo) != 0u)
1018 return __propagateFloat64NaN(a, a);
1019 return mix(default_nan, a, aSign == 0u);
1021 __shortShift64Left(aFracHi, aFracLo, -shiftCount, aFracHi, aFracLo);
1023 __shift64ExtraRightJamming(aFracHi, aFracLo, zFrac2, shiftCount,
1024 aFracHi, aFracLo, zFrac2);
1026 return __roundAndPackUInt64(aSign, aFracHi, aFracLo, zFrac2);
1030 __fp64_to_int64(uint64_t a)
1033 uint aFracLo = __extractFloat64FracLo(a);
1034 uint aFracHi = __extractFloat64FracHi(a);
1035 int aExp = __extractFloat64Exp(a);
1036 uint aSign = __extractFloat64Sign(a);
1037 int64_t default_NegNaN = -0x7FFFFFFFFFFFFFFEL;
1038 int64_t default_PosNaN = 0xFFFFFFFFFFFFFFFFL;
1040 aFracHi = mix(aFracHi, aFracHi | 0x00100000u, aExp != 0);
1041 int shiftCount = 0x433 - aExp;
1043 if (shiftCount <= 0) {
1044 if (shiftCount < -11 && aExp == 0x7FF) {
1045 if ((aFracHi | aFracLo) != 0u)
1046 return default_NegNaN;
1047 return mix(default_NegNaN, default_PosNaN, aSign == 0u);
1049 __shortShift64Left(aFracHi, aFracLo, -shiftCount, aFracHi, aFracLo);
1051 __shift64ExtraRightJamming(aFracHi, aFracLo, zFrac2, shiftCount,
1052 aFracHi, aFracLo, zFrac2);
1055 return __roundAndPackInt64(aSign, aFracHi, aFracLo, zFrac2);
1059 __fp32_to_uint64(float f)
1061 uint a = floatBitsToUint(f);
1062 uint aFrac = a & 0x007FFFFFu;
1063 int aExp = int((a>>23) & 0xFFu);
1064 uint aSign = a & 0x80000000u;
1068 uint64_t default_nan = 0xFFFFFFFFFFFFFFFFUL;
1069 int shiftCount = 0xBE - aExp;
1071 if (shiftCount <0) {
1076 aFrac = mix(aFrac, aFrac | 0x00800000u, aExp != 0);
1077 __shortShift64Left(aFrac, 0, 40, zFrac0, zFrac1);
1079 if (shiftCount != 0) {
1080 __shift64ExtraRightJamming(zFrac0, zFrac1, zFrac2, shiftCount,
1081 zFrac0, zFrac1, zFrac2);
1084 return __roundAndPackUInt64(aSign, zFrac0, zFrac1, zFrac2);
1088 __fp32_to_int64(float f)
1090 uint a = floatBitsToUint(f);
1091 uint aFrac = a & 0x007FFFFFu;
1092 int aExp = int((a>>23) & 0xFFu);
1093 uint aSign = a & 0x80000000u;
1097 int64_t default_NegNaN = -0x7FFFFFFFFFFFFFFEL;
1098 int64_t default_PosNaN = 0xFFFFFFFFFFFFFFFFL;
1099 int shiftCount = 0xBE - aExp;
1101 if (shiftCount <0) {
1102 if (aExp == 0xFF && aFrac != 0u)
1103 return default_NegNaN;
1104 return mix(default_NegNaN, default_PosNaN, aSign == 0u);
1107 aFrac = mix(aFrac, aFrac | 0x00800000u, aExp != 0);
1108 __shortShift64Left(aFrac, 0, 40, zFrac0, zFrac1);
1110 if (shiftCount != 0) {
1111 __shift64ExtraRightJamming(zFrac0, zFrac1, zFrac2, shiftCount,
1112 zFrac0, zFrac1, zFrac2);
1115 return __roundAndPackInt64(aSign, zFrac0, zFrac1, zFrac2);
1119 __int64_to_fp64(int64_t a)
1124 uint64_t absA = mix(uint64_t(a), uint64_t(-a), a < 0);
1125 uint aFracHi = __extractFloat64FracHi(absA);
1126 uvec2 aFrac = unpackUint2x32(absA);
1127 uint zSign = uint(unpackInt2x32(a).y) & 0x80000000u;
1129 if ((aFracHi & 0x80000000u) != 0u) {
1130 return mix(0ul, __packFloat64(0x80000000u, 0x434, 0u, 0u), a < 0);
1133 return __normalizeRoundAndPackFloat64(zSign, 0x432, aFrac.y, aFrac.x);
1136 /* Returns the result of converting the double-precision floating-point value
1137 * `a' to the 32-bit two's complement integer format. The conversion is
1138 * performed according to the IEEE Standard for Floating-Point Arithmetic---
1139 * which means in particular that the conversion is rounded according to the
1140 * current rounding mode. If `a' is a NaN, the largest positive integer is
1141 * returned. Otherwise, if the conversion overflows, the largest integer with
1142 * the same sign as `a' is returned.
1145 __fp64_to_int(uint64_t a)
1147 uint aFracLo = __extractFloat64FracLo(a);
1148 uint aFracHi = __extractFloat64FracHi(a);
1149 int aExp = __extractFloat64Exp(a);
1150 uint aSign = __extractFloat64Sign(a);
1153 uint aFracExtra = 0u;
1154 int shiftCount = aExp - 0x413;
1156 if (0 <= shiftCount) {
1158 if ((aExp == 0x7FF) && bool(aFracHi | aFracLo))
1160 return mix(0x7FFFFFFF, 0x80000000, aSign != 0u);
1162 __shortShift64Left(aFracHi | 0x00100000u, aFracLo, shiftCount, absZ, aFracExtra);
1167 aFracHi |= 0x00100000u;
1168 aFracExtra = ( aFracHi << (shiftCount & 31)) | aFracLo;
1169 absZ = aFracHi >> (- shiftCount);
1172 int z = mix(int(absZ), -int(absZ), aSign != 0u);
1173 int nan = mix(0x7FFFFFFF, 0x80000000, aSign != 0u);
1174 return mix(z, nan, ((aSign != 0u) != (z < 0)) && bool(z));
1177 /* Returns the result of converting the 32-bit two's complement integer `a'
1178 * to the double-precision floating-point format. The conversion is performed
1179 * according to the IEEE Standard for Floating-Point Arithmetic.
1182 __int_to_fp64(int a)
1187 return __packFloat64(0u, 0, 0u, 0u);
1188 uint zSign = uint(a) & 0x80000000u;
1189 uint absA = mix(uint(a), uint(-a), a < 0);
1190 int shiftCount = __countLeadingZeros32(absA) - 11;
1191 if (0 <= shiftCount) {
1192 zFrac0 = absA << shiftCount;
1195 __shift64Right(absA, 0u, -shiftCount, zFrac0, zFrac1);
1197 return __packFloat64(zSign, 0x412 - shiftCount, zFrac0, zFrac1);
1201 __fp64_to_bool(uint64_t a)
1203 return !__feq64_nonnan(__fabs64(a), 0ul);
1207 __bool_to_fp64(bool a)
1209 return packUint2x32(uvec2(0x00000000u, uint(-int(a) & 0x3ff00000)));
1212 /* Packs the sign `zSign', exponent `zExp', and significand `zFrac' into a
1213 * single-precision floating-point value, returning the result. After being
1214 * shifted into the proper positions, the three fields are simply added
1215 * together to form the result. This means that any integer portion of `zSig'
1216 * will be added into the exponent. Since a properly normalized significand
1217 * will have an integer portion equal to 1, the `zExp' input should be 1 less
1218 * than the desired result exponent whenever `zFrac' is a complete, normalized
1222 __packFloat32(uint zSign, int zExp, uint zFrac)
1224 return uintBitsToFloat(zSign + (uint(zExp)<<23) + zFrac);
1227 /* Takes an abstract floating-point value having sign `zSign', exponent `zExp',
1228 * and significand `zFrac', and returns the proper single-precision floating-
1229 * point value corresponding to the abstract input. Ordinarily, the abstract
1230 * value is simply rounded and packed into the single-precision format, with
1231 * the inexact exception raised if the abstract input cannot be represented
1232 * exactly. However, if the abstract value is too large, the overflow and
1233 * inexact exceptions are raised and an infinity or maximal finite value is
1234 * returned. If the abstract value is too small, the input value is rounded to
1235 * a subnormal number, and the underflow and inexact exceptions are raised if
1236 * the abstract input cannot be represented exactly as a subnormal single-
1237 * precision floating-point number.
1238 * The input significand `zFrac' has its binary point between bits 30
1239 * and 29, which is 7 bits to the left of the usual location. This shifted
1240 * significand must be normalized or smaller. If `zFrac' is not normalized,
1241 * `zExp' must be 0; in that case, the result returned is a subnormal number,
1242 * and it must not require rounding. In the usual case that `zFrac' is
1243 * normalized, `zExp' must be 1 less than the "true" floating-point exponent.
1244 * The handling of underflow and overflow follows the IEEE Standard for
1245 * Floating-Point Arithmetic.
1248 __roundAndPackFloat32(uint zSign, int zExp, uint zFrac)
1250 bool roundNearestEven;
1254 roundNearestEven = FLOAT_ROUNDING_MODE == FLOAT_ROUND_NEAREST_EVEN;
1255 roundIncrement = 0x40;
1256 if (!roundNearestEven) {
1257 if (FLOAT_ROUNDING_MODE == FLOAT_ROUND_TO_ZERO) {
1260 roundIncrement = 0x7F;
1262 if (FLOAT_ROUNDING_MODE == FLOAT_ROUND_UP)
1265 if (FLOAT_ROUNDING_MODE == FLOAT_ROUND_DOWN)
1270 roundBits = int(zFrac & 0x7Fu);
1271 if (0xFDu <= uint(zExp)) {
1272 if ((0xFD < zExp) || ((zExp == 0xFD) && (int(zFrac) + roundIncrement) < 0))
1273 return __packFloat32(zSign, 0xFF, 0u) - float(roundIncrement == 0);
1275 bool zexp_lt0 = zExp < 0;
1276 uint zFrac_lt0 = mix(uint(zFrac != 0u), (zFrac>>count) | uint((zFrac<<((-count) & 31)) != 0u), (-zExp) < 32);
1277 zFrac = mix(zFrac, zFrac_lt0, zexp_lt0);
1278 roundBits = mix(roundBits, int(zFrac) & 0x7f, zexp_lt0);
1279 zExp = mix(zExp, 0, zexp_lt0);
1281 zFrac = (zFrac + uint(roundIncrement))>>7;
1282 zFrac &= ~uint(((roundBits ^ 0x40) == 0) && roundNearestEven);
1284 return __packFloat32(zSign, mix(zExp, 0, zFrac == 0u), zFrac);
1287 /* Returns the result of converting the double-precision floating-point value
1288 * `a' to the single-precision floating-point format. The conversion is
1289 * performed according to the IEEE Standard for Floating-Point Arithmetic.
1292 __fp64_to_fp32(uint64_t __a)
1294 uvec2 a = unpackUint2x32(__a);
1298 uint aFracLo = __extractFloat64FracLo(__a);
1299 uint aFracHi = __extractFloat64FracHi(__a);
1300 int aExp = __extractFloat64Exp(__a);
1301 uint aSign = __extractFloat64Sign(__a);
1302 if (aExp == 0x7FF) {
1303 __shortShift64Left(a.y, a.x, 12, a.y, a.x);
1304 float rval = uintBitsToFloat(aSign | 0x7FC00000u | (a.y>>9));
1305 rval = mix(__packFloat32(aSign, 0xFF, 0u), rval, (aFracHi | aFracLo) != 0u);
1308 __shift64RightJamming(aFracHi, aFracLo, 22, allZero, zFrac);
1309 zFrac = mix(zFrac, zFrac | 0x40000000u, aExp != 0);
1310 return __roundAndPackFloat32(aSign, aExp - 0x381, zFrac);
1314 __uint64_to_fp32(uint64_t __a)
1316 uvec2 aFrac = unpackUint2x32(__a);
1317 int shiftCount = mix(__countLeadingZeros32(aFrac.y) - 33,
1318 __countLeadingZeros32(aFrac.x) - 1,
1321 if (0 <= shiftCount)
1322 __shortShift64Left(aFrac.y, aFrac.x, shiftCount, aFrac.y, aFrac.x);
1324 __shift64RightJamming(aFrac.y, aFrac.x, -shiftCount, aFrac.y, aFrac.x);
1326 return __roundAndPackFloat32(0u, 0x9C - shiftCount, aFrac.x);
1330 __int64_to_fp32(int64_t __a)
1332 uint aSign = uint(unpackInt2x32(__a).y) & 0x80000000u;
1333 uint64_t absA = mix(uint64_t(__a), uint64_t(-__a), __a < 0);
1334 uvec2 aFrac = unpackUint2x32(absA);
1335 int shiftCount = mix(__countLeadingZeros32(aFrac.y) - 33,
1336 __countLeadingZeros32(aFrac.x) - 1,
1339 if (0 <= shiftCount)
1340 __shortShift64Left(aFrac.y, aFrac.x, shiftCount, aFrac.y, aFrac.x);
1342 __shift64RightJamming(aFrac.y, aFrac.x, -shiftCount, aFrac.y, aFrac.x);
1344 return __roundAndPackFloat32(aSign, 0x9C - shiftCount, aFrac.x);
1347 /* Returns the result of converting the single-precision floating-point value
1348 * `a' to the double-precision floating-point format.
1351 __fp32_to_fp64(float f)
1353 uint a = floatBitsToUint(f);
1354 uint aFrac = a & 0x007FFFFFu;
1355 int aExp = int((a>>23) & 0xFFu);
1356 uint aSign = a & 0x80000000u;
1364 __shift64Right(nanHi, nanLo, 12, nanHi, nanLo);
1365 nanHi |= aSign | 0x7FF80000u;
1366 return packUint2x32(uvec2(nanLo, nanHi));
1368 return __packFloat64(aSign, 0x7FF, 0u, 0u);
1373 return __packFloat64(aSign, 0, 0u, 0u);
1374 /* Normalize subnormal */
1375 int shiftCount = __countLeadingZeros32(aFrac) - 8;
1376 aFrac <<= shiftCount;
1377 aExp = 1 - shiftCount;
1381 __shift64Right(aFrac, 0u, 3, zFrac0, zFrac1);
1382 return __packFloat64(aSign, aExp + 0x380, zFrac0, zFrac1);
1385 /* Adds the 96-bit value formed by concatenating `a0', `a1', and `a2' to the
1386 * 96-bit value formed by concatenating `b0', `b1', and `b2'. Addition is
1387 * modulo 2^96, so any carry out is lost. The result is broken into three
1388 * 32-bit pieces which are stored at the locations pointed to by `z0Ptr',
1389 * `z1Ptr', and `z2Ptr'.
1392 __add96(uint a0, uint a1, uint a2,
1393 uint b0, uint b1, uint b2,
1399 uint carry1 = uint(z2 < a2);
1401 uint carry0 = uint(z1 < a1);
1404 z0 += uint(z1 < carry1);
1411 /* Subtracts the 96-bit value formed by concatenating `b0', `b1', and `b2' from
1412 * the 96-bit value formed by concatenating `a0', `a1', and `a2'. Subtraction
1413 * is modulo 2^96, so any borrow out (carry out) is lost. The result is broken
1414 * into three 32-bit pieces which are stored at the locations pointed to by
1415 * `z0Ptr', `z1Ptr', and `z2Ptr'.
1418 __sub96(uint a0, uint a1, uint a2,
1419 uint b0, uint b1, uint b2,
1425 uint borrow1 = uint(a2 < b2);
1427 uint borrow0 = uint(a1 < b1);
1429 z0 -= uint(z1 < borrow1);
1437 /* Returns an approximation to the 32-bit integer quotient obtained by dividing
1438 * `b' into the 64-bit value formed by concatenating `a0' and `a1'. The
1439 * divisor `b' must be at least 2^31. If q is the exact quotient truncated
1440 * toward zero, the approximation returned lies between q and q + 2 inclusive.
1441 * If the exact quotient q is larger than 32 bits, the maximum positive 32-bit
1442 * unsigned integer is returned.
1445 __estimateDiv64To32(uint a0, uint a1, uint b)
1458 z = (b0<<16 <= a0) ? 0xFFFF0000u : (a0 / b0)<<16;
1459 umulExtended(b, z, term0, term1);
1460 __sub64(a0, a1, term0, term1, rem0, rem1);
1461 while (int(rem0) < 0) {
1464 __add64(rem0, rem1, b0, b1, rem0, rem1);
1466 rem0 = (rem0<<16) | (rem1>>16);
1467 z |= (b0<<16 <= rem0) ? 0xFFFFu : rem0 / b0;
1472 __sqrtOddAdjustments(int index)
1512 __sqrtEvenAdjustments(int index)
1551 /* Returns an approximation to the square root of the 32-bit significand given
1552 * by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 of
1553 * `aExp' (the least significant bit) is 1, the integer returned approximates
1554 * 2^31*sqrt(`a'/2^31), where `a' is considered an integer. If bit 0 of `aExp'
1555 * is 0, the integer returned approximates 2^31*sqrt(`a'/2^30). In either
1556 * case, the approximation returned lies strictly within +/-2 of the exact
1560 __estimateSqrt32(int aExp, uint a)
1564 int index = int(a>>27 & 15u);
1565 if ((aExp & 1) != 0) {
1566 z = 0x4000u + (a>>17) - __sqrtOddAdjustments(index);
1567 z = ((a / z)<<14) + (z<<15);
1570 z = 0x8000u + (a>>17) - __sqrtEvenAdjustments(index);
1572 z = (0x20000u <= z) ? 0xFFFF8000u : (z<<15);
1574 return uint(int(a)>>1);
1576 return ((__estimateDiv64To32(a, 0u, z))>>1) + (z>>1);
1579 /* Returns the square root of the double-precision floating-point value `a'.
1580 * The operation is performed according to the IEEE Standard for Floating-Point
1584 __fsqrt64(uint64_t a)
1589 uint doubleZFrac0 = 0u;
1598 uint64_t default_nan = 0xFFFFFFFFFFFFFFFFUL;
1600 uint aFracLo = __extractFloat64FracLo(a);
1601 uint aFracHi = __extractFloat64FracHi(a);
1602 int aExp = __extractFloat64Exp(a);
1603 uint aSign = __extractFloat64Sign(a);
1604 if (aExp == 0x7FF) {
1605 if ((aFracHi | aFracLo) != 0u)
1606 return __propagateFloat64NaN(a, a);
1612 if ((uint(aExp) | aFracHi | aFracLo) == 0u)
1617 if ((aFracHi | aFracLo) == 0u)
1618 return __packFloat64(0u, 0, 0u, 0u);
1619 __normalizeFloat64Subnormal(aFracHi, aFracLo, aExp, aFracHi, aFracLo);
1621 int zExp = ((aExp - 0x3FF)>>1) + 0x3FE;
1622 aFracHi |= 0x00100000u;
1623 __shortShift64Left(aFracHi, aFracLo, 11, term0, term1);
1624 zFrac0 = (__estimateSqrt32(aExp, term0)>>1) + 1u;
1626 zFrac0 = 0x7FFFFFFFu;
1627 doubleZFrac0 = zFrac0 + zFrac0;
1628 __shortShift64Left(aFracHi, aFracLo, 9 - (aExp & 1), aFracHi, aFracLo);
1629 umulExtended(zFrac0, zFrac0, term0, term1);
1630 __sub64(aFracHi, aFracLo, term0, term1, rem0, rem1);
1631 while (int(rem0) < 0) {
1634 __add64(rem0, rem1, 0u, doubleZFrac0 | 1u, rem0, rem1);
1636 zFrac1 = __estimateDiv64To32(rem1, 0u, doubleZFrac0);
1637 if ((zFrac1 & 0x1FFu) <= 5u) {
1640 umulExtended(doubleZFrac0, zFrac1, term1, term2);
1641 __sub64(rem1, 0u, term1, term2, rem1, rem2);
1642 umulExtended(zFrac1, zFrac1, term2, term3);
1643 __sub96(rem1, rem2, 0u, 0u, term2, term3, rem1, rem2, rem3);
1644 while (int(rem1) < 0) {
1646 __shortShift64Left(0u, zFrac1, 1, term2, term3);
1648 term2 |= doubleZFrac0;
1649 __add96(rem1, rem2, rem3, 0u, term2, term3, rem1, rem2, rem3);
1651 zFrac1 |= uint((rem1 | rem2 | rem3) != 0u);
1653 __shift64ExtraRightJamming(zFrac0, zFrac1, 0u, 10, zFrac0, zFrac1, zFrac2);
1654 return __roundAndPackFloat64(0u, zExp, zFrac0, zFrac1, zFrac2);
1658 __ftrunc64(uint64_t __a)
1660 uvec2 a = unpackUint2x32(__a);
1661 int aExp = __extractFloat64Exp(__a);
1665 int unbiasedExp = aExp - 1023;
1666 int fracBits = 52 - unbiasedExp;
1667 uint maskLo = mix(~0u << fracBits, 0u, fracBits >= 32);
1668 uint maskHi = mix(~0u << (fracBits - 32), ~0u, fracBits < 33);
1672 zLo = mix(zLo, 0u, unbiasedExp < 0);
1673 zHi = mix(zHi, 0u, unbiasedExp < 0);
1674 zLo = mix(zLo, a.x, unbiasedExp > 52);
1675 zHi = mix(zHi, a.y, unbiasedExp > 52);
1676 return packUint2x32(uvec2(zLo, zHi));
1680 __ffloor64(uint64_t a)
1682 bool is_positive = __fge64(a, 0ul);
1683 uint64_t tr = __ftrunc64(a);
1685 if (is_positive || __feq64(tr, a)) {
1688 return __fadd64(tr, 0xbff0000000000000ul /* -1.0 */);
1693 __fround64(uint64_t __a)
1695 uvec2 a = unpackUint2x32(__a);
1696 int unbiasedExp = __extractFloat64Exp(__a) - 1023;
1700 if (unbiasedExp < 20) {
1701 if (unbiasedExp < 0) {
1702 if ((aHi & 0x80000000u) != 0u && aLo == 0u) {
1706 if ((a.y & 0x000FFFFFu) == 0u && a.x == 0u) {
1708 return packUint2x32(uvec2(aLo, aHi));
1710 aHi = mix(aHi, (aHi | 0x3FF00000u), unbiasedExp == -1);
1713 uint maskExp = 0x000FFFFFu >> unbiasedExp;
1714 uint lastBit = maskExp + 1;
1715 aHi += 0x00080000u >> unbiasedExp;
1716 if ((aHi & maskExp) == 0u)
1721 } else if (unbiasedExp > 51 || unbiasedExp == 1024) {
1724 uint maskExp = 0xFFFFFFFFu >> (unbiasedExp - 20);
1725 if ((aLo & maskExp) == 0u)
1727 uint tmp = aLo + (1u << (51 - unbiasedExp));
1734 return packUint2x32(uvec2(aLo, aHi));
1738 __fmin64(uint64_t a, uint64_t b)
1740 if (__is_nan(a)) return b;
1741 if (__is_nan(b)) return a;
1743 if (__flt64_nonnan(a, b)) return a;
1748 __fmax64(uint64_t a, uint64_t b)
1750 if (__is_nan(a)) return b;
1751 if (__is_nan(b)) return a;
1753 if (__flt64_nonnan(a, b)) return b;
1758 __ffract64(uint64_t a)
1760 return __fadd64(a, __fneg64(__ffloor64(a)));