src/compiler/glsl/lower_int64.cpp

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file lower_int64.cpp
  26  *
  27  * Lower 64-bit operations to 32-bit operations.  Each 64-bit value is lowered
  28  * to a uvec2.  For each operation that can be lowered, there is a function
  29  * called __builtin_foo with the same number of parameters that takes uvec2
  30  * sources and produces uvec2 results.  An operation like
  31  *
  32  *     uint64_t(x) * uint64_t(y)
  33  *
  34  * becomes
  35  *
  36  *     packUint2x32(__builtin_umul64(unpackUint2x32(x), unpackUint2x32(y)));
  37  */
  38
  39 #include "main/macros.h"
  40 #include "compiler/glsl_types.h"
  41 #include "ir.h"
  42 #include "ir_rvalue_visitor.h"
  43 #include "ir_builder.h"
  44 #include "ir_optimization.h"
  45 #include "util/hash_table.h"
  46 #include "builtin_functions.h"
  47
  48 typedef ir_function_signature *(*function_generator)(void *mem_ctx,
  49                                                      builtin_available_predicate avail);
  50
  51 using namespace ir_builder;
  52
  53 namespace lower_64bit {
  54 void expand_source(ir_factory &, ir_rvalue *val, ir_variable **expanded_src);
  55
  56 ir_dereference_variable *compact_destination(ir_factory &,
  57                                              const glsl_type *type,
  58                                              ir_variable *result[4]);
  59
  60 ir_rvalue *lower_op_to_function_call(ir_instruction *base_ir,
  61                                      ir_expression *ir,
  62                                      ir_function_signature *callee);
  63 };
  64
  65 using namespace lower_64bit;
  66
  67 namespace {
  68
  69 class lower_64bit_visitor : public ir_rvalue_visitor {
  70 public:
  71    lower_64bit_visitor(void *mem_ctx, exec_list *instructions, unsigned lower)
  72       : progress(false), lower(lower), instructions(instructions),
  73         function_list(), added_functions(&function_list, mem_ctx)
  74    {
  75       functions = _mesa_hash_table_create(mem_ctx,
  76                                           _mesa_key_hash_string,
  77                                           _mesa_key_string_equal);
  78
  79       foreach_in_list(ir_instruction, node, instructions) {
  80          ir_function *const f = node->as_function();
  81
  82          if (f == NULL || strncmp(f->name, "__builtin_", 10) != 0)
  83             continue;
  84
  85          add_function(f);
  86       }
  87    }
  88
  89    ~lower_64bit_visitor()
  90    {
  91       _mesa_hash_table_destroy(functions, NULL);
  92    }
  93
  94    void handle_rvalue(ir_rvalue **rvalue);
  95
  96    void add_function(ir_function *f)
  97    {
  98       _mesa_hash_table_insert(functions, f->name, f);
  99    }
 100
 101    ir_function *find_function(const char *name)
 102    {
 103       struct hash_entry *const entry =
 104          _mesa_hash_table_search(functions, name);
 105
 106       return entry != NULL ? (ir_function *) entry->data : NULL;
 107    }
 108
 109    bool progress;
 110
 111 private:
 112    unsigned lower; /** Bitfield of which operations to lower */
 113
 114    exec_list *instructions;
 115
 116    /** Hashtable containing all of the known functions in the IR */
 117    struct hash_table *functions;
 118
 119 public:
 120    exec_list function_list;
 121
 122 private:
 123    ir_factory added_functions;
 124
 125    ir_rvalue *handle_op(ir_expression *ir, const char *function_name,
 126                         function_generator generator);
 127 };
 128
 129 } /* anonymous namespace */
 130
 131 static bool
 132 is_integer_64(const glsl_type *t)
 133 {
 134    return t->base_type == GLSL_TYPE_UINT64 || t->base_type == GLSL_TYPE_INT64;
 135 }
 136
 137 /**
 138  * Determine if a particular type of lowering should occur
 139  */
 140 #define lowering(x) (this->lower & x)
 141
 142 bool
 143 lower_64bit_integer_instructions(exec_list *instructions,
 144                                  unsigned what_to_lower)
 145 {
 146    if (instructions->is_empty())
 147       return false;
 148
 149    ir_instruction *first_inst = (ir_instruction *) instructions->get_head_raw();
 150    void *const mem_ctx = ralloc_parent(first_inst);
 151    lower_64bit_visitor v(mem_ctx, instructions, what_to_lower);
 152
 153    visit_list_elements(&v, instructions);
 154
 155    if (v.progress && !v.function_list.is_empty()) {
 156       /* Move all of the nodes from function_list to the head if the incoming
 157        * instruction list.
 158        */
 159       exec_node *const after = &instructions->head_sentinel;
 160       exec_node *const before = instructions->head_sentinel.next;
 161       exec_node *const head = v.function_list.head_sentinel.next;
 162       exec_node *const tail = v.function_list.tail_sentinel.prev;
 163
 164       before->next = head;
 165       head->prev = before;
 166
 167       after->prev = tail;
 168       tail->next = after;
 169    }
 170
 171    return v.progress;
 172 }
 173
 174
 175 /**
 176  * Expand individual 64-bit values to uvec2 values
 177  *
 178  * Each operation is in one of a few forms.
 179  *
 180  *     vector op vector
 181  *     vector op scalar
 182  *     scalar op vector
 183  *     scalar op scalar
 184  *
 185  * In the 'vector op vector' case, the two vectors must have the same size.
 186  * In a way, the 'scalar op scalar' form is special case of the 'vector op
 187  * vector' form.
 188  *
 189  * This method generates a new set of uvec2 values for each element of a
 190  * single operand.  If the operand is a scalar, the uvec2 is replicated
 191  * multiple times.  A value like
 192  *
 193  *     u64vec3(a) + u64vec3(b)
 194  *
 195  * becomes
 196  *
 197  *     u64vec3 tmp0 = u64vec3(a) + u64vec3(b);
 198  *     uvec2 tmp1 = unpackUint2x32(tmp0.x);
 199  *     uvec2 tmp2 = unpackUint2x32(tmp0.y);
 200  *     uvec2 tmp3 = unpackUint2x32(tmp0.z);
 201  *
 202  * and the returned operands array contains ir_variable pointers to
 203  *
 204  *     { tmp1, tmp2, tmp3, tmp1 }
 205  */
 206 void
 207 lower_64bit::expand_source(ir_factory &body,
 208                            ir_rvalue *val,
 209                            ir_variable **expanded_src)
 210 {
 211    assert(val->type->base_type == GLSL_TYPE_UINT64 ||
 212           val->type->base_type == GLSL_TYPE_INT64);
 213
 214    ir_variable *const temp = body.make_temp(val->type, "tmp");
 215
 216    body.emit(assign(temp, val));
 217
 218    const ir_expression_operation unpack_opcode =
 219       val->type->base_type == GLSL_TYPE_UINT64
 220       ? ir_unop_unpack_uint_2x32 : ir_unop_unpack_int_2x32;
 221
 222    const glsl_type *const type =
 223       val->type->base_type == GLSL_TYPE_UINT64
 224       ? glsl_type::uvec2_type : glsl_type::ivec2_type;
 225
 226    unsigned i;
 227    for (i = 0; i < val->type->vector_elements; i++) {
 228       expanded_src[i] = body.make_temp(type, "expanded_64bit_source");
 229
 230       body.emit(assign(expanded_src[i],
 231                        expr(unpack_opcode, swizzle(temp, i, 1))));
 232    }
 233
 234    for (/* empty */; i < 4; i++)
 235       expanded_src[i] = expanded_src[0];
 236 }
 237
 238 /**
 239  * Convert a series of uvec2 results into a single 64-bit integer vector
 240  */
 241 ir_dereference_variable *
 242 lower_64bit::compact_destination(ir_factory &body,
 243                                  const glsl_type *type,
 244                                  ir_variable *result[4])
 245 {
 246    const ir_expression_operation pack_opcode =
 247       type->base_type == GLSL_TYPE_UINT64
 248       ? ir_unop_pack_uint_2x32 : ir_unop_pack_int_2x32;
 249
 250    ir_variable *const compacted_result =
 251       body.make_temp(type, "compacted_64bit_result");
 252
 253    for (unsigned i = 0; i < type->vector_elements; i++) {
 254       body.emit(assign(compacted_result,
 255                        expr(pack_opcode, result[i]),
 256                        1U << i));
 257    }
 258
 259    void *const mem_ctx = ralloc_parent(compacted_result);
 260    return new(mem_ctx) ir_dereference_variable(compacted_result);
 261 }
 262
 263 ir_rvalue *
 264 lower_64bit::lower_op_to_function_call(ir_instruction *base_ir,
 265                                        ir_expression *ir,
 266                                        ir_function_signature *callee)
 267 {
 268    const unsigned num_operands = ir->get_num_operands();
 269    ir_variable *src[4][4];
 270    ir_variable *dst[4];
 271    void *const mem_ctx = ralloc_parent(ir);
 272    exec_list instructions;
 273    unsigned source_components = 0;
 274    const glsl_type *const result_type =
 275       ir->type->base_type == GLSL_TYPE_UINT64
 276       ? glsl_type::uvec2_type : glsl_type::ivec2_type;
 277
 278    ir_factory body(&instructions, mem_ctx);
 279
 280    for (unsigned i = 0; i < num_operands; i++) {
 281       expand_source(body, ir->operands[i], src[i]);
 282
 283       if (ir->operands[i]->type->vector_elements > source_components)
 284          source_components = ir->operands[i]->type->vector_elements;
 285    }
 286
 287    for (unsigned i = 0; i < source_components; i++) {
 288       dst[i] = body.make_temp(result_type, "expanded_64bit_result");
 289
 290       exec_list parameters;
 291
 292       for (unsigned j = 0; j < num_operands; j++)
 293          parameters.push_tail(new(mem_ctx) ir_dereference_variable(src[j][i]));
 294
 295       ir_dereference_variable *const return_deref =
 296          new(mem_ctx) ir_dereference_variable(dst[i]);
 297
 298       ir_call *const c = new(mem_ctx) ir_call(callee,
 299                                               return_deref,
 300                                               &parameters);
 301
 302       body.emit(c);
 303    }
 304
 305    ir_rvalue *const rv = compact_destination(body, ir->type, dst);
 306
 307    /* Move all of the nodes from instructions between base_ir and the
 308     * instruction before it.
 309     */
 310    exec_node *const after = base_ir;
 311    exec_node *const before = after->prev;
 312    exec_node *const head = instructions.head_sentinel.next;
 313    exec_node *const tail = instructions.tail_sentinel.prev;
 314
 315    before->next = head;
 316    head->prev = before;
 317
 318    after->prev = tail;
 319    tail->next = after;
 320
 321    return rv;
 322 }
 323
 324 ir_rvalue *
 325 lower_64bit_visitor::handle_op(ir_expression *ir,
 326                                const char *function_name,
 327                                function_generator generator)
 328 {
 329    for (unsigned i = 0; i < ir->get_num_operands(); i++)
 330       if (!is_integer_64(ir->operands[i]->type))
 331          return ir;
 332
 333    /* Get a handle to the correct ir_function_signature for the core
 334     * operation.
 335     */
 336    ir_function_signature *callee = NULL;
 337    ir_function *f = find_function(function_name);
 338
 339    if (f != NULL) {
 340       callee = (ir_function_signature *) f->signatures.get_head();
 341       assert(callee != NULL && callee->ir_type == ir_type_function_signature);
 342    } else {
 343       f = new(base_ir) ir_function(function_name);
 344       callee = generator(base_ir, NULL);
 345
 346       f->add_signature(callee);
 347
 348       add_function(f);
 349    }
 350
 351    return lower_op_to_function_call(this->base_ir, ir, callee);
 352 }
 353
 354 void
 355 lower_64bit_visitor::handle_rvalue(ir_rvalue **rvalue)
 356 {
 357    if (*rvalue == NULL || (*rvalue)->ir_type != ir_type_expression)
 358       return;
 359
 360    ir_expression *const ir = (*rvalue)->as_expression();
 361    assert(ir != NULL);
 362
 363    switch (ir->operation) {
 364    case ir_binop_mul:
 365       if (lowering(MUL64)) {
 366          *rvalue = handle_op(ir, "__builtin_umul64", generate_ir::umul64);
 367          this->progress = true;
 368       }
 369       break;
 370
 371    default:
 372       break;
 373    }
 374 }