src/compiler/nir/nir.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Connor Abbott (cwabbott0@gmail.com)
  25  *
  26  */
  27
  28 #include "nir.h"
  29 #include "nir_control_flow_private.h"
  30 #include "util/half_float.h"
  31 #include <limits.h>
  32 #include <assert.h>
  33 #include <math.h>
  34
  35 nir_shader *
  36 nir_shader_create(void *mem_ctx,
  37                   gl_shader_stage stage,
  38                   const nir_shader_compiler_options *options,
  39                   shader_info *si)
  40 {
  41    nir_shader *shader = rzalloc(mem_ctx, nir_shader);
  42
  43    exec_list_make_empty(&shader->uniforms);
  44    exec_list_make_empty(&shader->inputs);
  45    exec_list_make_empty(&shader->outputs);
  46    exec_list_make_empty(&shader->shared);
  47
  48    shader->options = options;
  49
  50    if (si) {
  51       assert(si->stage == stage);
  52       shader->info = *si;
  53    } else {
  54       shader->info.stage = stage;
  55    }
  56
  57    exec_list_make_empty(&shader->functions);
  58    exec_list_make_empty(&shader->registers);
  59    exec_list_make_empty(&shader->globals);
  60    exec_list_make_empty(&shader->system_values);
  61    shader->reg_alloc = 0;
  62
  63    shader->num_inputs = 0;
  64    shader->num_outputs = 0;
  65    shader->num_uniforms = 0;
  66    shader->num_shared = 0;
  67
  68    return shader;
  69 }
  70
  71 static nir_register *
  72 reg_create(void *mem_ctx, struct exec_list *list)
  73 {
  74    nir_register *reg = ralloc(mem_ctx, nir_register);
  75
  76    list_inithead(&reg->uses);
  77    list_inithead(&reg->defs);
  78    list_inithead(&reg->if_uses);
  79
  80    reg->num_components = 0;
  81    reg->bit_size = 32;
  82    reg->num_array_elems = 0;
  83    reg->is_packed = false;
  84    reg->name = NULL;
  85
  86    exec_list_push_tail(list, &reg->node);
  87
  88    return reg;
  89 }
  90
  91 nir_register *
  92 nir_global_reg_create(nir_shader *shader)
  93 {
  94    nir_register *reg = reg_create(shader, &shader->registers);
  95    reg->index = shader->reg_alloc++;
  96    reg->is_global = true;
  97
  98    return reg;
  99 }
 100
 101 nir_register *
 102 nir_local_reg_create(nir_function_impl *impl)
 103 {
 104    nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers);
 105    reg->index = impl->reg_alloc++;
 106    reg->is_global = false;
 107
 108    return reg;
 109 }
 110
 111 void
 112 nir_reg_remove(nir_register *reg)
 113 {
 114    exec_node_remove(&reg->node);
 115 }
 116
 117 void
 118 nir_shader_add_variable(nir_shader *shader, nir_variable *var)
 119 {
 120    switch (var->data.mode) {
 121    case nir_var_all:
 122       assert(!"invalid mode");
 123       break;
 124
 125    case nir_var_local:
 126       assert(!"nir_shader_add_variable cannot be used for local variables");
 127       break;
 128
 129    case nir_var_global:
 130       exec_list_push_tail(&shader->globals, &var->node);
 131       break;
 132
 133    case nir_var_shader_in:
 134       exec_list_push_tail(&shader->inputs, &var->node);
 135       break;
 136
 137    case nir_var_shader_out:
 138       exec_list_push_tail(&shader->outputs, &var->node);
 139       break;
 140
 141    case nir_var_uniform:
 142    case nir_var_shader_storage:
 143       exec_list_push_tail(&shader->uniforms, &var->node);
 144       break;
 145
 146    case nir_var_shared:
 147       assert(shader->info.stage == MESA_SHADER_COMPUTE);
 148       exec_list_push_tail(&shader->shared, &var->node);
 149       break;
 150
 151    case nir_var_system_value:
 152       exec_list_push_tail(&shader->system_values, &var->node);
 153       break;
 154    }
 155 }
 156
 157 nir_variable *
 158 nir_variable_create(nir_shader *shader, nir_variable_mode mode,
 159                     const struct glsl_type *type, const char *name)
 160 {
 161    nir_variable *var = rzalloc(shader, nir_variable);
 162    var->name = ralloc_strdup(var, name);
 163    var->type = type;
 164    var->data.mode = mode;
 165
 166    if ((mode == nir_var_shader_in &&
 167         shader->info.stage != MESA_SHADER_VERTEX) ||
 168        (mode == nir_var_shader_out &&
 169         shader->info.stage != MESA_SHADER_FRAGMENT))
 170       var->data.interpolation = INTERP_MODE_SMOOTH;
 171
 172    if (mode == nir_var_shader_in || mode == nir_var_uniform)
 173       var->data.read_only = true;
 174
 175    nir_shader_add_variable(shader, var);
 176
 177    return var;
 178 }
 179
 180 nir_variable *
 181 nir_local_variable_create(nir_function_impl *impl,
 182                           const struct glsl_type *type, const char *name)
 183 {
 184    nir_variable *var = rzalloc(impl->function->shader, nir_variable);
 185    var->name = ralloc_strdup(var, name);
 186    var->type = type;
 187    var->data.mode = nir_var_local;
 188
 189    nir_function_impl_add_variable(impl, var);
 190
 191    return var;
 192 }
 193
 194 nir_function *
 195 nir_function_create(nir_shader *shader, const char *name)
 196 {
 197    nir_function *func = ralloc(shader, nir_function);
 198
 199    exec_list_push_tail(&shader->functions, &func->node);
 200
 201    func->name = ralloc_strdup(func, name);
 202    func->shader = shader;
 203    func->num_params = 0;
 204    func->params = NULL;
 205    func->impl = NULL;
 206
 207    return func;
 208 }
 209
 210 /* NOTE: if the instruction you are copying a src to is already added
 211  * to the IR, use nir_instr_rewrite_src() instead.
 212  */
 213 void nir_src_copy(nir_src *dest, const nir_src *src, void *mem_ctx)
 214 {
 215    dest->is_ssa = src->is_ssa;
 216    if (src->is_ssa) {
 217       dest->ssa = src->ssa;
 218    } else {
 219       dest->reg.base_offset = src->reg.base_offset;
 220       dest->reg.reg = src->reg.reg;
 221       if (src->reg.indirect) {
 222          dest->reg.indirect = ralloc(mem_ctx, nir_src);
 223          nir_src_copy(dest->reg.indirect, src->reg.indirect, mem_ctx);
 224       } else {
 225          dest->reg.indirect = NULL;
 226       }
 227    }
 228 }
 229
 230 void nir_dest_copy(nir_dest *dest, const nir_dest *src, nir_instr *instr)
 231 {
 232    /* Copying an SSA definition makes no sense whatsoever. */
 233    assert(!src->is_ssa);
 234
 235    dest->is_ssa = false;
 236
 237    dest->reg.base_offset = src->reg.base_offset;
 238    dest->reg.reg = src->reg.reg;
 239    if (src->reg.indirect) {
 240       dest->reg.indirect = ralloc(instr, nir_src);
 241       nir_src_copy(dest->reg.indirect, src->reg.indirect, instr);
 242    } else {
 243       dest->reg.indirect = NULL;
 244    }
 245 }
 246
 247 void
 248 nir_alu_src_copy(nir_alu_src *dest, const nir_alu_src *src,
 249                  nir_alu_instr *instr)
 250 {
 251    nir_src_copy(&dest->src, &src->src, &instr->instr);
 252    dest->abs = src->abs;
 253    dest->negate = src->negate;
 254    for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
 255       dest->swizzle[i] = src->swizzle[i];
 256 }
 257
 258 void
 259 nir_alu_dest_copy(nir_alu_dest *dest, const nir_alu_dest *src,
 260                   nir_alu_instr *instr)
 261 {
 262    nir_dest_copy(&dest->dest, &src->dest, &instr->instr);
 263    dest->write_mask = src->write_mask;
 264    dest->saturate = src->saturate;
 265 }
 266
 267
 268 static void
 269 cf_init(nir_cf_node *node, nir_cf_node_type type)
 270 {
 271    exec_node_init(&node->node);
 272    node->parent = NULL;
 273    node->type = type;
 274 }
 275
 276 nir_function_impl *
 277 nir_function_impl_create_bare(nir_shader *shader)
 278 {
 279    nir_function_impl *impl = ralloc(shader, nir_function_impl);
 280
 281    impl->function = NULL;
 282
 283    cf_init(&impl->cf_node, nir_cf_node_function);
 284
 285    exec_list_make_empty(&impl->body);
 286    exec_list_make_empty(&impl->registers);
 287    exec_list_make_empty(&impl->locals);
 288    impl->reg_alloc = 0;
 289    impl->ssa_alloc = 0;
 290    impl->valid_metadata = nir_metadata_none;
 291
 292    /* create start & end blocks */
 293    nir_block *start_block = nir_block_create(shader);
 294    nir_block *end_block = nir_block_create(shader);
 295    start_block->cf_node.parent = &impl->cf_node;
 296    end_block->cf_node.parent = &impl->cf_node;
 297    impl->end_block = end_block;
 298
 299    exec_list_push_tail(&impl->body, &start_block->cf_node.node);
 300
 301    start_block->successors[0] = end_block;
 302    _mesa_set_add(end_block->predecessors, start_block);
 303    return impl;
 304 }
 305
 306 nir_function_impl *
 307 nir_function_impl_create(nir_function *function)
 308 {
 309    assert(function->impl == NULL);
 310
 311    nir_function_impl *impl = nir_function_impl_create_bare(function->shader);
 312
 313    function->impl = impl;
 314    impl->function = function;
 315
 316    return impl;
 317 }
 318
 319 nir_block *
 320 nir_block_create(nir_shader *shader)
 321 {
 322    nir_block *block = rzalloc(shader, nir_block);
 323
 324    cf_init(&block->cf_node, nir_cf_node_block);
 325
 326    block->successors[0] = block->successors[1] = NULL;
 327    block->predecessors = _mesa_set_create(block, _mesa_hash_pointer,
 328                                           _mesa_key_pointer_equal);
 329    block->imm_dom = NULL;
 330    /* XXX maybe it would be worth it to defer allocation?  This
 331     * way it doesn't get allocated for shader refs that never run
 332     * nir_calc_dominance?  For example, state-tracker creates an
 333     * initial IR, clones that, runs appropriate lowering pass, passes
 334     * to driver which does common lowering/opt, and then stores ref
 335     * which is later used to do state specific lowering and futher
 336     * opt.  Do any of the references not need dominance metadata?
 337     */
 338    block->dom_frontier = _mesa_set_create(block, _mesa_hash_pointer,
 339                                           _mesa_key_pointer_equal);
 340
 341    exec_list_make_empty(&block->instr_list);
 342
 343    return block;
 344 }
 345
 346 static inline void
 347 src_init(nir_src *src)
 348 {
 349    src->is_ssa = false;
 350    src->reg.reg = NULL;
 351    src->reg.indirect = NULL;
 352    src->reg.base_offset = 0;
 353 }
 354
 355 nir_if *
 356 nir_if_create(nir_shader *shader)
 357 {
 358    nir_if *if_stmt = ralloc(shader, nir_if);
 359
 360    cf_init(&if_stmt->cf_node, nir_cf_node_if);
 361    src_init(&if_stmt->condition);
 362
 363    nir_block *then = nir_block_create(shader);
 364    exec_list_make_empty(&if_stmt->then_list);
 365    exec_list_push_tail(&if_stmt->then_list, &then->cf_node.node);
 366    then->cf_node.parent = &if_stmt->cf_node;
 367
 368    nir_block *else_stmt = nir_block_create(shader);
 369    exec_list_make_empty(&if_stmt->else_list);
 370    exec_list_push_tail(&if_stmt->else_list, &else_stmt->cf_node.node);
 371    else_stmt->cf_node.parent = &if_stmt->cf_node;
 372
 373    return if_stmt;
 374 }
 375
 376 nir_loop *
 377 nir_loop_create(nir_shader *shader)
 378 {
 379    nir_loop *loop = rzalloc(shader, nir_loop);
 380
 381    cf_init(&loop->cf_node, nir_cf_node_loop);
 382
 383    nir_block *body = nir_block_create(shader);
 384    exec_list_make_empty(&loop->body);
 385    exec_list_push_tail(&loop->body, &body->cf_node.node);
 386    body->cf_node.parent = &loop->cf_node;
 387
 388    body->successors[0] = body;
 389    _mesa_set_add(body->predecessors, body);
 390
 391    return loop;
 392 }
 393
 394 static void
 395 instr_init(nir_instr *instr, nir_instr_type type)
 396 {
 397    instr->type = type;
 398    instr->block = NULL;
 399    exec_node_init(&instr->node);
 400 }
 401
 402 static void
 403 dest_init(nir_dest *dest)
 404 {
 405    dest->is_ssa = false;
 406    dest->reg.reg = NULL;
 407    dest->reg.indirect = NULL;
 408    dest->reg.base_offset = 0;
 409 }
 410
 411 static void
 412 alu_dest_init(nir_alu_dest *dest)
 413 {
 414    dest_init(&dest->dest);
 415    dest->saturate = false;
 416    dest->write_mask = 0xf;
 417 }
 418
 419 static void
 420 alu_src_init(nir_alu_src *src)
 421 {
 422    src_init(&src->src);
 423    src->abs = src->negate = false;
 424    for (int i = 0; i < NIR_MAX_VEC_COMPONENTS; ++i)
 425       src->swizzle[i] = i;
 426 }
 427
 428 nir_alu_instr *
 429 nir_alu_instr_create(nir_shader *shader, nir_op op)
 430 {
 431    unsigned num_srcs = nir_op_infos[op].num_inputs;
 432    /* TODO: don't use rzalloc */
 433    nir_alu_instr *instr =
 434       rzalloc_size(shader,
 435                    sizeof(nir_alu_instr) + num_srcs * sizeof(nir_alu_src));
 436
 437    instr_init(&instr->instr, nir_instr_type_alu);
 438    instr->op = op;
 439    alu_dest_init(&instr->dest);
 440    for (unsigned i = 0; i < num_srcs; i++)
 441       alu_src_init(&instr->src[i]);
 442
 443    return instr;
 444 }
 445
 446 nir_deref_instr *
 447 nir_deref_instr_create(nir_shader *shader, nir_deref_type deref_type)
 448 {
 449    nir_deref_instr *instr =
 450       rzalloc_size(shader, sizeof(nir_deref_instr));
 451
 452    instr_init(&instr->instr, nir_instr_type_deref);
 453
 454    instr->deref_type = deref_type;
 455    if (deref_type != nir_deref_type_var)
 456       src_init(&instr->parent);
 457
 458    if (deref_type == nir_deref_type_array)
 459       src_init(&instr->arr.index);
 460
 461    dest_init(&instr->dest);
 462
 463    return instr;
 464 }
 465
 466 nir_jump_instr *
 467 nir_jump_instr_create(nir_shader *shader, nir_jump_type type)
 468 {
 469    nir_jump_instr *instr = ralloc(shader, nir_jump_instr);
 470    instr_init(&instr->instr, nir_instr_type_jump);
 471    instr->type = type;
 472    return instr;
 473 }
 474
 475 nir_load_const_instr *
 476 nir_load_const_instr_create(nir_shader *shader, unsigned num_components,
 477                             unsigned bit_size)
 478 {
 479    nir_load_const_instr *instr = rzalloc(shader, nir_load_const_instr);
 480    instr_init(&instr->instr, nir_instr_type_load_const);
 481
 482    nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
 483
 484    return instr;
 485 }
 486
 487 nir_intrinsic_instr *
 488 nir_intrinsic_instr_create(nir_shader *shader, nir_intrinsic_op op)
 489 {
 490    unsigned num_srcs = nir_intrinsic_infos[op].num_srcs;
 491    /* TODO: don't use rzalloc */
 492    nir_intrinsic_instr *instr =
 493       rzalloc_size(shader,
 494                   sizeof(nir_intrinsic_instr) + num_srcs * sizeof(nir_src));
 495
 496    instr_init(&instr->instr, nir_instr_type_intrinsic);
 497    instr->intrinsic = op;
 498
 499    if (nir_intrinsic_infos[op].has_dest)
 500       dest_init(&instr->dest);
 501
 502    for (unsigned i = 0; i < num_srcs; i++)
 503       src_init(&instr->src[i]);
 504
 505    return instr;
 506 }
 507
 508 nir_call_instr *
 509 nir_call_instr_create(nir_shader *shader, nir_function *callee)
 510 {
 511    const unsigned num_params = callee->num_params;
 512    nir_call_instr *instr =
 513       rzalloc_size(shader, sizeof(*instr) +
 514                    num_params * sizeof(instr->params[0]));
 515
 516    instr_init(&instr->instr, nir_instr_type_call);
 517    instr->callee = callee;
 518    instr->num_params = num_params;
 519    for (unsigned i = 0; i < num_params; i++)
 520       src_init(&instr->params[i]);
 521
 522    return instr;
 523 }
 524
 525 nir_tex_instr *
 526 nir_tex_instr_create(nir_shader *shader, unsigned num_srcs)
 527 {
 528    nir_tex_instr *instr = rzalloc(shader, nir_tex_instr);
 529    instr_init(&instr->instr, nir_instr_type_tex);
 530
 531    dest_init(&instr->dest);
 532
 533    instr->num_srcs = num_srcs;
 534    instr->src = ralloc_array(instr, nir_tex_src, num_srcs);
 535    for (unsigned i = 0; i < num_srcs; i++)
 536       src_init(&instr->src[i].src);
 537
 538    instr->texture_index = 0;
 539    instr->texture_array_size = 0;
 540    instr->sampler_index = 0;
 541
 542    return instr;
 543 }
 544
 545 void
 546 nir_tex_instr_add_src(nir_tex_instr *tex,
 547                       nir_tex_src_type src_type,
 548                       nir_src src)
 549 {
 550    nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
 551                                          tex->num_srcs + 1);
 552
 553    for (unsigned i = 0; i < tex->num_srcs; i++) {
 554       new_srcs[i].src_type = tex->src[i].src_type;
 555       nir_instr_move_src(&tex->instr, &new_srcs[i].src,
 556                          &tex->src[i].src);
 557    }
 558
 559    ralloc_free(tex->src);
 560    tex->src = new_srcs;
 561
 562    tex->src[tex->num_srcs].src_type = src_type;
 563    nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs].src, src);
 564    tex->num_srcs++;
 565 }
 566
 567 void
 568 nir_tex_instr_remove_src(nir_tex_instr *tex, unsigned src_idx)
 569 {
 570    assert(src_idx < tex->num_srcs);
 571
 572    /* First rewrite the source to NIR_SRC_INIT */
 573    nir_instr_rewrite_src(&tex->instr, &tex->src[src_idx].src, NIR_SRC_INIT);
 574
 575    /* Now, move all of the other sources down */
 576    for (unsigned i = src_idx + 1; i < tex->num_srcs; i++) {
 577       tex->src[i-1].src_type = tex->src[i].src_type;
 578       nir_instr_move_src(&tex->instr, &tex->src[i-1].src, &tex->src[i].src);
 579    }
 580    tex->num_srcs--;
 581 }
 582
 583 nir_phi_instr *
 584 nir_phi_instr_create(nir_shader *shader)
 585 {
 586    nir_phi_instr *instr = ralloc(shader, nir_phi_instr);
 587    instr_init(&instr->instr, nir_instr_type_phi);
 588
 589    dest_init(&instr->dest);
 590    exec_list_make_empty(&instr->srcs);
 591    return instr;
 592 }
 593
 594 nir_parallel_copy_instr *
 595 nir_parallel_copy_instr_create(nir_shader *shader)
 596 {
 597    nir_parallel_copy_instr *instr = ralloc(shader, nir_parallel_copy_instr);
 598    instr_init(&instr->instr, nir_instr_type_parallel_copy);
 599
 600    exec_list_make_empty(&instr->entries);
 601
 602    return instr;
 603 }
 604
 605 nir_ssa_undef_instr *
 606 nir_ssa_undef_instr_create(nir_shader *shader,
 607                            unsigned num_components,
 608                            unsigned bit_size)
 609 {
 610    nir_ssa_undef_instr *instr = ralloc(shader, nir_ssa_undef_instr);
 611    instr_init(&instr->instr, nir_instr_type_ssa_undef);
 612
 613    nir_ssa_def_init(&instr->instr, &instr->def, num_components, bit_size, NULL);
 614
 615    return instr;
 616 }
 617
 618 static nir_const_value
 619 const_value_float(double d, unsigned bit_size)
 620 {
 621    nir_const_value v;
 622    switch (bit_size) {
 623    case 16: v.u16[0] = _mesa_float_to_half(d);  break;
 624    case 32: v.f32[0] = d;                       break;
 625    case 64: v.f64[0] = d;                       break;
 626    default:
 627       unreachable("Invalid bit size");
 628    }
 629    return v;
 630 }
 631
 632 static nir_const_value
 633 const_value_int(int64_t i, unsigned bit_size)
 634 {
 635    nir_const_value v;
 636    switch (bit_size) {
 637    case 8:  v.i8[0]  = i;  break;
 638    case 16: v.i16[0] = i;  break;
 639    case 32: v.i32[0] = i;  break;
 640    case 64: v.i64[0] = i;  break;
 641    default:
 642       unreachable("Invalid bit size");
 643    }
 644    return v;
 645 }
 646
 647 nir_const_value
 648 nir_alu_binop_identity(nir_op binop, unsigned bit_size)
 649 {
 650    const int64_t max_int = (1ull << (bit_size - 1)) - 1;
 651    const int64_t min_int = -max_int - 1;
 652    switch (binop) {
 653    case nir_op_iadd:
 654       return const_value_int(0, bit_size);
 655    case nir_op_fadd:
 656       return const_value_float(0, bit_size);
 657    case nir_op_imul:
 658       return const_value_int(1, bit_size);
 659    case nir_op_fmul:
 660       return const_value_float(1, bit_size);
 661    case nir_op_imin:
 662       return const_value_int(max_int, bit_size);
 663    case nir_op_umin:
 664       return const_value_int(~0ull, bit_size);
 665    case nir_op_fmin:
 666       return const_value_float(INFINITY, bit_size);
 667    case nir_op_imax:
 668       return const_value_int(min_int, bit_size);
 669    case nir_op_umax:
 670       return const_value_int(0, bit_size);
 671    case nir_op_fmax:
 672       return const_value_float(-INFINITY, bit_size);
 673    case nir_op_iand:
 674       return const_value_int(~0ull, bit_size);
 675    case nir_op_ior:
 676       return const_value_int(0, bit_size);
 677    case nir_op_ixor:
 678       return const_value_int(0, bit_size);
 679    default:
 680       unreachable("Invalid reduction operation");
 681    }
 682 }
 683
 684 nir_function_impl *
 685 nir_cf_node_get_function(nir_cf_node *node)
 686 {
 687    while (node->type != nir_cf_node_function) {
 688       node = node->parent;
 689    }
 690
 691    return nir_cf_node_as_function(node);
 692 }
 693
 694 /* Reduces a cursor by trying to convert everything to after and trying to
 695  * go up to block granularity when possible.
 696  */
 697 static nir_cursor
 698 reduce_cursor(nir_cursor cursor)
 699 {
 700    switch (cursor.option) {
 701    case nir_cursor_before_block:
 702       assert(nir_cf_node_prev(&cursor.block->cf_node) == NULL ||
 703              nir_cf_node_prev(&cursor.block->cf_node)->type != nir_cf_node_block);
 704       if (exec_list_is_empty(&cursor.block->instr_list)) {
 705          /* Empty block.  After is as good as before. */
 706          cursor.option = nir_cursor_after_block;
 707       }
 708       return cursor;
 709
 710    case nir_cursor_after_block:
 711       return cursor;
 712
 713    case nir_cursor_before_instr: {
 714       nir_instr *prev_instr = nir_instr_prev(cursor.instr);
 715       if (prev_instr) {
 716          /* Before this instruction is after the previous */
 717          cursor.instr = prev_instr;
 718          cursor.option = nir_cursor_after_instr;
 719       } else {
 720          /* No previous instruction.  Switch to before block */
 721          cursor.block = cursor.instr->block;
 722          cursor.option = nir_cursor_before_block;
 723       }
 724       return reduce_cursor(cursor);
 725    }
 726
 727    case nir_cursor_after_instr:
 728       if (nir_instr_next(cursor.instr) == NULL) {
 729          /* This is the last instruction, switch to after block */
 730          cursor.option = nir_cursor_after_block;
 731          cursor.block = cursor.instr->block;
 732       }
 733       return cursor;
 734
 735    default:
 736       unreachable("Inavlid cursor option");
 737    }
 738 }
 739
 740 bool
 741 nir_cursors_equal(nir_cursor a, nir_cursor b)
 742 {
 743    /* Reduced cursors should be unique */
 744    a = reduce_cursor(a);
 745    b = reduce_cursor(b);
 746
 747    return a.block == b.block && a.option == b.option;
 748 }
 749
 750 static bool
 751 add_use_cb(nir_src *src, void *state)
 752 {
 753    nir_instr *instr = state;
 754
 755    src->parent_instr = instr;
 756    list_addtail(&src->use_link,
 757                 src->is_ssa ? &src->ssa->uses : &src->reg.reg->uses);
 758
 759    return true;
 760 }
 761
 762 static bool
 763 add_ssa_def_cb(nir_ssa_def *def, void *state)
 764 {
 765    nir_instr *instr = state;
 766
 767    if (instr->block && def->index == UINT_MAX) {
 768       nir_function_impl *impl =
 769          nir_cf_node_get_function(&instr->block->cf_node);
 770
 771       def->index = impl->ssa_alloc++;
 772    }
 773
 774    return true;
 775 }
 776
 777 static bool
 778 add_reg_def_cb(nir_dest *dest, void *state)
 779 {
 780    nir_instr *instr = state;
 781
 782    if (!dest->is_ssa) {
 783       dest->reg.parent_instr = instr;
 784       list_addtail(&dest->reg.def_link, &dest->reg.reg->defs);
 785    }
 786
 787    return true;
 788 }
 789
 790 static void
 791 add_defs_uses(nir_instr *instr)
 792 {
 793    nir_foreach_src(instr, add_use_cb, instr);
 794    nir_foreach_dest(instr, add_reg_def_cb, instr);
 795    nir_foreach_ssa_def(instr, add_ssa_def_cb, instr);
 796 }
 797
 798 void
 799 nir_instr_insert(nir_cursor cursor, nir_instr *instr)
 800 {
 801    switch (cursor.option) {
 802    case nir_cursor_before_block:
 803       /* Only allow inserting jumps into empty blocks. */
 804       if (instr->type == nir_instr_type_jump)
 805          assert(exec_list_is_empty(&cursor.block->instr_list));
 806
 807       instr->block = cursor.block;
 808       add_defs_uses(instr);
 809       exec_list_push_head(&cursor.block->instr_list, &instr->node);
 810       break;
 811    case nir_cursor_after_block: {
 812       /* Inserting instructions after a jump is illegal. */
 813       nir_instr *last = nir_block_last_instr(cursor.block);
 814       assert(last == NULL || last->type != nir_instr_type_jump);
 815       (void) last;
 816
 817       instr->block = cursor.block;
 818       add_defs_uses(instr);
 819       exec_list_push_tail(&cursor.block->instr_list, &instr->node);
 820       break;
 821    }
 822    case nir_cursor_before_instr:
 823       assert(instr->type != nir_instr_type_jump);
 824       instr->block = cursor.instr->block;
 825       add_defs_uses(instr);
 826       exec_node_insert_node_before(&cursor.instr->node, &instr->node);
 827       break;
 828    case nir_cursor_after_instr:
 829       /* Inserting instructions after a jump is illegal. */
 830       assert(cursor.instr->type != nir_instr_type_jump);
 831
 832       /* Only allow inserting jumps at the end of the block. */
 833       if (instr->type == nir_instr_type_jump)
 834          assert(cursor.instr == nir_block_last_instr(cursor.instr->block));
 835
 836       instr->block = cursor.instr->block;
 837       add_defs_uses(instr);
 838       exec_node_insert_after(&cursor.instr->node, &instr->node);
 839       break;
 840    }
 841
 842    if (instr->type == nir_instr_type_jump)
 843       nir_handle_add_jump(instr->block);
 844 }
 845
 846 static bool
 847 src_is_valid(const nir_src *src)
 848 {
 849    return src->is_ssa ? (src->ssa != NULL) : (src->reg.reg != NULL);
 850 }
 851
 852 static bool
 853 remove_use_cb(nir_src *src, void *state)
 854 {
 855    (void) state;
 856
 857    if (src_is_valid(src))
 858       list_del(&src->use_link);
 859
 860    return true;
 861 }
 862
 863 static bool
 864 remove_def_cb(nir_dest *dest, void *state)
 865 {
 866    (void) state;
 867
 868    if (!dest->is_ssa)
 869       list_del(&dest->reg.def_link);
 870
 871    return true;
 872 }
 873
 874 static void
 875 remove_defs_uses(nir_instr *instr)
 876 {
 877    nir_foreach_dest(instr, remove_def_cb, instr);
 878    nir_foreach_src(instr, remove_use_cb, instr);
 879 }
 880
 881 void nir_instr_remove_v(nir_instr *instr)
 882 {
 883    remove_defs_uses(instr);
 884    exec_node_remove(&instr->node);
 885
 886    if (instr->type == nir_instr_type_jump) {
 887       nir_jump_instr *jump_instr = nir_instr_as_jump(instr);
 888       nir_handle_remove_jump(instr->block, jump_instr->type);
 889    }
 890 }
 891
 892 /*@}*/
 893
 894 void
 895 nir_index_local_regs(nir_function_impl *impl)
 896 {
 897    unsigned index = 0;
 898    foreach_list_typed(nir_register, reg, node, &impl->registers) {
 899       reg->index = index++;
 900    }
 901    impl->reg_alloc = index;
 902 }
 903
 904 void
 905 nir_index_global_regs(nir_shader *shader)
 906 {
 907    unsigned index = 0;
 908    foreach_list_typed(nir_register, reg, node, &shader->registers) {
 909       reg->index = index++;
 910    }
 911    shader->reg_alloc = index;
 912 }
 913
 914 static bool
 915 visit_alu_dest(nir_alu_instr *instr, nir_foreach_dest_cb cb, void *state)
 916 {
 917    return cb(&instr->dest.dest, state);
 918 }
 919
 920 static bool
 921 visit_deref_dest(nir_deref_instr *instr, nir_foreach_dest_cb cb, void *state)
 922 {
 923    return cb(&instr->dest, state);
 924 }
 925
 926 static bool
 927 visit_intrinsic_dest(nir_intrinsic_instr *instr, nir_foreach_dest_cb cb,
 928                      void *state)
 929 {
 930    if (nir_intrinsic_infos[instr->intrinsic].has_dest)
 931       return cb(&instr->dest, state);
 932
 933    return true;
 934 }
 935
 936 static bool
 937 visit_texture_dest(nir_tex_instr *instr, nir_foreach_dest_cb cb,
 938                    void *state)
 939 {
 940    return cb(&instr->dest, state);
 941 }
 942
 943 static bool
 944 visit_phi_dest(nir_phi_instr *instr, nir_foreach_dest_cb cb, void *state)
 945 {
 946    return cb(&instr->dest, state);
 947 }
 948
 949 static bool
 950 visit_parallel_copy_dest(nir_parallel_copy_instr *instr,
 951                          nir_foreach_dest_cb cb, void *state)
 952 {
 953    nir_foreach_parallel_copy_entry(entry, instr) {
 954       if (!cb(&entry->dest, state))
 955          return false;
 956    }
 957
 958    return true;
 959 }
 960
 961 bool
 962 nir_foreach_dest(nir_instr *instr, nir_foreach_dest_cb cb, void *state)
 963 {
 964    switch (instr->type) {
 965    case nir_instr_type_alu:
 966       return visit_alu_dest(nir_instr_as_alu(instr), cb, state);
 967    case nir_instr_type_deref:
 968       return visit_deref_dest(nir_instr_as_deref(instr), cb, state);
 969    case nir_instr_type_intrinsic:
 970       return visit_intrinsic_dest(nir_instr_as_intrinsic(instr), cb, state);
 971    case nir_instr_type_tex:
 972       return visit_texture_dest(nir_instr_as_tex(instr), cb, state);
 973    case nir_instr_type_phi:
 974       return visit_phi_dest(nir_instr_as_phi(instr), cb, state);
 975    case nir_instr_type_parallel_copy:
 976       return visit_parallel_copy_dest(nir_instr_as_parallel_copy(instr),
 977                                       cb, state);
 978
 979    case nir_instr_type_load_const:
 980    case nir_instr_type_ssa_undef:
 981    case nir_instr_type_call:
 982    case nir_instr_type_jump:
 983       break;
 984
 985    default:
 986       unreachable("Invalid instruction type");
 987       break;
 988    }
 989
 990    return true;
 991 }
 992
 993 struct foreach_ssa_def_state {
 994    nir_foreach_ssa_def_cb cb;
 995    void *client_state;
 996 };
 997
 998 static inline bool
 999 nir_ssa_def_visitor(nir_dest *dest, void *void_state)
1000 {
1001    struct foreach_ssa_def_state *state = void_state;
1002
1003    if (dest->is_ssa)
1004       return state->cb(&dest->ssa, state->client_state);
1005    else
1006       return true;
1007 }
1008
1009 bool
1010 nir_foreach_ssa_def(nir_instr *instr, nir_foreach_ssa_def_cb cb, void *state)
1011 {
1012    switch (instr->type) {
1013    case nir_instr_type_alu:
1014    case nir_instr_type_deref:
1015    case nir_instr_type_tex:
1016    case nir_instr_type_intrinsic:
1017    case nir_instr_type_phi:
1018    case nir_instr_type_parallel_copy: {
1019       struct foreach_ssa_def_state foreach_state = {cb, state};
1020       return nir_foreach_dest(instr, nir_ssa_def_visitor, &foreach_state);
1021    }
1022
1023    case nir_instr_type_load_const:
1024       return cb(&nir_instr_as_load_const(instr)->def, state);
1025    case nir_instr_type_ssa_undef:
1026       return cb(&nir_instr_as_ssa_undef(instr)->def, state);
1027    case nir_instr_type_call:
1028    case nir_instr_type_jump:
1029       return true;
1030    default:
1031       unreachable("Invalid instruction type");
1032    }
1033 }
1034
1035 static bool
1036 visit_src(nir_src *src, nir_foreach_src_cb cb, void *state)
1037 {
1038    if (!cb(src, state))
1039       return false;
1040    if (!src->is_ssa && src->reg.indirect)
1041       return cb(src->reg.indirect, state);
1042    return true;
1043 }
1044
1045 static bool
1046 visit_alu_src(nir_alu_instr *instr, nir_foreach_src_cb cb, void *state)
1047 {
1048    for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1049       if (!visit_src(&instr->src[i].src, cb, state))
1050          return false;
1051
1052    return true;
1053 }
1054
1055 static bool
1056 visit_deref_instr_src(nir_deref_instr *instr,
1057                       nir_foreach_src_cb cb, void *state)
1058 {
1059    if (instr->deref_type != nir_deref_type_var) {
1060       if (!visit_src(&instr->parent, cb, state))
1061          return false;
1062    }
1063
1064    if (instr->deref_type == nir_deref_type_array) {
1065       if (!visit_src(&instr->arr.index, cb, state))
1066          return false;
1067    }
1068
1069    return true;
1070 }
1071
1072 static bool
1073 visit_tex_src(nir_tex_instr *instr, nir_foreach_src_cb cb, void *state)
1074 {
1075    for (unsigned i = 0; i < instr->num_srcs; i++) {
1076       if (!visit_src(&instr->src[i].src, cb, state))
1077          return false;
1078    }
1079
1080    return true;
1081 }
1082
1083 static bool
1084 visit_intrinsic_src(nir_intrinsic_instr *instr, nir_foreach_src_cb cb,
1085                     void *state)
1086 {
1087    unsigned num_srcs = nir_intrinsic_infos[instr->intrinsic].num_srcs;
1088    for (unsigned i = 0; i < num_srcs; i++) {
1089       if (!visit_src(&instr->src[i], cb, state))
1090          return false;
1091    }
1092
1093    return true;
1094 }
1095
1096 static bool
1097 visit_call_src(nir_call_instr *instr, nir_foreach_src_cb cb, void *state)
1098 {
1099    for (unsigned i = 0; i < instr->num_params; i++) {
1100       if (!visit_src(&instr->params[i], cb, state))
1101          return false;
1102    }
1103
1104    return true;
1105 }
1106
1107 static bool
1108 visit_phi_src(nir_phi_instr *instr, nir_foreach_src_cb cb, void *state)
1109 {
1110    nir_foreach_phi_src(src, instr) {
1111       if (!visit_src(&src->src, cb, state))
1112          return false;
1113    }
1114
1115    return true;
1116 }
1117
1118 static bool
1119 visit_parallel_copy_src(nir_parallel_copy_instr *instr,
1120                         nir_foreach_src_cb cb, void *state)
1121 {
1122    nir_foreach_parallel_copy_entry(entry, instr) {
1123       if (!visit_src(&entry->src, cb, state))
1124          return false;
1125    }
1126
1127    return true;
1128 }
1129
1130 typedef struct {
1131    void *state;
1132    nir_foreach_src_cb cb;
1133 } visit_dest_indirect_state;
1134
1135 static bool
1136 visit_dest_indirect(nir_dest *dest, void *_state)
1137 {
1138    visit_dest_indirect_state *state = (visit_dest_indirect_state *) _state;
1139
1140    if (!dest->is_ssa && dest->reg.indirect)
1141       return state->cb(dest->reg.indirect, state->state);
1142
1143    return true;
1144 }
1145
1146 bool
1147 nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
1148 {
1149    switch (instr->type) {
1150    case nir_instr_type_alu:
1151       if (!visit_alu_src(nir_instr_as_alu(instr), cb, state))
1152          return false;
1153       break;
1154    case nir_instr_type_deref:
1155       if (!visit_deref_instr_src(nir_instr_as_deref(instr), cb, state))
1156          return false;
1157       break;
1158    case nir_instr_type_intrinsic:
1159       if (!visit_intrinsic_src(nir_instr_as_intrinsic(instr), cb, state))
1160          return false;
1161       break;
1162    case nir_instr_type_tex:
1163       if (!visit_tex_src(nir_instr_as_tex(instr), cb, state))
1164          return false;
1165       break;
1166    case nir_instr_type_call:
1167       if (!visit_call_src(nir_instr_as_call(instr), cb, state))
1168          return false;
1169       break;
1170    case nir_instr_type_load_const:
1171       /* Constant load instructions have no regular sources */
1172       break;
1173    case nir_instr_type_phi:
1174       if (!visit_phi_src(nir_instr_as_phi(instr), cb, state))
1175          return false;
1176       break;
1177    case nir_instr_type_parallel_copy:
1178       if (!visit_parallel_copy_src(nir_instr_as_parallel_copy(instr),
1179                                    cb, state))
1180          return false;
1181       break;
1182    case nir_instr_type_jump:
1183    case nir_instr_type_ssa_undef:
1184       return true;
1185
1186    default:
1187       unreachable("Invalid instruction type");
1188       break;
1189    }
1190
1191    visit_dest_indirect_state dest_state;
1192    dest_state.state = state;
1193    dest_state.cb = cb;
1194    return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
1195 }
1196
1197 nir_const_value *
1198 nir_src_as_const_value(nir_src src)
1199 {
1200    if (!src.is_ssa)
1201       return NULL;
1202
1203    if (src.ssa->parent_instr->type != nir_instr_type_load_const)
1204       return NULL;
1205
1206    nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
1207
1208    return &load->value;
1209 }
1210
1211 /**
1212  * Returns true if the source is known to be dynamically uniform. Otherwise it
1213  * returns false which means it may or may not be dynamically uniform but it
1214  * can't be determined.
1215  */
1216 bool
1217 nir_src_is_dynamically_uniform(nir_src src)
1218 {
1219    if (!src.is_ssa)
1220       return false;
1221
1222    /* Constants are trivially dynamically uniform */
1223    if (src.ssa->parent_instr->type == nir_instr_type_load_const)
1224       return true;
1225
1226    /* As are uniform variables */
1227    if (src.ssa->parent_instr->type == nir_instr_type_intrinsic) {
1228       nir_intrinsic_instr *intr = nir_instr_as_intrinsic(src.ssa->parent_instr);
1229
1230       if (intr->intrinsic == nir_intrinsic_load_uniform)
1231          return true;
1232    }
1233
1234    /* XXX: this could have many more tests, such as when a sampler function is
1235     * called with dynamically uniform arguments.
1236     */
1237    return false;
1238 }
1239
1240 static void
1241 src_remove_all_uses(nir_src *src)
1242 {
1243    for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1244       if (!src_is_valid(src))
1245          continue;
1246
1247       list_del(&src->use_link);
1248    }
1249 }
1250
1251 static void
1252 src_add_all_uses(nir_src *src, nir_instr *parent_instr, nir_if *parent_if)
1253 {
1254    for (; src; src = src->is_ssa ? NULL : src->reg.indirect) {
1255       if (!src_is_valid(src))
1256          continue;
1257
1258       if (parent_instr) {
1259          src->parent_instr = parent_instr;
1260          if (src->is_ssa)
1261             list_addtail(&src->use_link, &src->ssa->uses);
1262          else
1263             list_addtail(&src->use_link, &src->reg.reg->uses);
1264       } else {
1265          assert(parent_if);
1266          src->parent_if = parent_if;
1267          if (src->is_ssa)
1268             list_addtail(&src->use_link, &src->ssa->if_uses);
1269          else
1270             list_addtail(&src->use_link, &src->reg.reg->if_uses);
1271       }
1272    }
1273 }
1274
1275 void
1276 nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src)
1277 {
1278    assert(!src_is_valid(src) || src->parent_instr == instr);
1279
1280    src_remove_all_uses(src);
1281    *src = new_src;
1282    src_add_all_uses(src, instr, NULL);
1283 }
1284
1285 void
1286 nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src)
1287 {
1288    assert(!src_is_valid(dest) || dest->parent_instr == dest_instr);
1289
1290    src_remove_all_uses(dest);
1291    src_remove_all_uses(src);
1292    *dest = *src;
1293    *src = NIR_SRC_INIT;
1294    src_add_all_uses(dest, dest_instr, NULL);
1295 }
1296
1297 void
1298 nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src)
1299 {
1300    nir_src *src = &if_stmt->condition;
1301    assert(!src_is_valid(src) || src->parent_if == if_stmt);
1302
1303    src_remove_all_uses(src);
1304    *src = new_src;
1305    src_add_all_uses(src, NULL, if_stmt);
1306 }
1307
1308 void
1309 nir_instr_rewrite_dest(nir_instr *instr, nir_dest *dest, nir_dest new_dest)
1310 {
1311    if (dest->is_ssa) {
1312       /* We can only overwrite an SSA destination if it has no uses. */
1313       assert(list_empty(&dest->ssa.uses) && list_empty(&dest->ssa.if_uses));
1314    } else {
1315       list_del(&dest->reg.def_link);
1316       if (dest->reg.indirect)
1317          src_remove_all_uses(dest->reg.indirect);
1318    }
1319
1320    /* We can't re-write with an SSA def */
1321    assert(!new_dest.is_ssa);
1322
1323    nir_dest_copy(dest, &new_dest, instr);
1324
1325    dest->reg.parent_instr = instr;
1326    list_addtail(&dest->reg.def_link, &new_dest.reg.reg->defs);
1327
1328    if (dest->reg.indirect)
1329       src_add_all_uses(dest->reg.indirect, instr, NULL);
1330 }
1331
1332 /* note: does *not* take ownership of 'name' */
1333 void
1334 nir_ssa_def_init(nir_instr *instr, nir_ssa_def *def,
1335                  unsigned num_components,
1336                  unsigned bit_size, const char *name)
1337 {
1338    def->name = ralloc_strdup(instr, name);
1339    def->parent_instr = instr;
1340    list_inithead(&def->uses);
1341    list_inithead(&def->if_uses);
1342    def->num_components = num_components;
1343    def->bit_size = bit_size;
1344
1345    if (instr->block) {
1346       nir_function_impl *impl =
1347          nir_cf_node_get_function(&instr->block->cf_node);
1348
1349       def->index = impl->ssa_alloc++;
1350    } else {
1351       def->index = UINT_MAX;
1352    }
1353 }
1354
1355 /* note: does *not* take ownership of 'name' */
1356 void
1357 nir_ssa_dest_init(nir_instr *instr, nir_dest *dest,
1358                  unsigned num_components, unsigned bit_size,
1359                  const char *name)
1360 {
1361    dest->is_ssa = true;
1362    nir_ssa_def_init(instr, &dest->ssa, num_components, bit_size, name);
1363 }
1364
1365 void
1366 nir_ssa_def_rewrite_uses(nir_ssa_def *def, nir_src new_src)
1367 {
1368    assert(!new_src.is_ssa || def != new_src.ssa);
1369
1370    nir_foreach_use_safe(use_src, def)
1371       nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1372
1373    nir_foreach_if_use_safe(use_src, def)
1374       nir_if_rewrite_condition(use_src->parent_if, new_src);
1375 }
1376
1377 static bool
1378 is_instr_between(nir_instr *start, nir_instr *end, nir_instr *between)
1379 {
1380    assert(start->block == end->block);
1381
1382    if (between->block != start->block)
1383       return false;
1384
1385    /* Search backwards looking for "between" */
1386    while (start != end) {
1387       if (between == end)
1388          return true;
1389
1390       end = nir_instr_prev(end);
1391       assert(end);
1392    }
1393
1394    return false;
1395 }
1396
1397 /* Replaces all uses of the given SSA def with the given source but only if
1398  * the use comes after the after_me instruction.  This can be useful if you
1399  * are emitting code to fix up the result of some instruction: you can freely
1400  * use the result in that code and then call rewrite_uses_after and pass the
1401  * last fixup instruction as after_me and it will replace all of the uses you
1402  * want without touching the fixup code.
1403  *
1404  * This function assumes that after_me is in the same block as
1405  * def->parent_instr and that after_me comes after def->parent_instr.
1406  */
1407 void
1408 nir_ssa_def_rewrite_uses_after(nir_ssa_def *def, nir_src new_src,
1409                                nir_instr *after_me)
1410 {
1411    assert(!new_src.is_ssa || def != new_src.ssa);
1412
1413    nir_foreach_use_safe(use_src, def) {
1414       assert(use_src->parent_instr != def->parent_instr);
1415       /* Since def already dominates all of its uses, the only way a use can
1416        * not be dominated by after_me is if it is between def and after_me in
1417        * the instruction list.
1418        */
1419       if (!is_instr_between(def->parent_instr, after_me, use_src->parent_instr))
1420          nir_instr_rewrite_src(use_src->parent_instr, use_src, new_src);
1421    }
1422
1423    nir_foreach_if_use_safe(use_src, def)
1424       nir_if_rewrite_condition(use_src->parent_if, new_src);
1425 }
1426
1427 nir_component_mask_t
1428 nir_ssa_def_components_read(const nir_ssa_def *def)
1429 {
1430    nir_component_mask_t read_mask = 0;
1431    nir_foreach_use(use, def) {
1432       if (use->parent_instr->type == nir_instr_type_alu) {
1433          nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
1434          nir_alu_src *alu_src = exec_node_data(nir_alu_src, use, src);
1435          int src_idx = alu_src - &alu->src[0];
1436          assert(src_idx >= 0 && src_idx < nir_op_infos[alu->op].num_inputs);
1437
1438          for (unsigned c = 0; c < NIR_MAX_VEC_COMPONENTS; c++) {
1439             if (!nir_alu_instr_channel_used(alu, src_idx, c))
1440                continue;
1441
1442             read_mask |= (1 << alu_src->swizzle[c]);
1443          }
1444       } else {
1445          return (1 << def->num_components) - 1;
1446       }
1447    }
1448
1449    return read_mask;
1450 }
1451
1452 nir_block *
1453 nir_block_cf_tree_next(nir_block *block)
1454 {
1455    if (block == NULL) {
1456       /* nir_foreach_block_safe() will call this function on a NULL block
1457        * after the last iteration, but it won't use the result so just return
1458        * NULL here.
1459        */
1460       return NULL;
1461    }
1462
1463    nir_cf_node *cf_next = nir_cf_node_next(&block->cf_node);
1464    if (cf_next)
1465       return nir_cf_node_cf_tree_first(cf_next);
1466
1467    nir_cf_node *parent = block->cf_node.parent;
1468
1469    switch (parent->type) {
1470    case nir_cf_node_if: {
1471       /* Are we at the end of the if? Go to the beginning of the else */
1472       nir_if *if_stmt = nir_cf_node_as_if(parent);
1473       if (block == nir_if_last_then_block(if_stmt))
1474          return nir_if_first_else_block(if_stmt);
1475
1476       assert(block == nir_if_last_else_block(if_stmt));
1477       /* fall through */
1478    }
1479
1480    case nir_cf_node_loop:
1481       return nir_cf_node_as_block(nir_cf_node_next(parent));
1482
1483    case nir_cf_node_function:
1484       return NULL;
1485
1486    default:
1487       unreachable("unknown cf node type");
1488    }
1489 }
1490
1491 nir_block *
1492 nir_block_cf_tree_prev(nir_block *block)
1493 {
1494    if (block == NULL) {
1495       /* do this for consistency with nir_block_cf_tree_next() */
1496       return NULL;
1497    }
1498
1499    nir_cf_node *cf_prev = nir_cf_node_prev(&block->cf_node);
1500    if (cf_prev)
1501       return nir_cf_node_cf_tree_last(cf_prev);
1502
1503    nir_cf_node *parent = block->cf_node.parent;
1504
1505    switch (parent->type) {
1506    case nir_cf_node_if: {
1507       /* Are we at the beginning of the else? Go to the end of the if */
1508       nir_if *if_stmt = nir_cf_node_as_if(parent);
1509       if (block == nir_if_first_else_block(if_stmt))
1510          return nir_if_last_then_block(if_stmt);
1511
1512       assert(block == nir_if_first_then_block(if_stmt));
1513       /* fall through */
1514    }
1515
1516    case nir_cf_node_loop:
1517       return nir_cf_node_as_block(nir_cf_node_prev(parent));
1518
1519    case nir_cf_node_function:
1520       return NULL;
1521
1522    default:
1523       unreachable("unknown cf node type");
1524    }
1525 }
1526
1527 nir_block *nir_cf_node_cf_tree_first(nir_cf_node *node)
1528 {
1529    switch (node->type) {
1530    case nir_cf_node_function: {
1531       nir_function_impl *impl = nir_cf_node_as_function(node);
1532       return nir_start_block(impl);
1533    }
1534
1535    case nir_cf_node_if: {
1536       nir_if *if_stmt = nir_cf_node_as_if(node);
1537       return nir_if_first_then_block(if_stmt);
1538    }
1539
1540    case nir_cf_node_loop: {
1541       nir_loop *loop = nir_cf_node_as_loop(node);
1542       return nir_loop_first_block(loop);
1543    }
1544
1545    case nir_cf_node_block: {
1546       return nir_cf_node_as_block(node);
1547    }
1548
1549    default:
1550       unreachable("unknown node type");
1551    }
1552 }
1553
1554 nir_block *nir_cf_node_cf_tree_last(nir_cf_node *node)
1555 {
1556    switch (node->type) {
1557    case nir_cf_node_function: {
1558       nir_function_impl *impl = nir_cf_node_as_function(node);
1559       return nir_impl_last_block(impl);
1560    }
1561
1562    case nir_cf_node_if: {
1563       nir_if *if_stmt = nir_cf_node_as_if(node);
1564       return nir_if_last_else_block(if_stmt);
1565    }
1566
1567    case nir_cf_node_loop: {
1568       nir_loop *loop = nir_cf_node_as_loop(node);
1569       return nir_loop_last_block(loop);
1570    }
1571
1572    case nir_cf_node_block: {
1573       return nir_cf_node_as_block(node);
1574    }
1575
1576    default:
1577       unreachable("unknown node type");
1578    }
1579 }
1580
1581 nir_block *nir_cf_node_cf_tree_next(nir_cf_node *node)
1582 {
1583    if (node->type == nir_cf_node_block)
1584       return nir_block_cf_tree_next(nir_cf_node_as_block(node));
1585    else if (node->type == nir_cf_node_function)
1586       return NULL;
1587    else
1588       return nir_cf_node_as_block(nir_cf_node_next(node));
1589 }
1590
1591 nir_if *
1592 nir_block_get_following_if(nir_block *block)
1593 {
1594    if (exec_node_is_tail_sentinel(&block->cf_node.node))
1595       return NULL;
1596
1597    if (nir_cf_node_is_last(&block->cf_node))
1598       return NULL;
1599
1600    nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1601
1602    if (next_node->type != nir_cf_node_if)
1603       return NULL;
1604
1605    return nir_cf_node_as_if(next_node);
1606 }
1607
1608 nir_loop *
1609 nir_block_get_following_loop(nir_block *block)
1610 {
1611    if (exec_node_is_tail_sentinel(&block->cf_node.node))
1612       return NULL;
1613
1614    if (nir_cf_node_is_last(&block->cf_node))
1615       return NULL;
1616
1617    nir_cf_node *next_node = nir_cf_node_next(&block->cf_node);
1618
1619    if (next_node->type != nir_cf_node_loop)
1620       return NULL;
1621
1622    return nir_cf_node_as_loop(next_node);
1623 }
1624
1625 void
1626 nir_index_blocks(nir_function_impl *impl)
1627 {
1628    unsigned index = 0;
1629
1630    if (impl->valid_metadata & nir_metadata_block_index)
1631       return;
1632
1633    nir_foreach_block(block, impl) {
1634       block->index = index++;
1635    }
1636
1637    impl->num_blocks = index;
1638 }
1639
1640 static bool
1641 index_ssa_def_cb(nir_ssa_def *def, void *state)
1642 {
1643    unsigned *index = (unsigned *) state;
1644    def->index = (*index)++;
1645
1646    return true;
1647 }
1648
1649 /**
1650  * The indices are applied top-to-bottom which has the very nice property
1651  * that, if A dominates B, then A->index <= B->index.
1652  */
1653 void
1654 nir_index_ssa_defs(nir_function_impl *impl)
1655 {
1656    unsigned index = 0;
1657
1658    nir_foreach_block(block, impl) {
1659       nir_foreach_instr(instr, block)
1660          nir_foreach_ssa_def(instr, index_ssa_def_cb, &index);
1661    }
1662
1663    impl->ssa_alloc = index;
1664 }
1665
1666 /**
1667  * The indices are applied top-to-bottom which has the very nice property
1668  * that, if A dominates B, then A->index <= B->index.
1669  */
1670 unsigned
1671 nir_index_instrs(nir_function_impl *impl)
1672 {
1673    unsigned index = 0;
1674
1675    nir_foreach_block(block, impl) {
1676       nir_foreach_instr(instr, block)
1677          instr->index = index++;
1678    }
1679
1680    return index;
1681 }
1682
1683 nir_intrinsic_op
1684 nir_intrinsic_from_system_value(gl_system_value val)
1685 {
1686    switch (val) {
1687    case SYSTEM_VALUE_VERTEX_ID:
1688       return nir_intrinsic_load_vertex_id;
1689    case SYSTEM_VALUE_INSTANCE_ID:
1690       return nir_intrinsic_load_instance_id;
1691    case SYSTEM_VALUE_DRAW_ID:
1692       return nir_intrinsic_load_draw_id;
1693    case SYSTEM_VALUE_BASE_INSTANCE:
1694       return nir_intrinsic_load_base_instance;
1695    case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
1696       return nir_intrinsic_load_vertex_id_zero_base;
1697    case SYSTEM_VALUE_IS_INDEXED_DRAW:
1698       return nir_intrinsic_load_is_indexed_draw;
1699    case SYSTEM_VALUE_FIRST_VERTEX:
1700       return nir_intrinsic_load_first_vertex;
1701    case SYSTEM_VALUE_BASE_VERTEX:
1702       return nir_intrinsic_load_base_vertex;
1703    case SYSTEM_VALUE_INVOCATION_ID:
1704       return nir_intrinsic_load_invocation_id;
1705    case SYSTEM_VALUE_FRAG_COORD:
1706       return nir_intrinsic_load_frag_coord;
1707    case SYSTEM_VALUE_FRONT_FACE:
1708       return nir_intrinsic_load_front_face;
1709    case SYSTEM_VALUE_SAMPLE_ID:
1710       return nir_intrinsic_load_sample_id;
1711    case SYSTEM_VALUE_SAMPLE_POS:
1712       return nir_intrinsic_load_sample_pos;
1713    case SYSTEM_VALUE_SAMPLE_MASK_IN:
1714       return nir_intrinsic_load_sample_mask_in;
1715    case SYSTEM_VALUE_LOCAL_INVOCATION_ID:
1716       return nir_intrinsic_load_local_invocation_id;
1717    case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX:
1718       return nir_intrinsic_load_local_invocation_index;
1719    case SYSTEM_VALUE_WORK_GROUP_ID:
1720       return nir_intrinsic_load_work_group_id;
1721    case SYSTEM_VALUE_NUM_WORK_GROUPS:
1722       return nir_intrinsic_load_num_work_groups;
1723    case SYSTEM_VALUE_PRIMITIVE_ID:
1724       return nir_intrinsic_load_primitive_id;
1725    case SYSTEM_VALUE_TESS_COORD:
1726       return nir_intrinsic_load_tess_coord;
1727    case SYSTEM_VALUE_TESS_LEVEL_OUTER:
1728       return nir_intrinsic_load_tess_level_outer;
1729    case SYSTEM_VALUE_TESS_LEVEL_INNER:
1730       return nir_intrinsic_load_tess_level_inner;
1731    case SYSTEM_VALUE_VERTICES_IN:
1732       return nir_intrinsic_load_patch_vertices_in;
1733    case SYSTEM_VALUE_HELPER_INVOCATION:
1734       return nir_intrinsic_load_helper_invocation;
1735    case SYSTEM_VALUE_VIEW_INDEX:
1736       return nir_intrinsic_load_view_index;
1737    case SYSTEM_VALUE_SUBGROUP_SIZE:
1738       return nir_intrinsic_load_subgroup_size;
1739    case SYSTEM_VALUE_SUBGROUP_INVOCATION:
1740       return nir_intrinsic_load_subgroup_invocation;
1741    case SYSTEM_VALUE_SUBGROUP_EQ_MASK:
1742       return nir_intrinsic_load_subgroup_eq_mask;
1743    case SYSTEM_VALUE_SUBGROUP_GE_MASK:
1744       return nir_intrinsic_load_subgroup_ge_mask;
1745    case SYSTEM_VALUE_SUBGROUP_GT_MASK:
1746       return nir_intrinsic_load_subgroup_gt_mask;
1747    case SYSTEM_VALUE_SUBGROUP_LE_MASK:
1748       return nir_intrinsic_load_subgroup_le_mask;
1749    case SYSTEM_VALUE_SUBGROUP_LT_MASK:
1750       return nir_intrinsic_load_subgroup_lt_mask;
1751    case SYSTEM_VALUE_NUM_SUBGROUPS:
1752       return nir_intrinsic_load_num_subgroups;
1753    case SYSTEM_VALUE_SUBGROUP_ID:
1754       return nir_intrinsic_load_subgroup_id;
1755    case SYSTEM_VALUE_LOCAL_GROUP_SIZE:
1756       return nir_intrinsic_load_local_group_size;
1757    case SYSTEM_VALUE_GLOBAL_INVOCATION_ID:
1758       return nir_intrinsic_load_global_invocation_id;
1759    case SYSTEM_VALUE_WORK_DIM:
1760       return nir_intrinsic_load_work_dim;
1761    default:
1762       unreachable("system value does not directly correspond to intrinsic");
1763    }
1764 }
1765
1766 gl_system_value
1767 nir_system_value_from_intrinsic(nir_intrinsic_op intrin)
1768 {
1769    switch (intrin) {
1770    case nir_intrinsic_load_vertex_id:
1771       return SYSTEM_VALUE_VERTEX_ID;
1772    case nir_intrinsic_load_instance_id:
1773       return SYSTEM_VALUE_INSTANCE_ID;
1774    case nir_intrinsic_load_draw_id:
1775       return SYSTEM_VALUE_DRAW_ID;
1776    case nir_intrinsic_load_base_instance:
1777       return SYSTEM_VALUE_BASE_INSTANCE;
1778    case nir_intrinsic_load_vertex_id_zero_base:
1779       return SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1780    case nir_intrinsic_load_first_vertex:
1781       return SYSTEM_VALUE_FIRST_VERTEX;
1782    case nir_intrinsic_load_is_indexed_draw:
1783       return SYSTEM_VALUE_IS_INDEXED_DRAW;
1784    case nir_intrinsic_load_base_vertex:
1785       return SYSTEM_VALUE_BASE_VERTEX;
1786    case nir_intrinsic_load_invocation_id:
1787       return SYSTEM_VALUE_INVOCATION_ID;
1788    case nir_intrinsic_load_frag_coord:
1789       return SYSTEM_VALUE_FRAG_COORD;
1790    case nir_intrinsic_load_front_face:
1791       return SYSTEM_VALUE_FRONT_FACE;
1792    case nir_intrinsic_load_sample_id:
1793       return SYSTEM_VALUE_SAMPLE_ID;
1794    case nir_intrinsic_load_sample_pos:
1795       return SYSTEM_VALUE_SAMPLE_POS;
1796    case nir_intrinsic_load_sample_mask_in:
1797       return SYSTEM_VALUE_SAMPLE_MASK_IN;
1798    case nir_intrinsic_load_local_invocation_id:
1799       return SYSTEM_VALUE_LOCAL_INVOCATION_ID;
1800    case nir_intrinsic_load_local_invocation_index:
1801       return SYSTEM_VALUE_LOCAL_INVOCATION_INDEX;
1802    case nir_intrinsic_load_num_work_groups:
1803       return SYSTEM_VALUE_NUM_WORK_GROUPS;
1804    case nir_intrinsic_load_work_group_id:
1805       return SYSTEM_VALUE_WORK_GROUP_ID;
1806    case nir_intrinsic_load_primitive_id:
1807       return SYSTEM_VALUE_PRIMITIVE_ID;
1808    case nir_intrinsic_load_tess_coord:
1809       return SYSTEM_VALUE_TESS_COORD;
1810    case nir_intrinsic_load_tess_level_outer:
1811       return SYSTEM_VALUE_TESS_LEVEL_OUTER;
1812    case nir_intrinsic_load_tess_level_inner:
1813       return SYSTEM_VALUE_TESS_LEVEL_INNER;
1814    case nir_intrinsic_load_patch_vertices_in:
1815       return SYSTEM_VALUE_VERTICES_IN;
1816    case nir_intrinsic_load_helper_invocation:
1817       return SYSTEM_VALUE_HELPER_INVOCATION;
1818    case nir_intrinsic_load_view_index:
1819       return SYSTEM_VALUE_VIEW_INDEX;
1820    case nir_intrinsic_load_subgroup_size:
1821       return SYSTEM_VALUE_SUBGROUP_SIZE;
1822    case nir_intrinsic_load_subgroup_invocation:
1823       return SYSTEM_VALUE_SUBGROUP_INVOCATION;
1824    case nir_intrinsic_load_subgroup_eq_mask:
1825       return SYSTEM_VALUE_SUBGROUP_EQ_MASK;
1826    case nir_intrinsic_load_subgroup_ge_mask:
1827       return SYSTEM_VALUE_SUBGROUP_GE_MASK;
1828    case nir_intrinsic_load_subgroup_gt_mask:
1829       return SYSTEM_VALUE_SUBGROUP_GT_MASK;
1830    case nir_intrinsic_load_subgroup_le_mask:
1831       return SYSTEM_VALUE_SUBGROUP_LE_MASK;
1832    case nir_intrinsic_load_subgroup_lt_mask:
1833       return SYSTEM_VALUE_SUBGROUP_LT_MASK;
1834    case nir_intrinsic_load_num_subgroups:
1835       return SYSTEM_VALUE_NUM_SUBGROUPS;
1836    case nir_intrinsic_load_subgroup_id:
1837       return SYSTEM_VALUE_SUBGROUP_ID;
1838    case nir_intrinsic_load_local_group_size:
1839       return SYSTEM_VALUE_LOCAL_GROUP_SIZE;
1840    case nir_intrinsic_load_global_invocation_id:
1841       return SYSTEM_VALUE_GLOBAL_INVOCATION_ID;
1842    default:
1843       unreachable("intrinsic doesn't produce a system value");
1844    }
1845 }