2 * Copyright © 2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "nir_builder.h"
26 #include "util/format_rgb9e5.h"
28 static inline nir_ssa_def
*
29 nir_shift(nir_builder
*b
, nir_ssa_def
*value
, int left_shift
)
32 return nir_ishl(b
, value
, nir_imm_int(b
, left_shift
));
33 else if (left_shift
< 0)
34 return nir_ushr(b
, value
, nir_imm_int(b
, -left_shift
));
39 static inline nir_ssa_def
*
40 nir_mask_shift(struct nir_builder
*b
, nir_ssa_def
*src
,
41 uint32_t mask
, int left_shift
)
43 return nir_shift(b
, nir_iand(b
, src
, nir_imm_int(b
, mask
)), left_shift
);
46 static inline nir_ssa_def
*
47 nir_mask_shift_or(struct nir_builder
*b
, nir_ssa_def
*dst
, nir_ssa_def
*src
,
48 uint32_t src_mask
, int src_left_shift
)
50 return nir_ior(b
, nir_mask_shift(b
, src
, src_mask
, src_left_shift
), dst
);
53 static inline nir_ssa_def
*
54 nir_format_mask_uvec(nir_builder
*b
, nir_ssa_def
*src
,
58 for (unsigned i
= 0; i
< src
->num_components
; i
++) {
60 mask
.u32
[i
] = (1u << bits
[i
]) - 1;
62 return nir_iand(b
, src
, nir_build_imm(b
, src
->num_components
, 32, mask
));
65 static inline nir_ssa_def
*
66 nir_format_sign_extend_ivec(nir_builder
*b
, nir_ssa_def
*src
,
69 assert(src
->num_components
<= 4);
70 nir_ssa_def
*comps
[4];
71 for (unsigned i
= 0; i
< src
->num_components
; i
++) {
72 nir_ssa_def
*shift
= nir_imm_int(b
, src
->bit_size
- bits
[i
]);
73 comps
[i
] = nir_ishr(b
, nir_ishl(b
, nir_channel(b
, src
, i
), shift
), shift
);
75 return nir_vec(b
, comps
, src
->num_components
);
79 static inline nir_ssa_def
*
80 nir_format_unpack_int(nir_builder
*b
, nir_ssa_def
*packed
,
81 const unsigned *bits
, unsigned num_components
,
84 assert(num_components
>= 1 && num_components
<= 4);
85 const unsigned bit_size
= packed
->bit_size
;
86 nir_ssa_def
*comps
[4];
88 if (bits
[0] >= bit_size
) {
89 assert(bits
[0] == bit_size
);
90 assert(num_components
== 1);
95 for (unsigned i
= 0; i
< num_components
; i
++) {
96 assert(bits
[i
] < bit_size
);
97 assert(offset
+ bits
[i
] <= bit_size
);
98 nir_ssa_def
*lshift
= nir_imm_int(b
, bit_size
- (offset
+ bits
[i
]));
99 nir_ssa_def
*rshift
= nir_imm_int(b
, bit_size
- bits
[i
]);
101 comps
[i
] = nir_ishr(b
, nir_ishl(b
, packed
, lshift
), rshift
);
103 comps
[i
] = nir_ushr(b
, nir_ishl(b
, packed
, lshift
), rshift
);
106 assert(offset
<= bit_size
);
108 return nir_vec(b
, comps
, num_components
);
111 static inline nir_ssa_def
*
112 nir_format_unpack_uint(nir_builder
*b
, nir_ssa_def
*packed
,
113 const unsigned *bits
, unsigned num_components
)
115 return nir_format_unpack_int(b
, packed
, bits
, num_components
, false);
118 static inline nir_ssa_def
*
119 nir_format_unpack_sint(nir_builder
*b
, nir_ssa_def
*packed
,
120 const unsigned *bits
, unsigned num_components
)
122 return nir_format_unpack_int(b
, packed
, bits
, num_components
, true);
125 static inline nir_ssa_def
*
126 nir_format_pack_uint_unmasked(nir_builder
*b
, nir_ssa_def
*color
,
127 const unsigned *bits
, unsigned num_components
)
129 assert(num_components
>= 1 && num_components
<= 4);
130 nir_ssa_def
*packed
= nir_imm_int(b
, 0);
132 for (unsigned i
= 0; i
< num_components
; i
++) {
133 packed
= nir_ior(b
, packed
, nir_shift(b
, nir_channel(b
, color
, i
),
137 assert(offset
<= packed
->bit_size
);
142 static inline nir_ssa_def
*
143 nir_format_pack_uint(nir_builder
*b
, nir_ssa_def
*color
,
144 const unsigned *bits
, unsigned num_components
)
146 return nir_format_pack_uint_unmasked(b
, nir_format_mask_uvec(b
, color
, bits
),
147 bits
, num_components
);
150 static inline nir_ssa_def
*
151 nir_format_bitcast_uvec_unmasked(nir_builder
*b
, nir_ssa_def
*src
,
152 unsigned src_bits
, unsigned dst_bits
)
154 assert(src
->bit_size
>= src_bits
&& src
->bit_size
>= dst_bits
);
155 assert(src_bits
== 8 || src_bits
== 16 || src_bits
== 32);
156 assert(dst_bits
== 8 || dst_bits
== 16 || dst_bits
== 32);
158 if (src_bits
== dst_bits
)
161 const unsigned dst_components
=
162 DIV_ROUND_UP(src
->num_components
* src_bits
, dst_bits
);
163 assert(dst_components
<= 4);
165 nir_ssa_def
*dst_chan
[4] = {0};
166 if (dst_bits
> src_bits
) {
168 unsigned dst_idx
= 0;
169 for (unsigned i
= 0; i
< src
->num_components
; i
++) {
170 nir_ssa_def
*shifted
= nir_ishl(b
, nir_channel(b
, src
, i
),
171 nir_imm_int(b
, shift
));
173 dst_chan
[dst_idx
] = shifted
;
175 dst_chan
[dst_idx
] = nir_ior(b
, dst_chan
[dst_idx
], shifted
);
179 if (shift
>= dst_bits
) {
185 nir_ssa_def
*mask
= nir_imm_int(b
, ~0u >> (32 - dst_bits
));
187 unsigned src_idx
= 0;
189 for (unsigned i
= 0; i
< dst_components
; i
++) {
190 dst_chan
[i
] = nir_iand(b
, nir_ushr(b
, nir_channel(b
, src
, src_idx
),
191 nir_imm_int(b
, shift
)),
194 if (shift
>= src_bits
) {
201 return nir_vec(b
, dst_chan
, dst_components
);
204 static inline nir_ssa_def
*
205 _nir_format_norm_factor(nir_builder
*b
, unsigned *bits
,
206 unsigned num_components
,
209 nir_const_value factor
;
210 for (unsigned i
= 0; i
< num_components
; i
++) {
211 assert(bits
[i
] < 32);
212 factor
.f32
[i
] = (1ul << (bits
[i
] - is_signed
)) - 1;
214 return nir_build_imm(b
, num_components
, 32, factor
);
217 static inline nir_ssa_def
*
218 nir_format_unorm_to_float(nir_builder
*b
, nir_ssa_def
*u
, unsigned *bits
)
220 nir_ssa_def
*factor
=
221 _nir_format_norm_factor(b
, bits
, u
->num_components
, false);
223 return nir_fdiv(b
, nir_u2f32(b
, u
), factor
);
226 static inline nir_ssa_def
*
227 nir_format_snorm_to_float(nir_builder
*b
, nir_ssa_def
*s
, unsigned *bits
)
229 nir_ssa_def
*factor
=
230 _nir_format_norm_factor(b
, bits
, s
->num_components
, true);
232 return nir_fmax(b
, nir_fdiv(b
, nir_i2f32(b
, s
), factor
),
233 nir_imm_float(b
, -1.0f
));
236 static inline nir_ssa_def
*
237 nir_format_float_to_unorm(nir_builder
*b
, nir_ssa_def
*f
, unsigned *bits
)
239 nir_ssa_def
*factor
=
240 _nir_format_norm_factor(b
, bits
, f
->num_components
, false);
242 /* Clamp to the range [0, 1] */
245 return nir_f2u32(b
, nir_fround_even(b
, nir_fmul(b
, f
, factor
)));
248 static inline nir_ssa_def
*
249 nir_format_float_to_snorm(nir_builder
*b
, nir_ssa_def
*f
, unsigned *bits
)
251 nir_ssa_def
*factor
=
252 _nir_format_norm_factor(b
, bits
, f
->num_components
, true);
254 /* Clamp to the range [-1, 1] */
255 f
= nir_fmin(b
, nir_fmax(b
, f
, nir_imm_float(b
, -1)), nir_imm_float(b
, 1));
257 return nir_f2i32(b
, nir_fround_even(b
, nir_fmul(b
, f
, factor
)));
260 static inline nir_ssa_def
*
261 nir_format_linear_to_srgb(nir_builder
*b
, nir_ssa_def
*c
)
263 nir_ssa_def
*linear
= nir_fmul(b
, c
, nir_imm_float(b
, 12.92f
));
264 nir_ssa_def
*curved
=
265 nir_fsub(b
, nir_fmul(b
, nir_imm_float(b
, 1.055f
),
266 nir_fpow(b
, c
, nir_imm_float(b
, 1.0 / 2.4))),
267 nir_imm_float(b
, 0.055f
));
269 return nir_fsat(b
, nir_bcsel(b
, nir_flt(b
, c
, nir_imm_float(b
, 0.0031308f
)),
273 static inline nir_ssa_def
*
274 nir_format_srgb_to_linear(nir_builder
*b
, nir_ssa_def
*c
)
276 nir_ssa_def
*linear
= nir_fdiv(b
, c
, nir_imm_float(b
, 12.92f
));
277 nir_ssa_def
*curved
=
278 nir_fpow(b
, nir_fdiv(b
, nir_fadd(b
, c
, nir_imm_float(b
, 0.055f
)),
279 nir_imm_float(b
, 1.055f
)),
280 nir_imm_float(b
, 2.4f
));
282 return nir_fsat(b
, nir_bcsel(b
, nir_fge(b
, nir_imm_float(b
, 0.04045f
), c
),
286 static inline nir_ssa_def
*
287 nir_format_unpack_11f11f10f(nir_builder
*b
, nir_ssa_def
*packed
)
289 nir_ssa_def
*chans
[3];
290 chans
[0] = nir_mask_shift(b
, packed
, 0x000007ff, 4);
291 chans
[1] = nir_mask_shift(b
, packed
, 0x003ff800, -7);
292 chans
[2] = nir_mask_shift(b
, packed
, 0xffc00000, -17);
294 for (unsigned i
= 0; i
< 3; i
++)
295 chans
[i
] = nir_unpack_half_2x16_split_x(b
, chans
[i
]);
297 return nir_vec(b
, chans
, 3);
300 static inline nir_ssa_def
*
301 nir_format_pack_11f11f10f(nir_builder
*b
, nir_ssa_def
*color
)
303 /* 10 and 11-bit floats are unsigned. Clamp to non-negative */
304 nir_ssa_def
*clamped
= nir_fmax(b
, color
, nir_imm_float(b
, 0));
306 nir_ssa_def
*undef
= nir_ssa_undef(b
, 1, color
->bit_size
);
307 nir_ssa_def
*p1
= nir_pack_half_2x16_split(b
, nir_channel(b
, clamped
, 0),
308 nir_channel(b
, clamped
, 1));
309 nir_ssa_def
*p2
= nir_pack_half_2x16_split(b
, nir_channel(b
, clamped
, 2),
312 /* A 10 or 11-bit float has the same exponent as a 16-bit float but with
313 * fewer mantissa bits and no sign bit. All we have to do is throw away
314 * the sign bit and the bottom mantissa bits and shift it into place.
316 nir_ssa_def
*packed
= nir_imm_int(b
, 0);
317 packed
= nir_mask_shift_or(b
, packed
, p1
, 0x00007ff0, -4);
318 packed
= nir_mask_shift_or(b
, packed
, p1
, 0x7ff00000, -9);
319 packed
= nir_mask_shift_or(b
, packed
, p2
, 0x00007fe0, 17);
324 static inline nir_ssa_def
*
325 nir_format_pack_r9g9b9e5(nir_builder
*b
, nir_ssa_def
*color
)
327 /* See also float3_to_rgb9e5 */
329 /* First, we need to clamp it to range. */
330 nir_ssa_def
*clamped
= nir_fmin(b
, color
, nir_imm_float(b
, MAX_RGB9E5
));
332 /* Get rid of negatives and NaN */
333 clamped
= nir_bcsel(b
, nir_ult(b
, nir_imm_int(b
, 0x7f800000), color
),
334 nir_imm_float(b
, 0), clamped
);
336 /* maxrgb.u = MAX3(rc.u, gc.u, bc.u); */
337 nir_ssa_def
*maxu
= nir_umax(b
, nir_channel(b
, clamped
, 0),
338 nir_umax(b
, nir_channel(b
, clamped
, 1),
339 nir_channel(b
, clamped
, 2)));
341 /* maxrgb.u += maxrgb.u & (1 << (23-9)); */
342 maxu
= nir_iadd(b
, maxu
, nir_iand(b
, maxu
, nir_imm_int(b
, 1 << 14)));
344 /* exp_shared = MAX2((maxrgb.u >> 23), -RGB9E5_EXP_BIAS - 1 + 127) +
345 * 1 + RGB9E5_EXP_BIAS - 127;
347 nir_ssa_def
*exp_shared
=
348 nir_iadd(b
, nir_umax(b
, nir_ushr(b
, maxu
, nir_imm_int(b
, 23)),
349 nir_imm_int(b
, -RGB9E5_EXP_BIAS
- 1 + 127)),
350 nir_imm_int(b
, 1 + RGB9E5_EXP_BIAS
- 127));
352 /* revdenom_biasedexp = 127 - (exp_shared - RGB9E5_EXP_BIAS -
353 * RGB9E5_MANTISSA_BITS) + 1;
355 nir_ssa_def
*revdenom_biasedexp
=
356 nir_isub(b
, nir_imm_int(b
, 127 + RGB9E5_EXP_BIAS
+
357 RGB9E5_MANTISSA_BITS
+ 1),
360 /* revdenom.u = revdenom_biasedexp << 23; */
361 nir_ssa_def
*revdenom
=
362 nir_ishl(b
, revdenom_biasedexp
, nir_imm_int(b
, 23));
364 /* rm = (int) (rc.f * revdenom.f);
365 * gm = (int) (gc.f * revdenom.f);
366 * bm = (int) (bc.f * revdenom.f);
368 nir_ssa_def
*mantissa
=
369 nir_f2i32(b
, nir_fmul(b
, clamped
, revdenom
));
371 /* rm = (rm & 1) + (rm >> 1);
372 * gm = (gm & 1) + (gm >> 1);
373 * bm = (bm & 1) + (bm >> 1);
375 mantissa
= nir_iadd(b
, nir_iand(b
, mantissa
, nir_imm_int(b
, 1)),
376 nir_ushr(b
, mantissa
, nir_imm_int(b
, 1)));
378 nir_ssa_def
*packed
= nir_channel(b
, mantissa
, 0);
379 packed
= nir_mask_shift_or(b
, packed
, nir_channel(b
, mantissa
, 1), ~0, 9);
380 packed
= nir_mask_shift_or(b
, packed
, nir_channel(b
, mantissa
, 2), ~0, 18);
381 packed
= nir_mask_shift_or(b
, packed
, exp_shared
, ~0, 27);