src/compiler/nir/nir_format_convert.h

   1 /*
   2  * Copyright © 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "nir_builder.h"
  25
  26 #include "util/format_rgb9e5.h"
  27
  28 static inline nir_ssa_def *
  29 nir_shift(nir_builder *b, nir_ssa_def *value, int left_shift)
  30 {
  31    if (left_shift > 0)
  32       return nir_ishl(b, value, nir_imm_int(b, left_shift));
  33    else if (left_shift < 0)
  34       return nir_ushr(b, value, nir_imm_int(b, -left_shift));
  35    else
  36       return value;
  37 }
  38
  39 static inline nir_ssa_def *
  40 nir_mask_shift(struct nir_builder *b, nir_ssa_def *src,
  41                uint32_t mask, int left_shift)
  42 {
  43    return nir_shift(b, nir_iand(b, src, nir_imm_int(b, mask)), left_shift);
  44 }
  45
  46 static inline nir_ssa_def *
  47 nir_mask_shift_or(struct nir_builder *b, nir_ssa_def *dst, nir_ssa_def *src,
  48                   uint32_t src_mask, int src_left_shift)
  49 {
  50    return nir_ior(b, nir_mask_shift(b, src, src_mask, src_left_shift), dst);
  51 }
  52
  53 static inline nir_ssa_def *
  54 nir_format_unpack_uint(nir_builder *b, nir_ssa_def *packed,
  55                        const unsigned *bits, unsigned num_components)
  56 {
  57    assert(num_components >= 1 && num_components <= 4);
  58    nir_ssa_def *comps[4];
  59
  60    if (bits[0] >= packed->bit_size) {
  61       assert(bits[0] == packed->bit_size);
  62       assert(num_components == 1);
  63       return packed;
  64    }
  65
  66    unsigned offset = 0;
  67    for (unsigned i = 0; i < num_components; i++) {
  68       assert(bits[i] < 32);
  69       nir_ssa_def *mask = nir_imm_int(b, (1u << bits[i]) - 1);
  70       comps[i] = nir_iand(b, nir_shift(b, packed, -offset), mask);
  71       offset += bits[i];
  72    }
  73    assert(offset <= packed->bit_size);
  74
  75    return nir_vec(b, comps, num_components);
  76 }
  77
  78 static inline nir_ssa_def *
  79 nir_format_pack_uint_unmasked(nir_builder *b, nir_ssa_def *color,
  80                               const unsigned *bits, unsigned num_components)
  81 {
  82    assert(num_components >= 1 && num_components <= 4);
  83    nir_ssa_def *packed = nir_imm_int(b, 0);
  84    unsigned offset = 0;
  85    for (unsigned i = 0; i < num_components; i++) {
  86       packed = nir_ior(b, packed, nir_shift(b, nir_channel(b, color, i),
  87                                                offset));
  88       offset += bits[i];
  89    }
  90    assert(offset <= packed->bit_size);
  91
  92    return packed;
  93 }
  94
  95 static inline nir_ssa_def *
  96 nir_format_pack_uint(nir_builder *b, nir_ssa_def *color,
  97                      const unsigned *bits, unsigned num_components)
  98 {
  99    nir_const_value mask;
 100    for (unsigned i = 0; i < num_components; i++) {
 101       assert(bits[i] < 32);
 102       mask.u32[i] = (1u << bits[i]) - 1;
 103    }
 104    nir_ssa_def *mask_imm = nir_build_imm(b, num_components, 32, mask);
 105
 106    return nir_format_pack_uint_unmasked(b, nir_iand(b, color, mask_imm),
 107                                         bits, num_components);
 108 }
 109
 110 static inline nir_ssa_def *
 111 nir_format_linear_to_srgb(nir_builder *b, nir_ssa_def *c)
 112 {
 113    nir_ssa_def *linear = nir_fmul(b, c, nir_imm_float(b, 12.92f));
 114    nir_ssa_def *curved =
 115       nir_fsub(b, nir_fmul(b, nir_imm_float(b, 1.055f),
 116                               nir_fpow(b, c, nir_imm_float(b, 1.0 / 2.4))),
 117                   nir_imm_float(b, 0.055f));
 118
 119    return nir_fsat(b, nir_bcsel(b, nir_flt(b, c, nir_imm_float(b, 0.0031308f)),
 120                                    linear, curved));
 121 }
 122
 123 static inline nir_ssa_def *
 124 nir_format_srgb_to_linear(nir_builder *b, nir_ssa_def *c)
 125 {
 126    nir_ssa_def *linear = nir_fdiv(b, c, nir_imm_float(b, 12.92f));
 127    nir_ssa_def *curved =
 128       nir_fpow(b, nir_fdiv(b, nir_fadd(b, c, nir_imm_float(b, 0.055f)),
 129                               nir_imm_float(b, 1.055f)),
 130                   nir_imm_float(b, 2.4f));
 131
 132    return nir_fsat(b, nir_bcsel(b, nir_fge(b, nir_imm_float(b, 0.04045f), c),
 133                                    linear, curved));
 134 }
 135
 136 static inline nir_ssa_def *
 137 nir_format_unpack_11f11f10f(nir_builder *b, nir_ssa_def *packed)
 138 {
 139    nir_ssa_def *chans[3];
 140    chans[0] = nir_mask_shift(b, packed, 0x000007ff, 4);
 141    chans[1] = nir_mask_shift(b, packed, 0x003ff100, -7);
 142    chans[2] = nir_mask_shift(b, packed, 0xffc00000, -17);
 143
 144    for (unsigned i = 0; i < 3; i++)
 145       chans[i] = nir_unpack_half_2x16_split_x(b, chans[i]);
 146
 147    return nir_vec(b, chans, 3);
 148 }
 149
 150 static inline nir_ssa_def *
 151 nir_format_pack_r11g11b10f(nir_builder *b, nir_ssa_def *color)
 152 {
 153    /* 10 and 11-bit floats are unsigned.  Clamp to non-negative */
 154    nir_ssa_def *clamped = nir_fmax(b, color, nir_imm_float(b, 0));
 155
 156    nir_ssa_def *undef = nir_ssa_undef(b, 1, color->bit_size);
 157    nir_ssa_def *p1 = nir_pack_half_2x16_split(b, nir_channel(b, clamped, 0),
 158                                                  nir_channel(b, clamped, 1));
 159    nir_ssa_def *p2 = nir_pack_half_2x16_split(b, nir_channel(b, clamped, 2),
 160                                                  undef);
 161
 162    /* A 10 or 11-bit float has the same exponent as a 16-bit float but with
 163     * fewer mantissa bits and no sign bit.  All we have to do is throw away
 164     * the sign bit and the bottom mantissa bits and shift it into place.
 165     */
 166    nir_ssa_def *packed = nir_imm_int(b, 0);
 167    packed = nir_mask_shift_or(b, packed, p1, 0x00007ff0, -4);
 168    packed = nir_mask_shift_or(b, packed, p1, 0x7ff00000, -9);
 169    packed = nir_mask_shift_or(b, packed, p2, 0x00007fe0, 17);
 170
 171    return packed;
 172 }
 173
 174 static inline nir_ssa_def *
 175 nir_format_pack_r9g9b9e5(nir_builder *b, nir_ssa_def *color)
 176 {
 177    /* See also float3_to_rgb9e5 */
 178
 179    /* First, we need to clamp it to range. */
 180    nir_ssa_def *clamped = nir_fmin(b, color, nir_imm_float(b, MAX_RGB9E5));
 181
 182    /* Get rid of negatives and NaN */
 183    clamped = nir_bcsel(b, nir_ult(b, nir_imm_int(b, 0x7f800000), color),
 184                           nir_imm_float(b, 0), clamped);
 185
 186    /* maxrgb.u = MAX3(rc.u, gc.u, bc.u); */
 187    nir_ssa_def *maxu = nir_umax(b, nir_channel(b, clamped, 0),
 188                        nir_umax(b, nir_channel(b, clamped, 1),
 189                                    nir_channel(b, clamped, 2)));
 190
 191    /* maxrgb.u += maxrgb.u & (1 << (23-9)); */
 192    maxu = nir_iadd(b, maxu, nir_iand(b, maxu, nir_imm_int(b, 1 << 14)));
 193
 194    /* exp_shared = MAX2((maxrgb.u >> 23), -RGB9E5_EXP_BIAS - 1 + 127) +
 195     *              1 + RGB9E5_EXP_BIAS - 127;
 196     */
 197    nir_ssa_def *exp_shared =
 198       nir_iadd(b, nir_umax(b, nir_ushr(b, maxu, nir_imm_int(b, 23)),
 199                               nir_imm_int(b, -RGB9E5_EXP_BIAS - 1 + 127)),
 200                   nir_imm_int(b, 1 + RGB9E5_EXP_BIAS - 127));
 201
 202    /* revdenom_biasedexp = 127 - (exp_shared - RGB9E5_EXP_BIAS -
 203     *                             RGB9E5_MANTISSA_BITS) + 1;
 204     */
 205    nir_ssa_def *revdenom_biasedexp =
 206       nir_isub(b, nir_imm_int(b, 127 + RGB9E5_EXP_BIAS +
 207                                  RGB9E5_MANTISSA_BITS + 1),
 208                   exp_shared);
 209
 210    /* revdenom.u = revdenom_biasedexp << 23; */
 211    nir_ssa_def *revdenom =
 212       nir_ishl(b, revdenom_biasedexp, nir_imm_int(b, 23));
 213
 214    /* rm = (int) (rc.f * revdenom.f);
 215     * gm = (int) (gc.f * revdenom.f);
 216     * bm = (int) (bc.f * revdenom.f);
 217     */
 218    nir_ssa_def *mantissa =
 219       nir_f2i32(b, nir_fmul(b, clamped, revdenom));
 220
 221    /* rm = (rm & 1) + (rm >> 1);
 222     * gm = (gm & 1) + (gm >> 1);
 223     * bm = (bm & 1) + (bm >> 1);
 224     */
 225    mantissa = nir_iadd(b, nir_iand(b, mantissa, nir_imm_int(b, 1)),
 226                           nir_ushr(b, mantissa, nir_imm_int(b, 1)));
 227
 228    nir_ssa_def *packed = nir_channel(b, mantissa, 0);
 229    packed = nir_mask_shift_or(b, packed, nir_channel(b, mantissa, 1), ~0, 9);
 230    packed = nir_mask_shift_or(b, packed, nir_channel(b, mantissa, 2), ~0, 18);
 231    packed = nir_mask_shift_or(b, packed, exp_shared, ~0, 27);
 232
 233    return packed;
 234 }